From gerrit at coreboot.org Wed Feb 1 06:13:40 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:40 +0100 Subject: [coreboot] New patch to review for coreboot: 425158e CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/602 -gerrit commit 425158e483eb7ea8a5faf742742b42396ecd8fd4 Author: Kerry Sheh Date: Wed Feb 1 14:07:38 2012 +0800 CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir AGESA and CIMX build changed from commit 2a830d0b, sb800 and sb900 CIMX dir already traversed in vendorcode Makefile. Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/southbridge/amd/cimx/sb800/Makefile.inc | 1 - src/southbridge/amd/cimx/sb900/Makefile.inc | 1 - 2 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 48b198d..30d2133 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -17,7 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800 # SB800 Platform Files diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index 4a8da05..49eb604 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -17,7 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900 # SB900 Platform Files From gerrit at coreboot.org Wed Feb 1 06:13:40 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:40 +0100 Subject: [coreboot] Patch set updated for coreboot: cd71eb2 Mainboard: Supermicro/h8qgi mainboard update References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567 -gerrit commit cd71eb2ca5f4da5af050e606e608345c5933164d Author: Kerry Sheh Date: Wed Feb 1 13:59:01 2012 +0800 Mainboard: Supermicro/h8qgi mainboard update 1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 2 +- src/mainboard/supermicro/h8qgi/Kconfig | 20 +- src/mainboard/supermicro/h8qgi/Makefile.inc | 18 ++- src/mainboard/supermicro/h8qgi/OptionsIds.h | 2 +- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/ide.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/routing.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/sata.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/usb.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi_tables.c | 95 +++++--- src/mainboard/supermicro/h8qgi/agesawrapper.c | 147 ++++++++----- src/mainboard/supermicro/h8qgi/agesawrapper.h | 2 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 124 +++++++++-- src/mainboard/supermicro/h8qgi/chip.h | 2 +- src/mainboard/supermicro/h8qgi/cmos.layout | 2 +- src/mainboard/supermicro/h8qgi/devicetree.cb | 86 ++------ src/mainboard/supermicro/h8qgi/dimmSpd.c | 50 ++-- src/mainboard/supermicro/h8qgi/dsdt.asl | 217 +++++++----------- src/mainboard/supermicro/h8qgi/fadt.c | 61 ++---- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 30 +-- src/mainboard/supermicro/h8qgi/irq_tables.c | 8 +- src/mainboard/supermicro/h8qgi/mainboard.c | 40 +++-- src/mainboard/supermicro/h8qgi/mptable.c | 59 +++--- src/mainboard/supermicro/h8qgi/platform_cfg.h | 54 +++++ src/mainboard/supermicro/h8qgi/platform_oem.c | 4 +- src/mainboard/supermicro/h8qgi/platform_oem.h | 29 --- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 274 +++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/rd890_cfg.h | 174 ++++++++++++++ src/mainboard/supermicro/h8qgi/reset.c | 66 ++++++ src/mainboard/supermicro/h8qgi/romstage.c | 79 +++++-- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 142 ++++++++++++ src/mainboard/supermicro/h8qgi/sb700_cfg.h | 237 ++++++++++++++++++++ 33 files changed, 1504 insertions(+), 532 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index b7f0124..e83d1f0 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h index 24a05fb..aa2d451 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig old mode 100755 new mode 100644 index 5df0bb4..e900ea8 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select CPU_AMD_AGESA_FAMILY10 - select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX - select NORTHBRIDGE_AMD_AGESA_FAMILY10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_HARD_RESET select SERIAL_CPU_INIT - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 + select TINY_BOOTBLOCK #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default supermicro/h8qgi diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc old mode 100755 new mode 100644 index b09c5ca..82264a4 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,15 +17,31 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c +ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += platform_oem.c +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx +AGESA_ROOT ?= $(AGESA_PREFIX)/f15 +NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890 +SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700 + +subdirs-y += ../../../../$(AGESA_ROOT) +#subdirs-y += ../../../../$(NB_CIMX_ROOT) +#subdirs-y += ../../../../$(SB_CIMX_ROOT) + diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h index eb756df..c4441e9 100644 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl old mode 100755 new mode 100644 index 5eca9cc..2cb7aeb --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl old mode 100755 new mode 100644 index c79c18c..45303c0 --- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl old mode 100755 new mode 100644 index 8bc06f6..817f0f7 --- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl old mode 100755 new mode 100644 index bd4acf0..9ce8650 --- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl old mode 100755 new mode 100644 index 81ea9a2..099e7ac --- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index b8ce0b0..7314283 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end) #endif extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) #else apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif - apicid_sr5650 = apicid_sp5100 + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -89,18 +89,18 @@ unsigned long acpi_fill_madt(unsigned long current) 0 ); - /* IOAPIC on rs5690 */ - gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, dword, gsi_base ); - } + } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, //BUS @@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - //acpi_header_t *ssdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - /* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */ -#ifdef UNUSED_CODE - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); ssdt = (acpi_header_t *) current; - current += ssdt->length; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } - else { + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #endif - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 5bb4a9d..dbdd9d7 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,7 +34,6 @@ #include "Dispatcher.h" #include "cpuCacheInit.h" #include "amdlib.h" -#include "platform_oem.h" #include "Filecode.h" #include "heapManager.h" #include /* CPU_SPECIFIC_SERVICES */ @@ -54,7 +53,7 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -//VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL; /*---------------------------------------------------------------------------------------- @@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); static UINT32 agesawrapper_amdinitcpuio(VOID) { @@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) UINT32 node; UINT32 sblink; UINT32 i; + UINT32 TOM; /* get the number of coherent nodes in the system */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); @@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) PciData = 0x00000A03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set F0000000-FFFFFFFF to Node0 sbLink. */ + /* Set TOM1-FFFFFFFF to Node0 sbLink. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); PciData = 0x00FFFF00; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciData = 0x00F00000 | 0x03; + TOM = (UINT32)MsrRead(TOP_MEM); + PciData = (TOM >> 8) | 0x03; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */ + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x0000E000; + PciData = 0x00FFF000; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00009033; + PciData = 0x00000033; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800; + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; @@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID) AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdResetParams.HtConfig.Depth = 0; //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default @@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly(AmdEarlyParamsPtr); - status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + status = AmdInitEarly(AmdEarlyParamsPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID) UINT16 i; UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr; UINT32 TscRateInMhz; CPU_SPECIFIC_SERVICES *FamilySpecificServices; @@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + if (status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + } AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID) BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParams; LibAmdMemFill(&AmdParamStruct, 0, @@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitEnv(EnvParams); if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return (UINT32)status; @@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick) return AcpiWheaMce; case PICK_WHEA_CMC: return AcpiWheaCmc; -/* case PICK_ALIB: return AcpiAlib; -*/ default: return NULL; } @@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); @@ -405,34 +426,49 @@ UINT32 agesawrapper_amdinitmid(VOID) UINT32 agesawrapper_amdinitlate(VOID) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - Status = AmdInitLate(&AmdLateParams); + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); ASSERT(Status == AGESA_SUCCESS); } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - //AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } @@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr) ASSERT(Status <= AGESA_UNSUPPORTED); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - // AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } @@ -784,9 +811,9 @@ static void agesa_error(EVENT_PARAMS *event) printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); break; - case MEM_ERROR_ECC_DIS: - printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); - break; +// case MEM_ERROR_ECC_DIS: +// printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); +// break; case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); @@ -1141,6 +1168,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) */ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) { + printk(BIOS_DEBUG, "enter in %s\n", __func__); AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; @@ -1164,6 +1192,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } + printk(BIOS_DEBUG, "exit %s \n", __func__); return (UINT32)Status; } diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h index 43c7d10..c1eb012 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 02cf79b..480c7b6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -70,7 +70,10 @@ ////#define BLDOPT_REMOVE_SLIT TRUE //#define BLDOPT_REMOVE_WHEA TRUE //#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + +/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + //#define BLDOPT_REMOVE_HT_ASSIST TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE @@ -107,7 +110,7 @@ #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] = {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + /* Coherent link deemphasis. */ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3}, @@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] = {HT_SOCKET3, HT_LINK1B, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3A, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, - }; CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = { - {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull}, + {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818}, {CPU_LIST_TERMINAL} }; @@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET FALSE//TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE #define AGESA_ENTRY_INIT_RECOVERY FALSE #define AGESA_ENTRY_INIT_EARLY TRUE #define AGESA_ENTRY_INIT_POST TRUE @@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +/* +#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#endif +#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#endif +*/ + +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ #include "MaranelloInstall.h" /*---------------------------------------------------------------------------------------- @@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = *---------------------------------------------------------------------------------------- */ +//reference BKDG Table87: works +#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM. +#define SEED_A 0x54 +#define SEED_B 0x4D +#define SEED_C 0x45 +#define SEED_D 0x40 + +#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM. +//4B 41 51 + /* * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable @@ -486,6 +528,53 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // +#if 0//CONFIG_CPU_AMD_AGESA_FAMILY10 + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, + * Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, F10_WL_SEED, F10_WL_SEED, + F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, + F10_WL_SEED, F10_WL_SEED, F10_WL_SEED), +#endif + +#if 0 //CONFIG_CPU_AMD_AGESA_FAMILY15 + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED), + + /* HW_RXEN_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + */ + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_B, ALL_DIMMS, + SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, + SEED_B), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_C, ALL_DIMMS, + SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, + SEED_C), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_D, ALL_DIMMS, + SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, + SEED_D), +#endif + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 PSO_END }; @@ -493,7 +582,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { /* * These tables are optional and may be used to adjust memory timing settings */ - //HY Customer table UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h index a252705..1181130 100644 --- a/src/mainboard/supermicro/h8qgi/chip.h +++ b/src/mainboard/supermicro/h8qgi/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout old mode 100755 new mode 100644 index 3b98cbb..0fd4708 --- a/src/mainboard/supermicro/h8qgi/cmos.layout +++ b/src/mainboard/supermicro/h8qgi/cmos.layout @@ -2,7 +2,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb old mode 100755 new mode 100644 index 9afaac7..9d77a73 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,20 +16,18 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa/family10/root_complex +chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa/family10 - device lapic 0x10 on end + chip cpu/amd/agesa/family15 + device lapic 0x20 on end #f15 + #device lapic 0x10 on end #f10 end end device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3 - chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 @@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 register "port_enable" = "0x2104" - end #southbridge/amd/sr5650 - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB1 device pci 12.1 on end # USB1 @@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex device pci 13.1 on end # USB2 device pci 13.2 on end # USB2 device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec. + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8qgi not have codec. device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy @@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/sp5100 + end # southbridge/amd/cimx/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - - - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3 - end - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - - device pci 1b.0 on end - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - - - device pci 1c.0 on end - device pci 1c.1 on end - device pci 1c.2 on end - device pci 1c.3 on end - device pci 1c.4 on end - - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.4 on end - - - device pci 1e.0 on end - device pci 1e.1 on end - device pci 1e.2 on end - device pci 1e.3 on end - device pci 1e.4 on end - - device pci 1f.0 on end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.4 on end - - end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex + device pci 18.5 on end #f15 + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #pci_domain -end #northbridge/amd/agesa/family10/root_complex +end #northbridge/amd/agesa/family15/root_complex diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c index 4ff21ee..a838cb4 100644 --- a/src/mainboard/supermicro/h8qgi/dimmSpd.c +++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,14 +38,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA */ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) { - u8 value; - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS - - value = pci_read_config8(sm_dev, reg); - value &= ~(enable); - value |= out; - value &= ~(enable << 4); - pci_write_config8(sm_dev, reg, value); + u8 value; + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + + value = pci_read_config8(sm_dev, reg); + value &= ~(enable); + value |= out; + value &= ~(enable << 4); + pci_write_config8(sm_dev, reg, value); } /*----------------------------------------------------------------------------- @@ -55,31 +55,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm /* socket 0 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 1 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 2 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 3 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, }; diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl old mode 100755 new mode 100644 index ebdb1eb..3f10012 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -988,73 +988,58 @@ DefinitionBlock ( Scope(\_GPE) { /* Start Scope GPE */ /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L00) { + //DBGO("\\_GPE\\_L00\n") + } /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L01) { + //DBGO("\\_GPE\\_L01\n") + } /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L02) { + //DBGO("\\_GPE\\_L02\n") + } /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ + //DBGO("\\_GPE\\_L00\n") Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L04) { + //DBGO("\\_GPE\\_L04\n") + } /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L05) { + //DBGO("\\_GPE\\_L05\n") + } - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ + /* _L06 General event 6 - Used for GPM6, moved to USB.asl */ + /* _L07 General event 7 - Used for GPM7, moved to USB.asl */ /* Legacy PM event */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ + //DBGO("\\_GPE\\_L08\n") } /* Temp warning (TWarn) event */ Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ + //DBGO("\\_GPE\\_L09\n") Notify (\_TZ.TZ00, 0x80) } /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ + Method(_L0A) { + //DBGO("\\_GPE\\_L0A\n") + } /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ + //DBGO("\\_GPE\\_L0B\n") Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -1065,126 +1050,81 @@ DefinitionBlock ( } /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ + Method(_L0C) { + //DBGO("\\_GPE\\_L0C\n") + } /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ + Method(_L0D) { + //DBGO("\\_GPE\\_L0D\n") + } - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ + /* _L0E GPM9 SCI event - Moved to USB.asl */ /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ + Method(_L0F) { + //DBGO("\\_GPE\\_L0F\n") + } /* ExtEvent0 SCI event */ Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ + //DBGO("\\_GPE\\_L10\n") } /* ExtEvent1 SCI event */ Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ + //DBGO("\\_GPE\\_L11\n") } /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ + Method(_L12) { + //DBGO("\\_GPE\\_L12\n") + } - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ + /* _L13 GPM0 SCI event - Moved to USB.asl */ + /* _L14 GPM1 SCI event - Moved to USB.asl */ + /* _L15 GPM2 SCI event - Moved to USB.asl */ + /* _L16 GPM3 SCI event - Moved to USB.asl */ + /* _L17 GPM8 SCI event - Moved to USB.asl */ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ + //DBGO("\\_GPE\\_L18\n") Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ + /* _L19 GPM4 SCI event - Moved to USB.asl */ + /* _L1A GPM5 SCI event - Moved to USB.asl */ /* Azalia SCI event */ Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ + //DBGO("\\_GPE\\_L1B\n") Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ + Method(_L1C) { + //DBGO("\\_GPE\\_L1C\n") + } /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ + Method(_L1D) { + //DBGO("\\_GPE\\_L1D\n") + } /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ + Method(_L1E) { + //DBGO("\\_GPE\\_L1E\n") + } - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ + /* _L1F SATA SCI event - Moved to sata.asl */ } /* End Scope GPE */ @@ -1569,7 +1509,7 @@ DefinitionBlock ( 0x0CF8, // Range Maximum 0x01, // Alignment 0x08, // Length - ) + ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity @@ -1602,10 +1542,10 @@ DefinitionBlock ( ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity - 0x9000, // Range Minimum - 0xefff, // Range Maximum + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum 0x0000, // Translation Offset - 0x6000, // Length + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space @@ -1613,21 +1553,26 @@ DefinitionBlock ( 0xE0000000, // Address Base 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Granularity - 0xF0000000, // Range Minimum - 0xFFFFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x10000000, // Length - ,, , AddressRangeMemory, TypeStatic) }) Method (_CRS, 0, NotSerialized) { CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - Store (PCBA, BAS1) - Store (PCLN, LEN1) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, BAS1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) + //DBGO(TOM1) Return (CRS) } diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index c2f714d..0c63162 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,21 +28,17 @@ #include #include #include -#include "southbridge/amd/sb700/sb700.h" +#include "Platform.h" /*sb700 platform header*/ -u16 pm_base = SB700_ACPI_IO_BASE; -/* pm_base should be set in sb acpi */ -/* pm_base should be got from bar2 of sb700. Here I compact ACPI - * registers into 32 bytes limit. - * */ +#ifndef ACPI_BLK_BASE + #define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); @@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8); - - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ fadt->pm1_evt_len = 4; @@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; @@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; @@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; @@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; @@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 14e6bca..8c31cbf 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,8 +23,10 @@ #include #include #include -#include #include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -34,22 +36,6 @@ u8 bus_isa; u8 bus_sp5100[2]; u8 bus_sr5650[14]; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* - * HT Chain device num, actually it is unit id base of every ht device in chain, - * assume every chain only have 4 ht device at most - */ -u32 hcdnx[] = { - 0x20202020, -}; u32 bus_type[256]; @@ -106,8 +92,7 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff; - // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sr5650[0] = 0; bus_sp5100[0] = bus_sr5650[0]; /* sp5100 */ @@ -151,4 +136,9 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Late_Post(); +#endif } diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 640a0a6..11e5256 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,9 +27,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index f00b5a0..675c87f 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,36 +25,48 @@ #include #include #include -#include "southbridge/amd/sr5650/cmn.h" +#include #include "chip.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); +void set_pcie_dereset(void *nbconfig); +void set_pcie_reset(void *nbconfig); /** * */ -void set_pcie_reset(void) +void set_pcie_reset(void *nbconfig) { } /** + * Mainboard specific RD890 CIMx callback * Release Resets to PCIe Links - * PCIE_RESET_GPIO1,2,4,5 + * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie */ -void set_pcie_dereset(void) +void set_pcie_dereset(void *nbconfig) { - device_t pcie_core_dev; + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007); + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } } /************************************************* -* enable the dedicated function in h8qgi board. -*************************************************/ + * enable the dedicated function in h8qgi board. + *************************************************/ static void h8qgi_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -69,5 +81,5 @@ int add_mainboard_resources(struct lb_memory *mem) struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") - .enable_dev = h8qgi_enable, + .enable_dev = h8qgi_enable, }; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5c01994..92771bd 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,17 +33,16 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; +extern u8 bus_isa; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; device_t dev; u32 dword; - u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); @@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v) #if CONFIG_MAX_CPUS >= 16 apicid_sp5100 = 0x0; #else - apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif apicid_sr5650 = apicid_sp5100 + 1; - //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); +#ifdef UNUSED_CODE + u8 byte; /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); @@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v) dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); +#endif /* * 00:12.0: PROG SATA : INT F @@ -102,11 +103,11 @@ static void *smp_write_config_table(void *v) /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); - } + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); + } } @@ -155,27 +156,27 @@ static void *smp_write_config_table(void *v) * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); + /* PCI_SLOT 0. */ + PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h new file mode 100644 index 0000000..bbc4ad7 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c index f36b0d8..883cad1 100644 --- a/src/mainboard/supermicro/h8qgi/platform_oem.c +++ b/src/mainboard/supermicro/h8qgi/platform_oem.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,6 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "platform_oem.h" #include "Filecode.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -43,6 +42,7 @@ * **/ /*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h deleted file mode 100644 index ab0d6df..0000000 --- a/src/mainboard/supermicro/h8qgi/platform_oem.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_OEM_H_ -#define _PLATFORM_OEM_H_ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -#endif //_PLATFORM_OEM_H_ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c new file mode 100644 index 0000000..7a947b3 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include +#include + +#ifndef __PRE_RAM__ +#include +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h new file mode 100644 index 0000000..8f45019 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c new file mode 100644 index 0000000..68a39f2 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 08b0eb2..119593e 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,34 +29,54 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" -#include "southbridge/amd/sr5650/sr5650.h" -#include "southbridge/amd/sb700/sb700.h" +#include +#include #include "superio/nuvoton/wpcm450/wpcm450.h" +#include "superio/winbond/w83627dhg/w83627dhg.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ +//TODO: should not put here +static void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, base); + reg8 = pci_read_config8(dev, 0x48); + reg8 |= 1 << 2; + pci_write_config8(dev, 0x48, reg8); +} + +static void sb7xx_51xx_disable_wideio(u8 wio_index) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, 0); + reg8 = pci_read_config8(dev, 0x48); + reg8 &= ~(1 << 2); + pci_write_config8(dev, 0x48, reg8); +} + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + post_code(0x30); agesawrapper_amdinitmmio(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - post_code(0x31); - sb7xx_51xx_lpc_port80(); - post_code(0x32); - } + post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); @@ -78,7 +98,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } - post_code(0x38); + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x38); + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + post_code(0x39); + nb_Poweron_Init(); + post_code(0x3A); + sb_Poweron_Init(); + } + post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); @@ -86,12 +118,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } - sr5650_early_setup(); - post_code(0x39); - - sb7xx_51xx_early_setup(); - sr5650_htinit(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + post_code(0x3C); + nb_Ht_Init(); + post_code(0x3D); + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); @@ -103,8 +133,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } - printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); post_code(0x41); val = agesawrapper_amdinitenv(); @@ -114,8 +145,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); post_code(0x50); print_debug("Disabling cache as ram "); diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c new file mode 100644 index 0000000..4cbb8ca --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h new file mode 100644 index 0000000..aac61ec --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_ From gerrit at coreboot.org Wed Feb 1 06:13:41 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:41 +0100 Subject: [coreboot] Patch set updated for coreboot: 22d10e9 SIO: condition compile Nuvoton WPCM450 early_init.c References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/566 -gerrit commit 22d10e91dec3aefb162cba777f32815bd745a295 Author: Kerry Sheh Date: Wed Feb 1 13:59:00 2012 +0800 SIO: condition compile Nuvoton WPCM450 early_init.c Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450 Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/nuvoton/wpcm450/Makefile.inc | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc index c70b2fb..b4e4ea7 100644 --- a/src/superio/nuvoton/wpcm450/Makefile.inc +++ b/src/superio/nuvoton/wpcm450/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2011 Advanced Micro Devices, Inc. +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-y += early_init.c +romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c From gerrit at coreboot.org Wed Feb 1 06:13:42 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:42 +0100 Subject: [coreboot] Patch set updated for coreboot: 6eff497 SIO: Winbond w83627dhg update References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565 -gerrit commit 6eff4971430c641cdba28b38798026bb8f23f7bc Author: Kerry Sheh Date: Wed Feb 1 13:58:57 2012 +0800 SIO: Winbond w83627dhg update 1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/superio/winbond/w83627dhg/Makefile.inc | 2 + src/superio/winbond/w83627dhg/early_serial.c | 29 +++++++++++++++++++++++-- src/superio/winbond/w83627dhg/superio.c | 4 +- src/superio/winbond/w83627dhg/w83627dhg.h | 6 +++++ 6 files changed, 38 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 3183c1c..4a1b1c3 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -39,7 +39,7 @@ #include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627dhg/early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index f2525e3..621c27f 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -40,7 +40,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627dhg/early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc index 0b0bb8b..09df47e 100644 --- a/src/superio/winbond/w83627dhg/Makefile.inc +++ b/src/superio/winbond/w83627dhg/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2008 Uwe Hermann +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,5 +19,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index f530dc6..e0be8de 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Uwe Hermann + * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,24 +19,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include #include #include "w83627dhg.h" -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83627dhg_enable_serial(device_t dev, u16 iobase) +void w83627dhg_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -44,3 +47,23 @@ static void w83627dhg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +/** + * Select Pin 89, Pin 90 function as I2C interface SDA, SCL. + * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or + * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} + */ +void w83627dhg_enable_i2c(device_t dev) +{ + u8 val; + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + + val = pnp_read_config(dev, 0x2A); + val |= 1 << 1; + pnp_write_config(dev, 0x2A, val); + + pnp_exit_ext_func_mode(dev); +} + diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1771c26..a936ce1 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -26,13 +26,13 @@ #include "chip.h" #include "w83627dhg.h" -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { outb(0xaa, dev->path.pnp.port); } diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 74761e9..158e60b 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Uwe Hermann + * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,4 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ +void pnp_enter_ext_func_mode(device_t dev); +void pnp_exit_ext_func_mode(device_t dev); +void w83627dhg_enable_serial(device_t dev, u16 iobase); +void w83627dhg_enable_i2c(device_t dev); + #endif From gerrit at coreboot.org Wed Feb 1 06:13:42 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:42 +0100 Subject: [coreboot] Patch set updated for coreboot: 0dcb076 Mainboard: Add AMD dinar mainboard. References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/564 -gerrit commit 0dcb076b020e1395ec40cea2309d2ce93a80c153 Author: Kerry Sheh Date: Wed Feb 1 13:58:52 2012 +0800 Mainboard: Add AMD dinar mainboard. Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/dinar/BiosCallOuts.c | 563 ++++++ src/mainboard/amd/dinar/BiosCallOuts.h | 79 + src/mainboard/amd/dinar/Kconfig | 211 ++ src/mainboard/amd/dinar/Makefile.inc | 40 + src/mainboard/amd/dinar/Oem.h | 79 + src/mainboard/amd/dinar/OptionsIds.h | 64 + src/mainboard/amd/dinar/PlatformGnbPcie.c | 176 ++ src/mainboard/amd/dinar/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/dinar/acpi/cpstate.asl | 75 + src/mainboard/amd/dinar/acpi/ide.asl | 244 +++ src/mainboard/amd/dinar/acpi/routing.asl | 311 +++ src/mainboard/amd/dinar/acpi/sata.asl | 149 ++ src/mainboard/amd/dinar/acpi/usb.asl | 20 + src/mainboard/amd/dinar/acpi_tables.c | 320 +++ src/mainboard/amd/dinar/agesawrapper.c | 628 ++++++ src/mainboard/amd/dinar/agesawrapper.h | 329 +++ src/mainboard/amd/dinar/buildOpts.c | 483 +++++ src/mainboard/amd/dinar/chip.h | 23 + src/mainboard/amd/dinar/cmos.layout | 118 ++ src/mainboard/amd/dinar/devicetree.cb | 104 + src/mainboard/amd/dinar/dimmSpd.c | 333 +++ src/mainboard/amd/dinar/dsdt.asl | 1157 +++++++++++ src/mainboard/amd/dinar/fadt.c | 173 ++ src/mainboard/amd/dinar/get_bus_conf.c | 156 ++ src/mainboard/amd/dinar/gpio.c | 482 +++++ src/mainboard/amd/dinar/gpio.h | 2329 ++++++++++++++++++++++ src/mainboard/amd/dinar/irq_tables.c | 122 ++ src/mainboard/amd/dinar/mainboard.c | 138 ++ src/mainboard/amd/dinar/mptable.c | 196 ++ src/mainboard/amd/dinar/platform_cfg.h | 54 + src/mainboard/amd/dinar/rd890_cfg.c | 274 +++ src/mainboard/amd/dinar/rd890_cfg.h | 175 ++ src/mainboard/amd/dinar/reset.c | 66 + src/mainboard/amd/dinar/romstage.c | 157 ++ src/mainboard/amd/dinar/sb700_cfg.c | 142 ++ src/mainboard/amd/dinar/sb700_cfg.h | 237 +++ 37 files changed, 10282 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 62ae584..c6de048 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -7,6 +7,8 @@ config BOARD_AMD_DB800 bool "DB800 (Salsa)" config BOARD_AMD_DBM690T bool "DBM690T (Herring)" +config BOARD_AMD_DINAR + bool "Dinar" config BOARD_AMD_MAHOGANY bool "Mahogany" config BOARD_AMD_MAHOGANY_FAM10 @@ -39,6 +41,7 @@ endchoice source "src/mainboard/amd/db800/Kconfig" source "src/mainboard/amd/dbm690t/Kconfig" +source "src/mainboard/amd/dinar/Kconfig" source "src/mainboard/amd/mahogany/Kconfig" source "src/mainboard/amd/mahogany_fam10/Kconfig" source "src/mainboard/amd/norwich/Kconfig" diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c new file mode 100644 index 0000000..39e1d13 --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -0,0 +1,563 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "SB700.h" + +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG24 +#define SB_GPIO_REG24 24 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + break; + } + } + + if(i >= CallOutCount) + { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = AGESA_SUCCESS; + return Status; +} diff --git a/src/mainboard/amd/dinar/BiosCallOuts.h b/src/mainboard/amd/dinar/BiosCallOuts.h new file mode 100644 index 0000000..22451aa --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig new file mode 100644 index 0000000..32382d6 --- /dev/null +++ b/src/mainboard/amd/dinar/Kconfig @@ -0,0 +1,211 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_DINAR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SCH4037 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select BOARD_ROMSIZE_KB_2048 + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select HAVE_ACPI_TABLES + #TODO select HAVE_ACPI_RESUME + select ENABLE_APIC_EXT_ID + select TINY_BOOTBLOCK + select GFXUMA + +config MAINBOARD_DIR + string + default amd/dinar + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Dinar" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 64 + +config MAX_PHYSICAL_CPUS + int + default 16 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + +config SIO_PORT + hex + default 0x2e + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + depends on VGA_BIOS + default "1002,515e" + +config AHCI_BIOS + bool + default y + +config AHCI_BIOS_FILE + string "AHCI ROM path and filename" + depends on AHCI_BIOS + default "site-local/ahci/sb700.bin" + +config AHCI_BIOS_ID + string "AHCI device PCI IDs" + depends on AHCI_BIOS + default "1002,4391" + +config XHC_BIOS + bool + default n + +config XHC_BIOS_FILE + string "XHC BIOS path and filename" + depends on XHC_BIOS + default "site-local/xhc/Xhc.rom" + +config XHC_BIOS_ID + string "XHC device PCI IDs" + depends on XHC_BIOS + default "1022,7812" + +config CONSOLE_POST + bool + depends on !NO_POST + default n + +config SATA_CONTROLLER_MODE + hex + default 0x0 + depends on SOUTHBRIDGE_AMD_CIMX_SB700 + +config ONBOARD_LAN + bool + default y + +config ONBOARD_1394 + bool + default y + +config ONBOARD_USB30 + bool + default n + +config ONBOARD_BLUETOOTH + bool + default y + +config ONBOARD_WEBCAM + bool + default y + +config ONBOARD_TRAVIS + bool + default y + +config ONBOARD_LIGHTSENSOR + bool + default n + +config PCI_ROM_RUN + bool + default n + +config UDELAY_IO + bool + default n + +config REDIRECT_CIMX_TRACE_TO_SERIAL + bool "Redirect CIMX Trace to serial console" + default y + +endif # BOARD_AMD_DINAR diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc new file mode 100644 index 0000000..89e6d42 --- /dev/null +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -0,0 +1,40 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += sb700_cfg.c +romstage-y += rd890_cfg.c +#romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += sb700_cfg.c +ramstage-y += rd890_cfg.c +#ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c + +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ + echo `wrong configuration`) diff --git a/src/mainboard/amd/dinar/Oem.h b/src/mainboard/amd/dinar/Oem.h new file mode 100644 index 0000000..67b1314 --- /dev/null +++ b/src/mainboard/amd/dinar/Oem.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define MOVE_PCIEBAR_TO_F0000000 + +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF8000000 +#else +#define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h new file mode 100644 index 0000000..e1d397e --- /dev/null +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/dinar/PlatformGnbPcie.c b/src/mainboard/amd/dinar/PlatformGnbPcie.c new file mode 100644 index 0000000..277d247 --- /dev/null +++ b/src/mainboard/amd/dinar/PlatformGnbPcie.c @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) + }, + // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) + }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + // { + // DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + // PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), + // PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + // } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) + } +}; + +PCIe_COMPLEX_DESCRIPTOR Llano = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *LlanoPcieComplexListPtr; + VOID *LlanoPciePortPtr; + VOID *LlanoPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return Status; + } + + LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (LlanoPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (LlanoPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 7, + &InitEarly->StdHeader); + + LibAmdMemFill (LlanoPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 6, + &InitEarly->StdHeader); + + LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; +} + diff --git a/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h b/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..c10d251 --- /dev/null +++ b/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl new file mode 100644 index 0000000..ea670a3 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl new file mode 100644 index 0000000..765a67e --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/dinar/acpi/routing.asl b/src/mainboard/amd/dinar/acpi/routing.asl new file mode 100644 index 0000000..c7a9165 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/routing.asl @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + /* Bus 0, Dev 2 */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + /* Bus 0, Dev 3 */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0010FFFF, 0, 0, 18 }, + Package(){0x0010FFFF, 1, 0, 17 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, 0, 19 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* For Device(PBR2) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* For Device(PBR2) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS3, Package(){ + /* For Device(PBR3) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS3, Package(){ + /* For Device(PBR3) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS4, Package(){ + /* For Device(PBR4) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* For Device(PBR4) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* For Device(PBR5) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* For Device(PBR5) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* For Device(PBR6) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* For Device(PBR6) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* For Device(PBR7) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* For Device(PBR7) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* For Device(PE20) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APE0, Package(){ + /* For Device(PE20) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* For Device(PE21) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APE1, Package(){ + /* For Device(PE21) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* For Device(PE22) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APE2, Package(){ + /* For Device(PE22) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* For Device(PE23) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APE3, Package(){ + /* For Device(PE23) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) +} diff --git a/src/mainboard/amd/dinar/acpi/sata.asl b/src/mainboard/amd/dinar/acpi/sata.asl new file mode 100644 index 0000000..32b9cd9 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/dinar/acpi/usb.asl b/src/mainboard/amd/dinar/acpi/usb.asl new file mode 100644 index 0000000..8a87ace --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/usb.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c new file mode 100644 index 0000000..ee00e81 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -0,0 +1,320 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + u32 dword; + u32 gsi_base = 0; + u32 apicid_sb700; + u32 apicid_rd890; + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write sb700 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_sb700, + IO_APIC_ADDR, + 0 + ); + + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* sb700 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_rd890, + dword, + gsi_base + ); + } + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, + 0, //BUS + 0, //SOURCE + 2, //gsirq + 0 //flags + ); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + //acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ +#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); +#endif + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); +#endif + + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c new file mode 100644 index 0000000..afbf108 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -0,0 +1,628 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "heapManager.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ +/* +BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the +MMIO configuration space range. The size of the MMIO configuration space range varies with this +field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows: +Bits Buses Bits Buses +0h 1 5h 32 +1h 2 6h 64 +2h 4 7h 128 +3h 8 8h 256 +4h 16 Fh-9h Reserved +*/ +UINT8 +GetEndBusNum ( + VOID + ) +{ + UINT64 BusNum; + UINT8 Index; + for (Index = 1; Index <= 8; Index ++ ) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1 ) { + break; + } + } + return Index; +} + +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 TopMem; + UINT32 NodeCnt; + UINT32 Node; + UINT32 SbLink; + UINT32 Index; + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4] + /* Find out the Link ID of Node0 that connects to the + * Southbridge (system IO hub). e.g. family10 MCM Processor, + * SbLink is Processor0 Link2, internal Node0 Link3 + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + SbLink = (PciData >> 8) & 3; //assume ganged + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ + for (Node = 0; Node < NodeCnt; Node ++) { + /* clear all MMIO Mapped Base/Limit Registers */ + for (Index = 0; Index < 8; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + /* clear all IO Space Base/Limit Registers */ + for (Index = 0; Index < 4; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* Enable MMIO on AMD CPU Address Map Controller */ + + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80); + PciData = (0xA0000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84); + PciData = 0xB0000 >> 8; + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set UMA MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + TopMem = (UINT32)MsrReg; + MsrReg = (MsrReg >> 8) | 3; + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c); + if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { + PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; + } + else { + PciData = (0x100000000ull - 1) >> 8; + } + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set XAPIC MMIO. 24K */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98); + PciData = (0xFEC00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c); + PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0); + PciData = (0xFEE00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8); + PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0); + PciData = 0x13; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4); + PciData = 0x00FFF000; + PciData &= (~0x7F); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | BIT46; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90); + + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Enable memory access */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); + + PciData |= BIT1; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); +#endif + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; +} + +VOID +OemCustomizeInitPost ( + IN AMD_POST_PARAMS *InitPost + ) +{ + InitPost->MemConfig.UmaMode = UMA_AUTO; + InitPost->MemConfig.BottomIo = 0xE0; + InitPost->MemConfig.UmaSize = 0xE0-0xC0; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + /* OEM Should Customize the defaults through this hook */ + OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + + case PICK_PSTATE: + return AcpiPstate; + + case PICK_SRAT: + return AcpiSrat; + + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate(VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); + if (Status != AGESA_SUCCESS) { + //agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdLateRunApTask (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h new file mode 100644 index 0000000..400e0c0 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* BITS Define */ +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MMIO_NP_BIT BIT7 + +/* Hudson-2 ACPI PmIO Space Define */ +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +//void brazos_platform_stage(void); +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +void sb_After_Pci_Init (void); +void sb_Mid_Post_Init (void); +void sb_Late_Post (void); +UINT32 agesawrapper_amdreadeventlog (void); +UINT32 agesawrapper_amdinitmmio (void); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c new file mode 100644 index 0000000..fd0464d --- /dev/null +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Sabine/Lynx platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ + */ +#include "AGESA.h" +#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ + + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +/* User makes option selections here + * Comment out the items wanted to be included in the build. + * Uncomment those items you with to REMOVE from the build. + */ +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +//#define BLDOPT_REMOVE_SRAT TRUE +//#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +/* Build configuration values here. +*/ +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_PLAT_NUM_IO_APICS 2 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE +#define BLDCFG_ONLINE_SPARE TRUE +#define BLDCFG_MEMORY_PARITY_ENABLE TRUE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION TRUE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 0 +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 +//#define BLDCFG_USE_ATM_MODE TRUE + +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife +//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 + +//#define IDSOPT_IDS_ENABLED TRUE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE +#define BLDCFG_PSTATE_HPC_MODE FALSE + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap +/* + * Agesa entry points used in this implementation. + */ +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "MarG34PI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} + +// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +#define INSTALL_G34_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_10_SUPPORT TRUE +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT +#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE +#undef INSTALL_FAMILY_10_SUPPORT +#define INSTALL_FAMILY_10_SUPPORT FALSE +#endif +#endif + +#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT +#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE +#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE +#endif +#endif + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0xFF) +#define DFLT_SCRUB_L2_RATE (0x10) +#define DFLT_SCRUB_L3_RATE (0x10) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0x12) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define DFLT_VRM_SLEW_RATE (2500) + +/* Process the options... + * This file include MUST occur + AFTER the user option selection settings + */ +CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF +}; + +#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList + +// And another platform specific one ... +//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = +//{ +// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, +// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, +// HT_LIST_TERMINAL +//}; + +CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList + +// A performance-per-watt optimization. +CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, + HT_LIST_TERMINAL, +}; + +// uncomment the line below to make Perf-per-watt enabled by default. +#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt + + +CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList + +CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = +{ + // Source Socket, Link (4-7 are sublink 1), Target Socket + {0, 0, 1}, + {0, 1, 1}, + {0, 3, 1}, + {0, 4, 1}, + {0, 5, 1}, + {0, 7, 1}, +}; + +#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap + +/* + * PCI Bus numbers for Drachma/Peso board + */ +CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = +{ + // Socket, Link, SecBus, SubBus + 0, 2, 0x00, 0xBF, // RD890 of Dinar + 1, 0, 0xC0, 0xFF, // HTX + HT_LIST_TERMINAL +}; + +#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers + +CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = +{ + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, + 0xFF +}; + +#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList +/* + CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = + { +// {socketA, linkA, socketB, linkB} +{0, 0, 1, 1}, +}; + +#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap +*/ + +/* + * Device Capabilities Override for disabling ID Clumping + */ +CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap + + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterfaceStub.h" +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + + // Dinar has the following routing: + // CS0 M[B,A]_CLK_H/L[0] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[1] + // CS3 M[B,A]_CLK_H/L[3] + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//HY Customer table +UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]); +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h new file mode 100644 index 0000000..42630fa --- /dev/null +++ b/src/mainboard/amd/dinar/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout new file mode 100644 index 0000000..5178430 --- /dev/null +++ b/src/mainboard/amd/dinar/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb new file mode 100644 index 0000000..92fe521 --- /dev/null +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -0,0 +1,104 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +chip northbridge/amd/agesa/family15/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on end # Link 0 + device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) + chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 off end # GPP3a Port0 + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 off end # GPP3a Port4 + device pci a.0 off end # GPP3a Port5 + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x2104" + end # northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on # SM + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/smsc/sch4037 # SIO SMSC SCH4037 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + irq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + end #SIO SMSC307 + end #LPC + device pci 14.4 on end # PCI bridge, 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15/root_complex + diff --git a/src/mainboard/amd/dinar/dimmSpd.c b/src/mainboard/amd/dinar/dimmSpd.c new file mode 100644 index 0000000..f26ec20 --- /dev/null +++ b/src/mainboard/amd/dinar/dimmSpd.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define SMBUS_BASE_ADDR 0xB00 +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define LTC4305_SMBUS_ADDR 0x94 + +typedef struct _DIMM_INFO_SMBUS{ + UINT8 SocketId; + UINT8 MemChannelId; + UINT8 DimmId; + UINT8 SmbusAddress; +} DIMM_INFO_SMBUS; +/* + * SPD address table - porting required + */ +STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = +{ + /* Socket, Channel, Dimm, Smbus */ + {0, 0, 0, 0xAC}, + {0, 0, 1, 0xAE}, + {0, 1, 0, 0xA8}, + {0, 1, 1, 0xAA}, + {0, 2, 0, 0xA4}, + {0, 2, 1, 0xA6}, + {0, 3, 0, 0xA0}, + {0, 3, 1, 0xA2}, + {1, 0, 0, 0xAC}, + {1, 0, 1, 0xAE}, + {1, 1, 0, 0xA8}, + {1, 1, 1, 0xAA}, + {1, 2, 0, 0xA4}, + {1, 2, 1, 0xA6}, + {1, 3, 0, 0xA0}, + {1, 3, 1, 0xA2} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +STATIC +VOID +WritePmReg ( + IN UINT8 Reg, + IN UINT8 Data + ) +{ + __outbyte (0xCD6, Reg); + __outbyte (0xCD7, Data); +} +STATIC +VOID +SetupFch ( + IN UINT16 + IN IoBase + ) +{ + + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + /* set SMBus clock to 400 KHz */ + __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4); +} + +/* + * + * ReadSmbusByteData - read a single SPD byte from any offset + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + + Address |= 1; // set read bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and read bit + __outbyte (Iobase + 2, 0x48); // read byte command + + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + *ByteData = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} +/* + * + * WriteSmbusByteData - Write a single SPD byte onto any offset + * + */ +STATIC +AGESA_STATUS +WriteSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + IN UINT8 ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + Address &= 0xFE; // set write bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and write bit + __outbyte (Iobase + 5, ByteData); // offset in byte data // + __outbyte (Iobase + 2, 0x48); // write byte command + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByte ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *Buffer + ) +{ + UINTN Status; + UINT64 Limit; + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + Buffer [0] = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSpd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + * + */ + +STATIC +AGESA_STATUS +ReadSpd ( + IN UINT16 IoBase, + IN UINT8 SmbusSlaveAddress, + OUT UINT8 *Buffer, + IN UINTN Count + ) +{ + UINTN Index, Status; + + /* read the first byte using offset zero */ + Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0); + if (Status) return Status; + + /* read the remaining bytes using auto-increment for speed */ + for (Index = 1; Index < Count; Index++){ + Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]); + if (Status) return Status; + } + return 0; +} + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ) +{ + AGESA_STATUS Status; + UINT8 SmBusAddress = 0; + UINTN Index; + UINTN MaxSocket = DIMENSION (SpdAddrLookup); + + for (Index = 0; Index < MaxSocket; Index ++){ + if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && + (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && + (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { + SmBusAddress = SpdAddrLookup[Index].SmbusAddress; + break; + } + } + + + if (SmBusAddress == 0) return AGESA_ERROR; + + SetupFch (SMBUS_BASE_ADDR); + + Status = WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + + switch (SpdData->SocketId) { + case 0: + /* Switch onto the First CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + break; + case 1: + /* Switch onto the Second CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x40, 0x03); + break; + default: + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + break; + } + Status = ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 256); + + /*Output SPD Debug Message*/ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + printk(BIOS_DEBUG, " Status = %d\n",Status); + printk(BIOS_DEBUG, "SocketId MemChannelId SpdData->DimmId SmBusAddress Buffer\n"); + printk(BIOS_DEBUG, "%x, %x, %x, %x, %x\n", SpdData->SocketId, SpdData->MemChannelId, SpdData->DimmId, SmBusAddress, SpdData->Buffer); + + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + return Status; +} diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl new file mode 100644 index 0000000..0cbffb7 --- /dev/null +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -0,0 +1,1157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "DINAR ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSV, Ones) /* Assume nothing */ + Name(GPIC, 0x1) /* Assume PIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) + Field(PIRQ, ByteAcc, NoLock, Preserve) { + PIDX, 0x00000008, + PDAT, 0x00000008, /* Offset: 1h */ + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + Offset(0x10), + PIRS, 0x00000008, + Offset(0x13), + HDAD, 0x00000008, + , 0x00000008, + GEC, 0x00000008, + Offset(0x30), + USB1, 0x00000008, + USB2, 0x00000008, + USB3, 0x00000008, + USB4, 0x00000008, + USB5, 0x00000008, + USB6, 0x00000008, + USB7, 0x00000008, + Offset(0x40), + IDE, 0x00000008, + SATA, 0x00000008, + Offset(0x50), + GPP0, 0x00000008, + GPP1, 0x00000008, + GPP2, 0x00000008, + GPP3, 0x00000008 + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ + OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) + Field(PMRG, ByteAcc, NoLock, Preserve) { + PMRI, 0x00000008, + PMRD, 0x00000008, + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { + Offset(0x24), + MMSO,32, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x50), + HPAD,32, + Offset(0x60), + P1EB,16, + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xC8), + ,2, + SPRE,1, + TPDE,1, + Offset(0xF0), + ,3, + RSTU,1 + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, NoLock, Preserve) { + ,14, + PEWS,1, + WSTA,1, + ,14, + PEWD,1 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + /* Debug Port registers, 80h. */ + OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) + Field(DBBG, ByteAcc, NoLock, Preserve) { + DBG8, 0x00000008, + } + + Method(_PIC, 1) { + Store(Arg0, GPIC) + If (GPIC) { + Store(0xAA, \_SB.DBG8) + \_SB.DSPI() + } else { + Store(0xAC, \_SB.DBG8) + } + } + + Method(DSPI, 0) { + \_SB.GRUA(0x1F) + \_SB.GRUB(0x1F) + \_SB.GRUC(0x1F) + \_SB.GRUD(0x1F) + Store(0x1F, PIRE) + Store(0x1F, PIRF) + Store(0x1F, PIRG) + Store(0x1F, PIRH) + } + + Method(GRUA, 1) { + Store(Arg0, PIRA) + Store(Arg0, HDAD) + Store(Arg0, GEC) + Store(Arg0, GPP0) + Store(Arg0, GPP0) + } + + Method(GRUB, 1) { + Store(Arg0, PIRB) + Store(Arg0, USB2) + Store(Arg0, USB4) + Store(Arg0, USB6) + Store(Arg0, GPP1) + Store(Arg0, IDE) + } + + Method(GRUC, 1) { + Store(Arg0, PIRC) + Store(Arg0, USB1) + Store(Arg0, USB3) + Store(Arg0, USB5) + Store(Arg0, USB7) + Store(Arg0, GPP2) + } + + Method(GRUD, 1) { + Store(Arg0, PIRD) + Store(Arg0, SATA) + Store(Arg0, GPP3) + } + + Name(IRQB, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 15 + }}) + + Name(IRQP, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 3, 4, 5, 7, 10, 11, 12, 14, 15 + }}) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUA(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUA(Local0) + } + } + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUB(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUB(Local0) + } + } + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUC(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUC(Local0) + } + } + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUD(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUD(Local0) + } + } + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRE) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRE) + } + } + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRF) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRF) + } + } + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRG) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRG) + } + } + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRH) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRH) + } + } + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PEWS, PEWS) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + } /* End Scope GPE */ + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + External (TOM3) + External (TOM4) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + Method(_PRT,0) { + If(GPIC){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Method(_STA,0) { + Return(0x0F) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Method(_PRT,0) { + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* The external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Method(_PRT,0) { + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Method(_PRT,0) { + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Method(_PRT,0) { + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Method(_PRT,0) { + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Method(_PRT,0) { + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Method(_PRT,0) { + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Method(_PRT,0) { + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Method(_PRT,0) { + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Method(_PRT,0) { + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* Describe the Southbridge devices */ + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + } + } /* end AZHD */ + + Device(GEC) { + Name(_ADR, 0x00140006) + } /* end GEC */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + #include "acpi/usb.asl" + } /* end UOH1 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + #include "acpi/usb.asl" + } /* end UOH3 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + #include "acpi/usb.asl" + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + #include "acpi/usb.asl" + } /* end UEH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + #include "acpi/usb.asl" + } /* end UOH2 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + #include "acpi/usb.asl" + } /* end UOH4 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + #include "acpi/usb.asl" + } /* end UOH5 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + #include "acpi/usb.asl" + } /* end XHC0 */ + + Device(XHC1) { + Name(_ADR, 0x00100001) + #include "acpi/usb.asl" + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {8} + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {0} + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IRQNoFlags () {12} + }) + Method (_STA, 0) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + } /* end LIBR */ + + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method(_STA, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(0x0F) + } + Return(0x0) + } + Method(_CRS, 0) { + CreateDWordField(CRS, 0x0A, HPEB) + Store(HPAD, Local0) + And(Local0, 0xFFFFFFC0, HPEB) + Return(CRS) + } + } /* End Device(_SB.PCI0.HPET) */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + Store(\_SB.PCI0.TOM1, MM1B) + Subtract(PCBA, MM1B, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ +} +/* End of ASL file */ diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c new file mode 100644 index 0000000..baf0328 --- /dev/null +++ b/src/mainboard/amd/dinar/fadt.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "Platform.h" /*sb700 platform header*/ + +#ifndef ACPI_BLK_BASE +#define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c new file mode 100644 index 0000000..f66e92c --- /dev/null +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb700[2]; +u8 bus_rd890[14]; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* + * HT Chain device num, actually it is unit id base of every ht device in chain, + * assume every chain only have 4 ht device at most + */ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_sb700; +u32 sbdn_rd890; + +static u32 get_bus_conf_done = 0; + + + + +void get_bus_conf(void) +{ + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); + + sbdn_sb700 = 0; + + for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { + bus_sb700[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) { + bus_rd890[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + + bus_rd890[0] = (pci1234x[0] >> 16) & 0xff; + bus_sb700[0] = bus_rd890[0]; + + /* sb700 */ + dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + + + + if (dev) { + bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb700[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rd890 */ + for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) { + dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0)); + if (dev) { + bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rd890[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rd890[i]] = 1; /* PCI bus. */ + } + } + } + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX +// sb_After_Pci_Init(); +// sb_Late_Post(); +#endif + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); +} diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c new file mode 100644 index 0000000..f18c09d --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.c @@ -0,0 +1,482 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Filecode.h" +#include "Hudson-2.h" +#include "AmdSbLib.h" +#include "gpio.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG07 +#define SB_GPIO_REG07 7 +#endif + +#ifndef SB_GPIO_REG25 +#define SB_GPIO_REG25 25 +#endif + +#ifndef SB_GPIO_REG26 +#define SB_GPIO_REG26 26 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +void gpioEarlyInit (void); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +void +gpioEarlyInit( + void + ) +{ + u8 Flags; + u8 Data8 = 0; + u8 StripInfo = 0; + u8 BoardType = 1; + u8 RegIndex8 = 0; + u8 boardRevC = 0x2; + u16 Data16 = 0; + u32 Index = 0; + u32 AcpiMmioAddr = 0; + u32 GpioMmioAddr = 0; + u32 IoMuxMmioAddr = 0; + u32 MiscMmioAddr = 0; + u32 SmiMmioAddr = 0; + u32 andMask32 = 0; + + // Enable HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + Data8 |= BIT0; + WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + // Get HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); + Data16 = Data8 << 8; + ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); + Data16 |= Data8; + AcpiMmioAddr = (u32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE; + MiscMmioAddr = AcpiMmioAddr + MISC_BASE; + Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); + if ((Data8 & BIT4) == 0) { + BoardType = 0; // external clock board + } + Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); + StripInfo = (Data8 & BIT7) >> 7; + Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); + StripInfo |= (Data8 & BIT7) >> 6; + if (StripInfo < boardRevC) { // for old board. Rev B + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + } + for (Index = 0; Index < MAX_GPIO_NO; Index++) { + if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { + if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { + // Configure multi-funtion + Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); + } + // Configure GPIO + if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { + Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); + Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); + } + if (Index == GPIO_65) { + if ( BoardType == 0 ) { + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + } + } + } + // Configure GEVENT + if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { + SmiMmioAddr = AcpiMmioAddr + SMI_BASE; + + andMask32 = ~(1 << (Index - GEVENT_00)); + + //EventEnable: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); + + //SciTrig: 0-Falling Edge, 1-Rising Edge + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); + + //SciLevl: 0-Edge trigger, 1-Level Trigger + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); + + //SmiSciEn: 0-Not send SMI, 1-Send SMI + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); + + //SciS0En: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); + + //SciMap: 00000b ~ 11111b + RegIndex8=(u8)((Index - GEVENT_00) >> 2); + Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); + + //SmiTrig: 0-Active Low, 1-Active High + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); + + //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + RegIndex8=(u8)((Index - GEVENT_00) >> 4); + Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); + } + } + + // + // config MXM + // GPIO9: Input for MXM_PRESENT2# + // GPIO10: Input for MXM_PRESENT1# + // GPIO28: Input for MXM_PWRGD + // GPIO35: Output for MXM Reset + // GPIO45: Output for MXM Power Enable, active HIGH + // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + // + // set INTE#/GPIO32 as GPO for PCIE_SW + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); + + // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + + // set AD9/GPIO9 as GPI for MXM_PRESENT2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + + // set AD10/GPIO10 as GPI for MXM_PRESENT1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + + // set GNT1#/GPIO44 as GPO for MXM Reset + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + + // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + + // set AD28/GPIO28 as GPI for MXM_PWRGD + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + + // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); + + // + // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). + // + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + + // check if there any GFX card + Flags = 0; + // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); + // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); + ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); + ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + Flags = 1; + } + } + if ( Flags ) + { + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + // WAIT POWER READY: GPIO28 (MXM_PWRGD) + //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + while (!(Data8 && BIT7)) + { + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + } + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset + // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + } + else + { + // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); + } + + // + // APU GPP0: On board LAN + // GPIO25: PCIE_RST#_LAN, LOW active + // GPIO63: LAN_CLKREQ# + // GPIO197: LOM_POWER, HIGH Active + // Clock: GPP_CLK3 + // + // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + + // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 + + // + // APU GPP1: WUSB + // GPIO1: MPCIE_RST2#, LOW active + // GPIO13: WU_DISABLE#, LOW active + // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + // + // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD01/GPIO01 as GPO for MPCIE_RST2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // + // APU GPP2: WWAN + // GPIO0: MPCIE_RST1#, LOW active + // GPIO14: WP_DISABLE#, LOW active + // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + // + // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD00/GPIO00 as GPO for MPCIE_RST1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); + + // + // APU GPP3: 1394 + // GPIO59: Power control, HIGH active + // GPIO27: PCIE_RST#_1394, LOW active + // GPIO41: CLKREQ# + // Clock: GPP_CLK8 + // + // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# + + // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + // To fix glitch issue + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + // + // Enable/Disable OnBoard LAN + // + if (!CONFIG_ONBOARD_LAN) + { // 1 - DISABLED + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); + // } + + + // + // Enable/Disable 1394 + // + if (!CONFIG_ONBOARD_1394) + { // 1 - DISABLED + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); + // + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); + // } + + // + // external USB 3.0 control: + // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO26: PCIE_RST#_USB3.0 + // GPIO46: PCIE_USB30_CLKREQ# + // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + // Clock: GPP_CLK7 + // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { + // disable Onboard NEC USB3.0 controller + if (!CONFIG_ONBOARD_USB30) { + RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + } + // } + + // + // BlueTooth control: BT_ON + // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO07: BT_ON, 0 - OFF, 1 - ON + // + if (!CONFIG_ONBOARD_BLUETOOTH) { + //- if (SystemConfiguration.amdBlueTooth == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); + //- } + } + + // + // WebCam control: + // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + // + if (!CONFIG_ONBOARD_WEBCAM) { + //- if (SystemConfiguration.amdWebCam == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Travis enable: + // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + // + if (!CONFIG_ONBOARD_TRAVIS) { + //- if (SystemConfiguration.amdTravisCtrl == 0) { + RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Disable Light Sensor if needed + // + if (CONFIG_ONBOARD_LIGHTSENSOR) { + //- if (SystemConfiguration.amdLightSensor == 1) { + RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); + //- } + } + +} + + diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h new file mode 100644 index 0000000..c936e50 --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.h @@ -0,0 +1,2329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include +#include + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define Mmio_Address( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) + +#define Mmio32_Ptr( BaseAddr, Register ) \ + ( (volatile u32 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio32_G( BaseAddr, Register ) \ + *Mmio32_Ptr( BaseAddr, Register ) + +#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio32_G( BaseAddr, Register ) = \ +(u32) ( \ + ( Mmio32_G( BaseAddr, Register ) & \ + (u32)(AndData) \ + ) | \ + (u32)(OrData) \ + ) + +#define Mmio8_Ptr( BaseAddr, Register ) \ + ( (volatile u8 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio8_G( BaseAddr, Register ) \ + *Mmio8_Ptr( BaseAddr, Register ) + +#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio8_G( BaseAddr, Register ) = \ +(u8) ( \ + ( Mmio8_G( BaseAddr, Register ) & \ + (u8)(AndData) \ + ) | \ + (u8)(OrData) \ + ) + +#define SMIREG_EVENT_ENABLE 0x04 +#define SMIREG_SCITRIG 0x08 +#define SMIREG_SCILEVEL 0x0C +#define SMIREG_SMISCIEN 0x14 +#define SMIREG_SCIS0EN 0x20 +#define SMIREG_SCIMAP0 0x40 +#define SMIREG_SCIMAP1 0x44 +#define SMIREG_SCIMAP2 0x48 +#define SMIREG_SCIMAP3 0x4C +#define SMIREG_SCIMAP4 0x50 +#define SMIREG_SCIMAP5 0x54 +#define SMIREG_SCIMAP6 0x58 +#define SMIREG_SCIMAP7 0x5C +#define SMIREG_SCIMAP8 0x60 +#define SMIREG_SCIMAP9 0x64 +#define SMIREG_SCIMAP10 0x68 +#define SMIREG_SCIMAP11 0x6C +#define SMIREG_SCIMAP12 0x70 +#define SMIREG_SCIMAP13 0x74 +#define SMIREG_SCIMAP14 0x78 +#define SMIREG_SCIMAP15 0x7C +#define SMIREG_SMITRIG 0x98 +#define SMIREG_SMICONTROL0 0xA0 +#define SMIREG_SMICONTROL1 0xA4 + +#define FUNCTION0 0 +#define FUNCTION1 1 +#define FUNCTION2 2 +#define FUNCTION3 3 +#define NonGpio 0x80 // BIT7 + +// S0-domain General Purpose I/O: GPIO 00~67 +#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT +#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT +#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT +#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED +#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT +#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT +#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED +#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF +#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level +#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 +#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 +#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 +#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default +#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. +#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE +// 1:BATTERY IS FINE(DEFAULT) +// 0:BATTERY IS LOW +#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF +#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default +#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high +#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high +#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high +#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT +#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT +#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 +#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 +// 00 - REVA +// 01 - REVB +// 10 - REVC +// 11 - REVD +#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO +#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. +// 0:USB3.0 I/F in Express CARD +// 1:PCIE I/F in Express CARD detection +#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC +#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. +#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# +#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# +#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF +#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# +#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA +#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ +#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 +#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V +#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 +#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT +#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE +#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE +#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) +// 1:ENABLE; 0:DISABLE +// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 +#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN +#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER +#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER +#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE +#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# +#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 +#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 +#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# +#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 +#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM +#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default +#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +#define GPIO_68_SELECT FUNCTION0+NonGpio +#define GPIO_69_SELECT FUNCTION0+NonGpio +#define GPIO_70_SELECT FUNCTION0+NonGpio +#define GPIO_71_SELECT FUNCTION0+NonGpio +#define GPIO_72_SELECT FUNCTION0+NonGpio +#define GPIO_73_SELECT FUNCTION0+NonGpio +#define GPIO_74_SELECT FUNCTION0+NonGpio +#define GPIO_75_SELECT FUNCTION0+NonGpio +#define GPIO_76_SELECT FUNCTION0+NonGpio +#define GPIO_77_SELECT FUNCTION0+NonGpio +#define GPIO_78_SELECT FUNCTION0+NonGpio +#define GPIO_79_SELECT FUNCTION0+NonGpio +#define GPIO_80_SELECT FUNCTION0+NonGpio +#define GPIO_81_SELECT FUNCTION0+NonGpio +#define GPIO_82_SELECT FUNCTION0+NonGpio +#define GPIO_83_SELECT FUNCTION0+NonGpio +#define GPIO_84_SELECT FUNCTION0+NonGpio +#define GPIO_85_SELECT FUNCTION0+NonGpio +#define GPIO_86_SELECT FUNCTION0+NonGpio +#define GPIO_87_SELECT FUNCTION0+NonGpio +#define GPIO_88_SELECT FUNCTION0+NonGpio +#define GPIO_89_SELECT FUNCTION0+NonGpio +#define GPIO_90_SELECT FUNCTION0+NonGpio +#define GPIO_91_SELECT FUNCTION0+NonGpio +#define GPIO_92_SELECT FUNCTION0+NonGpio +#define GPIO_93_SELECT FUNCTION0+NonGpio +#define GPIO_94_SELECT FUNCTION0+NonGpio +#define GPIO_95_SELECT FUNCTION0+NonGpio +// GEVENT 00~23 are mapped to GPIO 96~119 +#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# +#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# +#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP +#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# +#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# +#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active +#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, +// there is a confliction to IR function when this pin is as a GEVENT. +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, +// special pin difination for SB700 VGA OUTPUT, high active, +// VGA power for Hudson-M2 will be down when it was asserted. +#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active +#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) +#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 +#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 +#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active +// [option for SPI_TPM_CS# in Hudson-M2 A12)] +#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & +// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time +#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, +// plus judge GPIO40 and GPIO19 level,low is assert. +// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) +// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) +#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active +#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, +// low active, when it's low, BIOS will enbale ODD_PWR +#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# +#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK +#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# +#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT +#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +#define GPIO_120_SELECT FUNCTION0+NonGpio +#define GPIO_121_SELECT FUNCTION0+NonGpio +#define GPIO_122_SELECT FUNCTION0+NonGpio +#define GPIO_123_SELECT FUNCTION0+NonGpio +#define GPIO_124_SELECT FUNCTION0+NonGpio +#define GPIO_125_SELECT FUNCTION0+NonGpio +#define GPIO_126_SELECT FUNCTION0+NonGpio +#define GPIO_127_SELECT FUNCTION0+NonGpio +#define GPIO_128_SELECT FUNCTION0+NonGpio +#define GPIO_129_SELECT FUNCTION0+NonGpio +#define GPIO_130_SELECT FUNCTION0+NonGpio +#define GPIO_131_SELECT FUNCTION0+NonGpio +#define GPIO_132_SELECT FUNCTION0+NonGpio +#define GPIO_133_SELECT FUNCTION0+NonGpio +#define GPIO_134_SELECT FUNCTION0+NonGpio +#define GPIO_135_SELECT FUNCTION0+NonGpio +#define GPIO_136_SELECT FUNCTION0+NonGpio +#define GPIO_137_SELECT FUNCTION0+NonGpio +#define GPIO_138_SELECT FUNCTION0+NonGpio +#define GPIO_139_SELECT FUNCTION0+NonGpio +#define GPIO_140_SELECT FUNCTION0+NonGpio +#define GPIO_141_SELECT FUNCTION0+NonGpio +#define GPIO_142_SELECT FUNCTION0+NonGpio +#define GPIO_143_SELECT FUNCTION0+NonGpio +#define GPIO_144_SELECT FUNCTION0+NonGpio +#define GPIO_145_SELECT FUNCTION0+NonGpio +#define GPIO_146_SELECT FUNCTION0+NonGpio +#define GPIO_147_SELECT FUNCTION0+NonGpio +#define GPIO_148_SELECT FUNCTION0+NonGpio +#define GPIO_149_SELECT FUNCTION0+NonGpio +#define GPIO_150_SELECT FUNCTION0+NonGpio +#define GPIO_151_SELECT FUNCTION0+NonGpio +#define GPIO_152_SELECT FUNCTION0+NonGpio +#define GPIO_153_SELECT FUNCTION0+NonGpio +#define GPIO_154_SELECT FUNCTION0+NonGpio +#define GPIO_155_SELECT FUNCTION0+NonGpio +#define GPIO_156_SELECT FUNCTION0+NonGpio +#define GPIO_157_SELECT FUNCTION0+NonGpio +#define GPIO_158_SELECT FUNCTION0+NonGpio +#define GPIO_159_SELECT FUNCTION0+NonGpio +#define GPIO_160_SELECT FUNCTION0+NonGpio + +// S5-domain General Purpose I/O +#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# +#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 +#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 +#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 +#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 +#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. +#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, +#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE +#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 +#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# +#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 +#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 +#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO +#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR +#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 +#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 +#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# +#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE +#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE +// option for HDMI CEC signal OW ACTIVE +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA +#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK +#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active +// RESERVED FOR LCD BACKLIGHT PWM +#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL +#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM +#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF +#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD + +#define TYPE_GPI (1<<5) +#define TYPE_GPO (0<<5) + +#define GPIO_00_TYPE TYPE_GPO +#define GPIO_01_TYPE TYPE_GPO +#define GPIO_02_TYPE TYPE_GPO +#define GPIO_03_TYPE TYPE_GPO +#define GPIO_04_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO +#define GPIO_06_TYPE TYPE_GPO +#define GPIO_07_TYPE TYPE_GPO +#define GPIO_08_TYPE TYPE_GPO +#define GPIO_09_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI +#define GPIO_11_TYPE TYPE_GPO +#define GPIO_12_TYPE TYPE_GPO +#define GPIO_13_TYPE TYPE_GPO +#define GPIO_14_TYPE TYPE_GPO +#define GPIO_15_TYPE TYPE_GPO +#define GPIO_16_TYPE TYPE_GPO +#define GPIO_17_TYPE TYPE_GPO +#define GPIO_18_TYPE TYPE_GPO +#define GPIO_19_TYPE TYPE_GPO +#define GPIO_20_TYPE TYPE_GPO +#define GPIO_21_TYPE TYPE_GPO +#define GPIO_22_TYPE TYPE_GPO +#define GPIO_23_TYPE TYPE_GPO +#define GPIO_24_TYPE TYPE_GPO +#define GPIO_25_TYPE TYPE_GPO +#define GPIO_26_TYPE TYPE_GPO +#define GPIO_27_TYPE TYPE_GPO +#define GPIO_28_TYPE TYPE_GPI +#define GPIO_29_TYPE TYPE_GPO +#define GPIO_30_TYPE TYPE_GPI +#define GPIO_31_TYPE TYPE_GPI +#define GPIO_32_TYPE TYPE_GPO +#define GPIO_33_TYPE TYPE_GPI +#define GPIO_34_TYPE TYPE_GPO +#define GPIO_35_TYPE TYPE_GPO +#define GPIO_36_TYPE TYPE_GPO +#define GPIO_37_TYPE TYPE_GPO +#define GPIO_38_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO +#define GPIO_40_TYPE TYPE_GPO +#define GPIO_41_TYPE TYPE_GPI +#define GPIO_42_TYPE TYPE_GPI +#define GPIO_43_TYPE TYPE_GPO +#define GPIO_44_TYPE TYPE_GPO +#define GPIO_45_TYPE TYPE_GPO +#define GPIO_46_TYPE TYPE_GPI +#define GPIO_47_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO +#define GPIO_50_TYPE TYPE_GPO +#define GPIO_51_TYPE TYPE_GPO +#define GPIO_52_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO +#define GPIO_56_TYPE TYPE_GPI +#define GPIO_57_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO +#define GPIO_59_TYPE TYPE_GPO +#define GPIO_60_TYPE TYPE_GPI +#define GPIO_61_TYPE TYPE_GPI +#define GPIO_62_TYPE TYPE_GPI +#define GPIO_63_TYPE TYPE_GPI +#define GPIO_64_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI +#define GPIO_66_TYPE TYPE_GPO +#define GPIO_67_TYPE TYPE_GPO +#define GPIO_68_TYPE TYPE_GPO +#define GPIO_69_TYPE TYPE_GPO +#define GPIO_70_TYPE TYPE_GPO +#define GPIO_71_TYPE TYPE_GPO +#define GPIO_72_TYPE TYPE_GPO +#define GPIO_73_TYPE TYPE_GPO +#define GPIO_74_TYPE TYPE_GPO +#define GPIO_75_TYPE TYPE_GPO +#define GPIO_76_TYPE TYPE_GPO +#define GPIO_77_TYPE TYPE_GPO +#define GPIO_78_TYPE TYPE_GPO +#define GPIO_79_TYPE TYPE_GPO +#define GPIO_80_TYPE TYPE_GPO +#define GPIO_81_TYPE TYPE_GPO +#define GPIO_82_TYPE TYPE_GPO +#define GPIO_83_TYPE TYPE_GPO +#define GPIO_84_TYPE TYPE_GPO +#define GPIO_85_TYPE TYPE_GPO +#define GPIO_86_TYPE TYPE_GPO +#define GPIO_87_TYPE TYPE_GPO +#define GPIO_88_TYPE TYPE_GPO +#define GPIO_89_TYPE TYPE_GPO +#define GPIO_90_TYPE TYPE_GPO +#define GPIO_91_TYPE TYPE_GPO +#define GPIO_92_TYPE TYPE_GPO +#define GPIO_93_TYPE TYPE_GPO +#define GPIO_94_TYPE TYPE_GPO +#define GPIO_95_TYPE TYPE_GPO + +// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +#define GPIO_96_TYPE TYPE_GPI +#define GPIO_97_TYPE TYPE_GPI +#define GPIO_98_TYPE TYPE_GPI +#define GPIO_99_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI +#define GPIO_101_TYPE TYPE_GPI +#define GPIO_102_TYPE TYPE_GPO +#define GPIO_103_TYPE TYPE_GPO +#define GPIO_104_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI +#define GPIO_106_TYPE TYPE_GPO +#define GPIO_107_TYPE TYPE_GPI +#define GPIO_108_TYPE TYPE_GPI +#define GPIO_109_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI +#define GPIO_111_TYPE TYPE_GPI +#define GPIO_112_TYPE TYPE_GPI +#define GPIO_113_TYPE TYPE_GPI +#define GPIO_114_TYPE TYPE_GPO +#define GPIO_115_TYPE TYPE_GPI +#define GPIO_116_TYPE TYPE_GPI +#define GPIO_117_TYPE TYPE_GPI +#define GPIO_118_TYPE TYPE_GPI +#define GPIO_119_TYPE TYPE_GPI + +#define GPIO_120_TYPE TYPE_GPO +#define GPIO_121_TYPE TYPE_GPO +#define GPIO_122_TYPE TYPE_GPO +#define GPIO_123_TYPE TYPE_GPO +#define GPIO_124_TYPE TYPE_GPO +#define GPIO_125_TYPE TYPE_GPO +#define GPIO_126_TYPE TYPE_GPO +#define GPIO_127_TYPE TYPE_GPO +#define GPIO_128_TYPE TYPE_GPO +#define GPIO_129_TYPE TYPE_GPO +#define GPIO_130_TYPE TYPE_GPO +#define GPIO_131_TYPE TYPE_GPO +#define GPIO_132_TYPE TYPE_GPO +#define GPIO_133_TYPE TYPE_GPO +#define GPIO_134_TYPE TYPE_GPO +#define GPIO_135_TYPE TYPE_GPO +#define GPIO_136_TYPE TYPE_GPO +#define GPIO_137_TYPE TYPE_GPO +#define GPIO_138_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO +#define GPIO_140_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO +#define GPIO_142_TYPE TYPE_GPO +#define GPIO_143_TYPE TYPE_GPO +#define GPIO_144_TYPE TYPE_GPO +#define GPIO_145_TYPE TYPE_GPO +#define GPIO_146_TYPE TYPE_GPO +#define GPIO_147_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO +#define GPIO_150_TYPE TYPE_GPO +#define GPIO_151_TYPE TYPE_GPO +#define GPIO_152_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO +#define GPIO_156_TYPE TYPE_GPO +#define GPIO_157_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO +#define GPIO_159_TYPE TYPE_GPO +#define GPIO_160_TYPE TYPE_GPO +#define GPIO_161_TYPE TYPE_GPO +#define GPIO_162_TYPE TYPE_GPO +#define GPIO_163_TYPE TYPE_GPO +#define GPIO_164_TYPE TYPE_GPI +#define GPIO_165_TYPE TYPE_GPO +#define GPIO_166_TYPE TYPE_GPI +#define GPIO_167_TYPE TYPE_GPI +#define GPIO_168_TYPE TYPE_GPI +#define GPIO_169_TYPE TYPE_GPI +#define GPIO_170_TYPE TYPE_GPO +#define GPIO_171_TYPE TYPE_GPI +#define GPIO_172_TYPE TYPE_GPO +#define GPIO_173_TYPE TYPE_GPI +#define GPIO_174_TYPE TYPE_GPI +#define GPIO_175_TYPE TYPE_GPO +#define GPIO_176_TYPE TYPE_GPO +#define GPIO_177_TYPE TYPE_GPO +#define GPIO_178_TYPE TYPE_GPO +#define GPIO_179_TYPE TYPE_GPO +#define GPIO_180_TYPE TYPE_GPO +#define GPIO_181_TYPE TYPE_GPO +#define GPIO_182_TYPE TYPE_GPO +#define GPIO_183_TYPE TYPE_GPO +#define GPIO_184_TYPE TYPE_GPI +#define GPIO_185_TYPE TYPE_GPO +#define GPIO_186_TYPE TYPE_GPO +#define GPIO_187_TYPE TYPE_GPO +#define GPIO_188_TYPE TYPE_GPO +#define GPIO_189_TYPE TYPE_GPI +#define GPIO_190_TYPE TYPE_GPI +#define GPIO_191_TYPE TYPE_GPO +#define GPIO_192_TYPE TYPE_GPO +#define GPIO_193_TYPE TYPE_GPO +#define GPIO_194_TYPE TYPE_GPO +#define GPIO_195_TYPE TYPE_GPO +#define GPIO_196_TYPE TYPE_GPO +#define GPIO_197_TYPE TYPE_GPO +#define GPIO_198_TYPE TYPE_GPO +#define GPIO_199_TYPE TYPE_GPI +#define GPIO_200_TYPE TYPE_GPO +#define GPIO_201_TYPE TYPE_GPI +#define GPIO_202_TYPE TYPE_GPI +#define GPIO_203_TYPE TYPE_GPI +#define GPIO_204_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI +#define GPIO_206_TYPE TYPE_GPI +#define GPIO_207_TYPE TYPE_GPI +#define GPIO_208_TYPE TYPE_GPI +#define GPIO_209_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO +#define GPIO_211_TYPE TYPE_GPO +#define GPIO_212_TYPE TYPE_GPO +#define GPIO_213_TYPE TYPE_GPO +#define GPIO_214_TYPE TYPE_GPO +#define GPIO_215_TYPE TYPE_GPO +#define GPIO_216_TYPE TYPE_GPO +#define GPIO_217_TYPE TYPE_GPO +#define GPIO_218_TYPE TYPE_GPO +#define GPIO_219_TYPE TYPE_GPO +#define GPIO_220_TYPE TYPE_GPO +#define GPIO_221_TYPE TYPE_GPO +#define GPIO_222_TYPE TYPE_GPO +#define GPIO_223_TYPE TYPE_GPO +#define GPIO_224_TYPE TYPE_GPO +#define GPIO_225_TYPE TYPE_GPO +#define GPIO_226_TYPE TYPE_GPO +#define GPIO_227_TYPE TYPE_GPO +#define GPIO_228_TYPE TYPE_GPO +#define GPIO_229_TYPE TYPE_GPO + +#define GPO_LOW (0<<6) +#define GPO_HI (1<<6) + +#define GPO_00_LEVEL GPO_HI +#define GPO_01_LEVEL GPO_HI +#define GPO_02_LEVEL GPO_HI +#define GPO_03_LEVEL GPO_HI +#define GPO_04_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI +#define GPO_06_LEVEL GPO_HI +#define GPO_07_LEVEL GPO_HI +#define GPO_08_LEVEL GPO_HI +#define GPO_09_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW +#define GPO_11_LEVEL GPO_HI +#define GPO_12_LEVEL GPO_HI +#define GPO_13_LEVEL GPO_HI +#define GPO_14_LEVEL GPO_HI +#define GPO_15_LEVEL GPO_HI +#define GPO_16_LEVEL GPO_HI +#define GPO_17_LEVEL GPO_HI +#define GPO_18_LEVEL GPO_HI +#define GPO_19_LEVEL GPO_LOW +#define GPO_20_LEVEL GPO_LOW +#define GPO_21_LEVEL GPO_LOW +#define GPO_22_LEVEL GPO_HI +#define GPO_23_LEVEL GPO_HI +#define GPO_24_LEVEL GPO_HI +#define GPO_25_LEVEL GPO_HI +#define GPO_26_LEVEL GPO_HI +#define GPO_27_LEVEL GPO_HI +#define GPO_28_LEVEL GPO_LOW +#define GPO_29_LEVEL GPO_HI +#define GPO_30_LEVEL GPO_LOW +#define GPO_31_LEVEL GPO_LOW +#define GPO_32_LEVEL GPO_HI +#define GPO_33_LEVEL GPO_LOW +#define GPO_34_LEVEL GPO_LOW +#define GPO_35_LEVEL GPO_LOW +#define GPO_36_LEVEL GPO_LOW +#define GPO_37_LEVEL GPO_HI +#define GPO_38_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI +#define GPO_40_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW +#define GPO_42_LEVEL GPO_LOW +#define GPO_43_LEVEL GPO_LOW +#define GPO_44_LEVEL GPO_HI +#define GPO_45_LEVEL GPO_HI +#define GPO_46_LEVEL GPO_LOW +#define GPO_47_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW +#define GPO_49_LEVEL GPO_HI +#define GPO_50_LEVEL GPO_HI +#define GPO_51_LEVEL GPO_LOW +#define GPO_52_LEVEL GPO_HI +#define GPO_53_LEVEL GPO_HI +#define GPO_54_LEVEL GPO_LOW +#define GPO_55_LEVEL GPO_LOW +#define GPO_56_LEVEL GPO_LOW +#define GPO_57_LEVEL GPO_HI +#define GPO_58_LEVEL GPO_HI +#define GPO_59_LEVEL GPO_HI +#define GPO_60_LEVEL GPO_LOW +#define GPO_61_LEVEL GPO_LOW +#define GPO_62_LEVEL GPO_LOW +#define GPO_63_LEVEL GPO_LOW +#define GPO_64_LEVEL GPO_LOW +#define GPO_65_LEVEL GPO_LOW +#define GPO_66_LEVEL GPO_LOW +#define GPO_67_LEVEL GPO_LOW +#define GPO_68_LEVEL GPO_LOW +#define GPO_69_LEVEL GPO_LOW +#define GPO_70_LEVEL GPO_LOW +#define GPO_71_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW +#define GPO_73_LEVEL GPO_LOW +#define GPO_74_LEVEL GPO_LOW +#define GPO_75_LEVEL GPO_LOW +#define GPO_76_LEVEL GPO_LOW +#define GPO_77_LEVEL GPO_LOW +#define GPO_78_LEVEL GPO_LOW +#define GPO_79_LEVEL GPO_LOW +#define GPO_80_LEVEL GPO_LOW +#define GPO_81_LEVEL GPO_LOW +#define GPO_82_LEVEL GPO_LOW +#define GPO_83_LEVEL GPO_LOW +#define GPO_84_LEVEL GPO_LOW +#define GPO_85_LEVEL GPO_LOW +#define GPO_86_LEVEL GPO_LOW +#define GPO_87_LEVEL GPO_LOW +#define GPO_88_LEVEL GPO_LOW +#define GPO_89_LEVEL GPO_LOW +#define GPO_90_LEVEL GPO_LOW +#define GPO_91_LEVEL GPO_LOW +#define GPO_92_LEVEL GPO_LOW +#define GPO_93_LEVEL GPO_LOW +#define GPO_94_LEVEL GPO_LOW +#define GPO_95_LEVEL GPO_LOW +#define GPO_96_LEVEL GPO_LOW +#define GPO_97_LEVEL GPO_LOW +#define GPO_98_LEVEL GPO_LOW +#define GPO_99_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW +#define GPO_101_LEVEL GPO_LOW +#define GPO_102_LEVEL GPO_LOW +#define GPO_103_LEVEL GPO_LOW +#define GPO_104_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW +#define GPO_106_LEVEL GPO_LOW +#define GPO_107_LEVEL GPO_LOW +#define GPO_108_LEVEL GPO_HI +#define GPO_109_LEVEL GPO_LOW +#define GPO_110_LEVEL GPO_HI +#define GPO_111_LEVEL GPO_HI +#define GPO_112_LEVEL GPO_HI +#define GPO_113_LEVEL GPO_LOW +#define GPO_114_LEVEL GPO_LOW +#define GPO_115_LEVEL GPO_LOW +#define GPO_116_LEVEL GPO_LOW +#define GPO_117_LEVEL GPO_LOW +#define GPO_118_LEVEL GPO_LOW +#define GPO_119_LEVEL GPO_LOW +#define GPO_120_LEVEL GPO_LOW +#define GPO_121_LEVEL GPO_LOW +#define GPO_122_LEVEL GPO_LOW +#define GPO_123_LEVEL GPO_LOW +#define GPO_124_LEVEL GPO_LOW +#define GPO_125_LEVEL GPO_LOW +#define GPO_126_LEVEL GPO_LOW +#define GPO_127_LEVEL GPO_LOW +#define GPO_128_LEVEL GPO_LOW +#define GPO_129_LEVEL GPO_LOW +#define GPO_130_LEVEL GPO_LOW +#define GPO_131_LEVEL GPO_LOW +#define GPO_132_LEVEL GPO_LOW +#define GPO_133_LEVEL GPO_LOW +#define GPO_134_LEVEL GPO_LOW +#define GPO_135_LEVEL GPO_LOW +#define GPO_136_LEVEL GPO_LOW +#define GPO_137_LEVEL GPO_LOW +#define GPO_138_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW +#define GPO_140_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW +#define GPO_142_LEVEL GPO_LOW +#define GPO_143_LEVEL GPO_LOW +#define GPO_144_LEVEL GPO_LOW +#define GPO_145_LEVEL GPO_LOW +#define GPO_146_LEVEL GPO_LOW +#define GPO_147_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW +#define GPO_149_LEVEL GPO_LOW +#define GPO_150_LEVEL GPO_LOW +#define GPO_151_LEVEL GPO_LOW +#define GPO_152_LEVEL GPO_LOW +#define GPO_153_LEVEL GPO_LOW +#define GPO_154_LEVEL GPO_LOW +#define GPO_155_LEVEL GPO_LOW +#define GPO_156_LEVEL GPO_LOW +#define GPO_157_LEVEL GPO_LOW +#define GPO_158_LEVEL GPO_LOW +#define GPO_159_LEVEL GPO_LOW +#define GPO_160_LEVEL GPO_LOW +#define GPO_161_LEVEL GPO_LOW +#define GPO_162_LEVEL GPO_LOW +#define GPO_163_LEVEL GPO_LOW +#define GPO_164_LEVEL GPO_LOW +#define GPO_165_LEVEL GPO_LOW +#define GPO_166_LEVEL GPO_LOW +#define GPO_167_LEVEL GPO_LOW +#define GPO_168_LEVEL GPO_LOW +#define GPO_169_LEVEL GPO_LOW +#define GPO_170_LEVEL GPO_HI +#define GPO_171_LEVEL GPO_LOW +#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_173_LEVEL GPO_LOW +#define GPO_174_LEVEL GPO_LOW +#define GPO_175_LEVEL GPO_LOW +#define GPO_176_LEVEL GPO_LOW +#define GPO_177_LEVEL GPO_LOW +#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_179_LEVEL GPO_HI +#define GPO_180_LEVEL GPO_HI +#define GPO_181_LEVEL GPO_LOW +#define GPO_182_LEVEL GPO_HI +#define GPO_183_LEVEL GPO_LOW +#define GPO_184_LEVEL GPO_LOW +#define GPO_185_LEVEL GPO_LOW +#define GPO_186_LEVEL GPO_LOW +#define GPO_187_LEVEL GPO_LOW +#define GPO_188_LEVEL GPO_LOW +#define GPO_189_LEVEL GPO_LOW +#define GPO_190_LEVEL GPO_LOW +#define GPO_191_LEVEL GPO_LOW +#define GPO_192_LEVEL GPO_LOW +#define GPO_193_LEVEL GPO_LOW +#define GPO_194_LEVEL GPO_LOW +#define GPO_195_LEVEL GPO_LOW +#define GPO_196_LEVEL GPO_LOW +#define GPO_197_LEVEL GPO_LOW +#define GPO_198_LEVEL GPO_LOW +#define GPO_199_LEVEL GPO_LOW +#define GPO_200_LEVEL GPO_HI +#define GPO_201_LEVEL GPO_LOW +#define GPO_202_LEVEL GPO_LOW +#define GPO_203_LEVEL GPO_LOW +#define GPO_204_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW +#define GPO_206_LEVEL GPO_LOW +#define GPO_207_LEVEL GPO_LOW +#define GPO_208_LEVEL GPO_LOW +#define GPO_209_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW +#define GPO_211_LEVEL GPO_LOW +#define GPO_212_LEVEL GPO_LOW +#define GPO_213_LEVEL GPO_LOW +#define GPO_214_LEVEL GPO_LOW +#define GPO_215_LEVEL GPO_LOW +#define GPO_216_LEVEL GPO_LOW +#define GPO_217_LEVEL GPO_LOW +#define GPO_218_LEVEL GPO_LOW +#define GPO_219_LEVEL GPO_LOW +#define GPO_220_LEVEL GPO_LOW +#define GPO_221_LEVEL GPO_LOW +#define GPO_222_LEVEL GPO_LOW +#define GPO_223_LEVEL GPO_LOW +#define GPO_224_LEVEL GPO_LOW +#define GPO_225_LEVEL GPO_LOW +#define GPO_226_LEVEL GPO_LOW +#define GPO_227_LEVEL GPO_LOW +#define GPO_228_LEVEL GPO_LOW +#define GPO_229_LEVEL GPO_LOW + +#define GPIO_NONSTICKY (0<<2) +#define GPIO_STICKY (1<<2) + +#define GPIO_00_STICKY GPIO_NONSTICKY +#define GPIO_01_STICKY GPIO_NONSTICKY +#define GPIO_02_STICKY GPIO_NONSTICKY +#define GPIO_03_STICKY GPIO_NONSTICKY +#define GPIO_04_STICKY GPIO_NONSTICKY +#define GPIO_05_STICKY GPIO_NONSTICKY +#define GPIO_06_STICKY GPIO_NONSTICKY +#define GPIO_07_STICKY GPIO_NONSTICKY +#define GPIO_08_STICKY GPIO_NONSTICKY +#define GPIO_09_STICKY GPIO_NONSTICKY +#define GPIO_10_STICKY GPIO_NONSTICKY +#define GPIO_11_STICKY GPIO_NONSTICKY +#define GPIO_12_STICKY GPIO_NONSTICKY +#define GPIO_13_STICKY GPIO_NONSTICKY +#define GPIO_14_STICKY GPIO_NONSTICKY +#define GPIO_15_STICKY GPIO_NONSTICKY +#define GPIO_16_STICKY GPIO_NONSTICKY +#define GPIO_17_STICKY GPIO_STICKY +#define GPIO_18_STICKY GPIO_NONSTICKY +#define GPIO_19_STICKY GPIO_NONSTICKY +#define GPIO_20_STICKY GPIO_NONSTICKY +#define GPIO_21_STICKY GPIO_NONSTICKY +#define GPIO_22_STICKY GPIO_NONSTICKY +#define GPIO_23_STICKY GPIO_NONSTICKY +#define GPIO_24_STICKY GPIO_NONSTICKY +#define GPIO_25_STICKY GPIO_NONSTICKY +#define GPIO_26_STICKY GPIO_NONSTICKY +#define GPIO_27_STICKY GPIO_NONSTICKY +#define GPIO_28_STICKY GPIO_NONSTICKY +#define GPIO_29_STICKY GPIO_NONSTICKY +#define GPIO_30_STICKY GPIO_NONSTICKY +#define GPIO_31_STICKY GPIO_NONSTICKY +#define GPIO_32_STICKY GPIO_NONSTICKY +#define GPIO_33_STICKY GPIO_NONSTICKY +#define GPIO_34_STICKY GPIO_NONSTICKY +#define GPIO_35_STICKY GPIO_NONSTICKY +#define GPIO_36_STICKY GPIO_NONSTICKY +#define GPIO_37_STICKY GPIO_NONSTICKY +#define GPIO_38_STICKY GPIO_NONSTICKY +#define GPIO_39_STICKY GPIO_NONSTICKY +#define GPIO_40_STICKY GPIO_NONSTICKY +#define GPIO_41_STICKY GPIO_NONSTICKY +#define GPIO_42_STICKY GPIO_NONSTICKY +#define GPIO_43_STICKY GPIO_NONSTICKY +#define GPIO_44_STICKY GPIO_NONSTICKY +#define GPIO_45_STICKY GPIO_NONSTICKY +#define GPIO_46_STICKY GPIO_NONSTICKY +#define GPIO_47_STICKY GPIO_NONSTICKY +#define GPIO_48_STICKY GPIO_NONSTICKY +#define GPIO_49_STICKY GPIO_NONSTICKY +#define GPIO_50_STICKY GPIO_NONSTICKY +#define GPIO_51_STICKY GPIO_NONSTICKY +#define GPIO_52_STICKY GPIO_NONSTICKY +#define GPIO_53_STICKY GPIO_NONSTICKY +#define GPIO_54_STICKY GPIO_NONSTICKY +#define GPIO_55_STICKY GPIO_NONSTICKY +#define GPIO_56_STICKY GPIO_NONSTICKY +#define GPIO_57_STICKY GPIO_NONSTICKY +#define GPIO_58_STICKY GPIO_NONSTICKY +#define GPIO_59_STICKY GPIO_NONSTICKY +#define GPIO_60_STICKY GPIO_NONSTICKY +#define GPIO_61_STICKY GPIO_NONSTICKY +#define GPIO_62_STICKY GPIO_NONSTICKY +#define GPIO_63_STICKY GPIO_NONSTICKY +#define GPIO_64_STICKY GPIO_NONSTICKY +#define GPIO_65_STICKY GPIO_NONSTICKY +#define GPIO_66_STICKY GPIO_NONSTICKY +#define GPIO_67_STICKY GPIO_NONSTICKY +#define GPIO_68_STICKY GPIO_NONSTICKY +#define GPIO_69_STICKY GPIO_NONSTICKY +#define GPIO_70_STICKY GPIO_NONSTICKY +#define GPIO_71_STICKY GPIO_NONSTICKY +#define GPIO_72_STICKY GPIO_NONSTICKY +#define GPIO_73_STICKY GPIO_NONSTICKY +#define GPIO_74_STICKY GPIO_NONSTICKY +#define GPIO_75_STICKY GPIO_NONSTICKY +#define GPIO_76_STICKY GPIO_NONSTICKY +#define GPIO_77_STICKY GPIO_NONSTICKY +#define GPIO_78_STICKY GPIO_NONSTICKY +#define GPIO_79_STICKY GPIO_NONSTICKY +#define GPIO_80_STICKY GPIO_NONSTICKY +#define GPIO_81_STICKY GPIO_NONSTICKY +#define GPIO_82_STICKY GPIO_NONSTICKY +#define GPIO_83_STICKY GPIO_NONSTICKY +#define GPIO_84_STICKY GPIO_NONSTICKY +#define GPIO_85_STICKY GPIO_NONSTICKY +#define GPIO_86_STICKY GPIO_NONSTICKY +#define GPIO_87_STICKY GPIO_NONSTICKY +#define GPIO_88_STICKY GPIO_NONSTICKY +#define GPIO_89_STICKY GPIO_NONSTICKY +#define GPIO_90_STICKY GPIO_NONSTICKY +#define GPIO_91_STICKY GPIO_NONSTICKY +#define GPIO_92_STICKY GPIO_NONSTICKY +#define GPIO_93_STICKY GPIO_NONSTICKY +#define GPIO_94_STICKY GPIO_NONSTICKY +#define GPIO_95_STICKY GPIO_NONSTICKY +#define GPIO_96_STICKY GPIO_NONSTICKY +#define GPIO_97_STICKY GPIO_NONSTICKY +#define GPIO_98_STICKY GPIO_NONSTICKY +#define GPIO_99_STICKY GPIO_NONSTICKY +#define GPIO_100_STICKY GPIO_NONSTICKY +#define GPIO_101_STICKY GPIO_NONSTICKY +#define GPIO_102_STICKY GPIO_STICKY +#define GPIO_103_STICKY GPIO_STICKY +#define GPIO_104_STICKY GPIO_NONSTICKY +#define GPIO_105_STICKY GPIO_NONSTICKY +#define GPIO_106_STICKY GPIO_NONSTICKY +#define GPIO_107_STICKY GPIO_NONSTICKY +#define GPIO_108_STICKY GPIO_STICKY +#define GPIO_109_STICKY GPIO_NONSTICKY +#define GPIO_110_STICKY GPIO_NONSTICKY +#define GPIO_111_STICKY GPIO_NONSTICKY +#define GPIO_112_STICKY GPIO_NONSTICKY +#define GPIO_113_STICKY GPIO_NONSTICKY +#define GPIO_114_STICKY GPIO_NONSTICKY +#define GPIO_115_STICKY GPIO_NONSTICKY +#define GPIO_116_STICKY GPIO_NONSTICKY +#define GPIO_117_STICKY GPIO_NONSTICKY +#define GPIO_118_STICKY GPIO_NONSTICKY +#define GPIO_119_STICKY GPIO_NONSTICKY +#define GPIO_120_STICKY GPIO_NONSTICKY +#define GPIO_121_STICKY GPIO_NONSTICKY +#define GPIO_122_STICKY GPIO_NONSTICKY +#define GPIO_123_STICKY GPIO_NONSTICKY +#define GPIO_124_STICKY GPIO_NONSTICKY +#define GPIO_125_STICKY GPIO_NONSTICKY +#define GPIO_126_STICKY GPIO_NONSTICKY +#define GPIO_127_STICKY GPIO_NONSTICKY +#define GPIO_128_STICKY GPIO_NONSTICKY +#define GPIO_129_STICKY GPIO_NONSTICKY +#define GPIO_130_STICKY GPIO_NONSTICKY +#define GPIO_131_STICKY GPIO_NONSTICKY +#define GPIO_132_STICKY GPIO_NONSTICKY +#define GPIO_133_STICKY GPIO_NONSTICKY +#define GPIO_134_STICKY GPIO_NONSTICKY +#define GPIO_135_STICKY GPIO_NONSTICKY +#define GPIO_136_STICKY GPIO_NONSTICKY +#define GPIO_137_STICKY GPIO_NONSTICKY +#define GPIO_138_STICKY GPIO_NONSTICKY +#define GPIO_139_STICKY GPIO_NONSTICKY +#define GPIO_140_STICKY GPIO_NONSTICKY +#define GPIO_141_STICKY GPIO_NONSTICKY +#define GPIO_142_STICKY GPIO_NONSTICKY +#define GPIO_143_STICKY GPIO_NONSTICKY +#define GPIO_144_STICKY GPIO_NONSTICKY +#define GPIO_145_STICKY GPIO_NONSTICKY +#define GPIO_146_STICKY GPIO_NONSTICKY +#define GPIO_147_STICKY GPIO_NONSTICKY +#define GPIO_148_STICKY GPIO_NONSTICKY +#define GPIO_149_STICKY GPIO_NONSTICKY +#define GPIO_150_STICKY GPIO_NONSTICKY +#define GPIO_151_STICKY GPIO_NONSTICKY +#define GPIO_152_STICKY GPIO_NONSTICKY +#define GPIO_153_STICKY GPIO_NONSTICKY +#define GPIO_154_STICKY GPIO_NONSTICKY +#define GPIO_155_STICKY GPIO_NONSTICKY +#define GPIO_156_STICKY GPIO_NONSTICKY +#define GPIO_157_STICKY GPIO_NONSTICKY +#define GPIO_158_STICKY GPIO_NONSTICKY +#define GPIO_159_STICKY GPIO_NONSTICKY +#define GPIO_160_STICKY GPIO_NONSTICKY +#define GPIO_161_STICKY GPIO_NONSTICKY +#define GPIO_162_STICKY GPIO_NONSTICKY +#define GPIO_163_STICKY GPIO_NONSTICKY +#define GPIO_164_STICKY GPIO_NONSTICKY +#define GPIO_165_STICKY GPIO_NONSTICKY +#define GPIO_166_STICKY GPIO_NONSTICKY +#define GPIO_167_STICKY GPIO_NONSTICKY +#define GPIO_168_STICKY GPIO_NONSTICKY +#define GPIO_169_STICKY GPIO_NONSTICKY +#define GPIO_170_STICKY GPIO_STICKY +#define GPIO_171_STICKY GPIO_NONSTICKY +#define GPIO_172_STICKY GPIO_STICKY +#define GPIO_173_STICKY GPIO_NONSTICKY +#define GPIO_174_STICKY GPIO_NONSTICKY +#define GPIO_175_STICKY GPIO_NONSTICKY +#define GPIO_176_STICKY GPIO_NONSTICKY +#define GPIO_177_STICKY GPIO_NONSTICKY +#define GPIO_178_STICKY GPIO_NONSTICKY +#define GPIO_179_STICKY GPIO_NONSTICKY +#define GPIO_180_STICKY GPIO_NONSTICKY +#define GPIO_181_STICKY GPIO_NONSTICKY +#define GPIO_182_STICKY GPIO_NONSTICKY +#define GPIO_183_STICKY GPIO_NONSTICKY +#define GPIO_184_STICKY GPIO_NONSTICKY +#define GPIO_185_STICKY GPIO_NONSTICKY +#define GPIO_186_STICKY GPIO_NONSTICKY +#define GPIO_187_STICKY GPIO_NONSTICKY +#define GPIO_188_STICKY GPIO_NONSTICKY +#define GPIO_189_STICKY GPIO_NONSTICKY +#define GPIO_190_STICKY GPIO_NONSTICKY +#define GPIO_191_STICKY GPIO_NONSTICKY +#define GPIO_192_STICKY GPIO_NONSTICKY +#define GPIO_193_STICKY GPIO_NONSTICKY +#define GPIO_194_STICKY GPIO_NONSTICKY +#define GPIO_195_STICKY GPIO_NONSTICKY +#define GPIO_196_STICKY GPIO_NONSTICKY +#define GPIO_197_STICKY GPIO_NONSTICKY +#define GPIO_198_STICKY GPIO_NONSTICKY +#define GPIO_199_STICKY GPIO_NONSTICKY +#define GPIO_200_STICKY GPIO_NONSTICKY +#define GPIO_201_STICKY GPIO_NONSTICKY +#define GPIO_202_STICKY GPIO_NONSTICKY +#define GPIO_203_STICKY GPIO_NONSTICKY +#define GPIO_204_STICKY GPIO_NONSTICKY +#define GPIO_205_STICKY GPIO_NONSTICKY +#define GPIO_206_STICKY GPIO_NONSTICKY +#define GPIO_207_STICKY GPIO_NONSTICKY +#define GPIO_208_STICKY GPIO_NONSTICKY +#define GPIO_209_STICKY GPIO_NONSTICKY +#define GPIO_210_STICKY GPIO_NONSTICKY +#define GPIO_211_STICKY GPIO_NONSTICKY +#define GPIO_212_STICKY GPIO_NONSTICKY +#define GPIO_213_STICKY GPIO_NONSTICKY +#define GPIO_214_STICKY GPIO_NONSTICKY +#define GPIO_215_STICKY GPIO_NONSTICKY +#define GPIO_216_STICKY GPIO_NONSTICKY +#define GPIO_217_STICKY GPIO_NONSTICKY +#define GPIO_218_STICKY GPIO_NONSTICKY +#define GPIO_219_STICKY GPIO_NONSTICKY +#define GPIO_220_STICKY GPIO_NONSTICKY +#define GPIO_221_STICKY GPIO_NONSTICKY +#define GPIO_222_STICKY GPIO_NONSTICKY +#define GPIO_223_STICKY GPIO_NONSTICKY +#define GPIO_224_STICKY GPIO_NONSTICKY +#define GPIO_225_STICKY GPIO_NONSTICKY +#define GPIO_226_STICKY GPIO_NONSTICKY +#define GPIO_227_STICKY GPIO_NONSTICKY +#define GPIO_228_STICKY GPIO_NONSTICKY +#define GPIO_229_STICKY GPIO_NONSTICKY + +#define PULLUP_ENABLE (0<<3) +#define PULLUP_DISABLE (1<<3) + +#define GPIO_00_PULLUP PULLUP_DISABLE +#define GPIO_01_PULLUP PULLUP_DISABLE +#define GPIO_02_PULLUP PULLUP_DISABLE +#define GPIO_03_PULLUP PULLUP_DISABLE +#define GPIO_04_PULLUP PULLUP_DISABLE +#define GPIO_05_PULLUP PULLUP_DISABLE +#define GPIO_06_PULLUP PULLUP_DISABLE +#define GPIO_07_PULLUP PULLUP_DISABLE +#define GPIO_08_PULLUP PULLUP_DISABLE +#define GPIO_09_PULLUP PULLUP_DISABLE +#define GPIO_10_PULLUP PULLUP_DISABLE +#define GPIO_11_PULLUP PULLUP_DISABLE +#define GPIO_12_PULLUP PULLUP_DISABLE +#define GPIO_13_PULLUP PULLUP_DISABLE +#define GPIO_14_PULLUP PULLUP_DISABLE +#define GPIO_15_PULLUP PULLUP_DISABLE +#define GPIO_16_PULLUP PULLUP_DISABLE +#define GPIO_17_PULLUP PULLUP_DISABLE +#define GPIO_18_PULLUP PULLUP_DISABLE +#define GPIO_19_PULLUP PULLUP_DISABLE +#define GPIO_20_PULLUP PULLUP_DISABLE +#define GPIO_21_PULLUP PULLUP_DISABLE +#define GPIO_22_PULLUP PULLUP_DISABLE +#define GPIO_23_PULLUP PULLUP_DISABLE +#define GPIO_24_PULLUP PULLUP_DISABLE +#define GPIO_25_PULLUP PULLUP_DISABLE +#define GPIO_26_PULLUP PULLUP_DISABLE +#define GPIO_27_PULLUP PULLUP_DISABLE +#define GPIO_28_PULLUP PULLUP_DISABLE +#define GPIO_29_PULLUP PULLUP_DISABLE +#define GPIO_30_PULLUP PULLUP_DISABLE +#define GPIO_31_PULLUP PULLUP_DISABLE +#define GPIO_32_PULLUP PULLUP_DISABLE +#define GPIO_33_PULLUP PULLUP_DISABLE +#define GPIO_34_PULLUP PULLUP_DISABLE +#define GPIO_35_PULLUP PULLUP_DISABLE +#define GPIO_36_PULLUP PULLUP_DISABLE +#define GPIO_37_PULLUP PULLUP_DISABLE +#define GPIO_38_PULLUP PULLUP_DISABLE +#define GPIO_39_PULLUP PULLUP_DISABLE +#define GPIO_40_PULLUP PULLUP_DISABLE +#define GPIO_41_PULLUP PULLUP_DISABLE +#define GPIO_42_PULLUP PULLUP_DISABLE +#define GPIO_43_PULLUP PULLUP_DISABLE +#define GPIO_44_PULLUP PULLUP_DISABLE +#define GPIO_45_PULLUP PULLUP_DISABLE +#define GPIO_46_PULLUP PULLUP_DISABLE +#define GPIO_47_PULLUP PULLUP_DISABLE +#define GPIO_48_PULLUP PULLUP_DISABLE +#define GPIO_49_PULLUP PULLUP_DISABLE +#define GPIO_50_PULLUP PULLUP_DISABLE +#define GPIO_51_PULLUP PULLUP_DISABLE +#define GPIO_52_PULLUP PULLUP_DISABLE +#define GPIO_53_PULLUP PULLUP_DISABLE +#define GPIO_54_PULLUP PULLUP_DISABLE +#define GPIO_55_PULLUP PULLUP_DISABLE +#define GPIO_56_PULLUP PULLUP_DISABLE +#define GPIO_57_PULLUP PULLUP_DISABLE +#define GPIO_58_PULLUP PULLUP_DISABLE +#define GPIO_59_PULLUP PULLUP_DISABLE +#define GPIO_60_PULLUP PULLUP_DISABLE +#define GPIO_61_PULLUP PULLUP_DISABLE +#define GPIO_62_PULLUP PULLUP_DISABLE +#define GPIO_63_PULLUP PULLUP_DISABLE +#define GPIO_64_PULLUP PULLUP_DISABLE +#define GPIO_65_PULLUP PULLUP_DISABLE +#define GPIO_66_PULLUP PULLUP_DISABLE +#define GPIO_67_PULLUP PULLUP_DISABLE +#define GPIO_68_PULLUP PULLUP_DISABLE +#define GPIO_69_PULLUP PULLUP_DISABLE +#define GPIO_70_PULLUP PULLUP_DISABLE +#define GPIO_71_PULLUP PULLUP_DISABLE +#define GPIO_72_PULLUP PULLUP_DISABLE +#define GPIO_73_PULLUP PULLUP_DISABLE +#define GPIO_74_PULLUP PULLUP_DISABLE +#define GPIO_75_PULLUP PULLUP_DISABLE +#define GPIO_76_PULLUP PULLUP_DISABLE +#define GPIO_77_PULLUP PULLUP_DISABLE +#define GPIO_78_PULLUP PULLUP_DISABLE +#define GPIO_79_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_81_PULLUP PULLUP_DISABLE +#define GPIO_82_PULLUP PULLUP_DISABLE +#define GPIO_83_PULLUP PULLUP_DISABLE +#define GPIO_84_PULLUP PULLUP_DISABLE +#define GPIO_85_PULLUP PULLUP_DISABLE +#define GPIO_86_PULLUP PULLUP_DISABLE +#define GPIO_87_PULLUP PULLUP_DISABLE +#define GPIO_88_PULLUP PULLUP_DISABLE +#define GPIO_89_PULLUP PULLUP_DISABLE +#define GPIO_90_PULLUP PULLUP_DISABLE +#define GPIO_91_PULLUP PULLUP_DISABLE +#define GPIO_92_PULLUP PULLUP_DISABLE +#define GPIO_93_PULLUP PULLUP_DISABLE +#define GPIO_94_PULLUP PULLUP_DISABLE +#define GPIO_95_PULLUP PULLUP_DISABLE +#define GPIO_96_PULLUP PULLUP_DISABLE +#define GPIO_97_PULLUP PULLUP_DISABLE +#define GPIO_98_PULLUP PULLUP_DISABLE +#define GPIO_99_PULLUP PULLUP_DISABLE +#define GPIO_100_PULLUP PULLUP_DISABLE +#define GPIO_101_PULLUP PULLUP_DISABLE +#define GPIO_102_PULLUP PULLUP_DISABLE +#define GPIO_103_PULLUP PULLUP_DISABLE +#define GPIO_104_PULLUP PULLUP_DISABLE +#define GPIO_105_PULLUP PULLUP_DISABLE +#define GPIO_106_PULLUP PULLUP_DISABLE +#define GPIO_107_PULLUP PULLUP_DISABLE +#define GPIO_108_PULLUP PULLUP_DISABLE +#define GPIO_109_PULLUP PULLUP_DISABLE +#define GPIO_110_PULLUP PULLUP_DISABLE +#define GPIO_111_PULLUP PULLUP_DISABLE +#define GPIO_112_PULLUP PULLUP_DISABLE +#define GPIO_113_PULLUP PULLUP_DISABLE +#define GPIO_114_PULLUP PULLUP_DISABLE +#define GPIO_115_PULLUP PULLUP_DISABLE +#define GPIO_116_PULLUP PULLUP_DISABLE +#define GPIO_117_PULLUP PULLUP_DISABLE +#define GPIO_118_PULLUP PULLUP_ENABLE +#define GPIO_119_PULLUP PULLUP_DISABLE +#define GPIO_120_PULLUP PULLUP_DISABLE +#define GPIO_121_PULLUP PULLUP_DISABLE +#define GPIO_122_PULLUP PULLUP_DISABLE +#define GPIO_123_PULLUP PULLUP_DISABLE +#define GPIO_124_PULLUP PULLUP_DISABLE +#define GPIO_125_PULLUP PULLUP_DISABLE +#define GPIO_126_PULLUP PULLUP_DISABLE +#define GPIO_127_PULLUP PULLUP_DISABLE +#define GPIO_128_PULLUP PULLUP_DISABLE +#define GPIO_129_PULLUP PULLUP_DISABLE +#define GPIO_130_PULLUP PULLUP_DISABLE +#define GPIO_131_PULLUP PULLUP_DISABLE +#define GPIO_132_PULLUP PULLUP_DISABLE +#define GPIO_133_PULLUP PULLUP_DISABLE +#define GPIO_134_PULLUP PULLUP_DISABLE +#define GPIO_135_PULLUP PULLUP_DISABLE +#define GPIO_136_PULLUP PULLUP_DISABLE +#define GPIO_137_PULLUP PULLUP_DISABLE +#define GPIO_138_PULLUP PULLUP_DISABLE +#define GPIO_139_PULLUP PULLUP_DISABLE +#define GPIO_140_PULLUP PULLUP_DISABLE +#define GPIO_141_PULLUP PULLUP_DISABLE +#define GPIO_142_PULLUP PULLUP_DISABLE +#define GPIO_143_PULLUP PULLUP_DISABLE +#define GPIO_144_PULLUP PULLUP_DISABLE +#define GPIO_145_PULLUP PULLUP_DISABLE +#define GPIO_146_PULLUP PULLUP_DISABLE +#define GPIO_147_PULLUP PULLUP_DISABLE +#define GPIO_148_PULLUP PULLUP_DISABLE +#define GPIO_149_PULLUP PULLUP_DISABLE +#define GPIO_150_PULLUP PULLUP_DISABLE +#define GPIO_151_PULLUP PULLUP_DISABLE +#define GPIO_152_PULLUP PULLUP_DISABLE +#define GPIO_153_PULLUP PULLUP_DISABLE +#define GPIO_154_PULLUP PULLUP_DISABLE +#define GPIO_155_PULLUP PULLUP_DISABLE +#define GPIO_156_PULLUP PULLUP_DISABLE +#define GPIO_157_PULLUP PULLUP_DISABLE +#define GPIO_158_PULLUP PULLUP_DISABLE +#define GPIO_159_PULLUP PULLUP_DISABLE +#define GPIO_160_PULLUP PULLUP_DISABLE +#define GPIO_161_PULLUP PULLUP_DISABLE +#define GPIO_162_PULLUP PULLUP_DISABLE +#define GPIO_163_PULLUP PULLUP_DISABLE +#define GPIO_164_PULLUP PULLUP_DISABLE +#define GPIO_165_PULLUP PULLUP_DISABLE +#define GPIO_166_PULLUP PULLUP_DISABLE +#define GPIO_167_PULLUP PULLUP_DISABLE +#define GPIO_168_PULLUP PULLUP_DISABLE +#define GPIO_169_PULLUP PULLUP_DISABLE +#define GPIO_170_PULLUP PULLUP_DISABLE +#define GPIO_171_PULLUP PULLUP_DISABLE +#define GPIO_172_PULLUP PULLUP_DISABLE +#define GPIO_173_PULLUP PULLUP_DISABLE +#define GPIO_174_PULLUP PULLUP_DISABLE +#define GPIO_175_PULLUP PULLUP_DISABLE +#define GPIO_176_PULLUP PULLUP_DISABLE +#define GPIO_177_PULLUP PULLUP_DISABLE +#define GPIO_178_PULLUP PULLUP_DISABLE +#define GPIO_179_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_181_PULLUP PULLUP_DISABLE +#define GPIO_182_PULLUP PULLUP_DISABLE +#define GPIO_183_PULLUP PULLUP_DISABLE +#define GPIO_184_PULLUP PULLUP_DISABLE +#define GPIO_185_PULLUP PULLUP_DISABLE +#define GPIO_186_PULLUP PULLUP_DISABLE +#define GPIO_187_PULLUP PULLUP_DISABLE +#define GPIO_188_PULLUP PULLUP_DISABLE +#define GPIO_189_PULLUP PULLUP_DISABLE +#define GPIO_190_PULLUP PULLUP_DISABLE +#define GPIO_191_PULLUP PULLUP_DISABLE +#define GPIO_192_PULLUP PULLUP_DISABLE +#define GPIO_193_PULLUP PULLUP_DISABLE +#define GPIO_194_PULLUP PULLUP_DISABLE +#define GPIO_195_PULLUP PULLUP_DISABLE +#define GPIO_196_PULLUP PULLUP_DISABLE +#define GPIO_197_PULLUP PULLUP_DISABLE +#define GPIO_198_PULLUP PULLUP_DISABLE +#define GPIO_199_PULLUP PULLUP_DISABLE +#define GPIO_200_PULLUP PULLUP_DISABLE +#define GPIO_201_PULLUP PULLUP_DISABLE +#define GPIO_202_PULLUP PULLUP_DISABLE +#define GPIO_203_PULLUP PULLUP_DISABLE +#define GPIO_204_PULLUP PULLUP_DISABLE +#define GPIO_205_PULLUP PULLUP_DISABLE +#define GPIO_206_PULLUP PULLUP_DISABLE +#define GPIO_207_PULLUP PULLUP_DISABLE +#define GPIO_208_PULLUP PULLUP_DISABLE +#define GPIO_209_PULLUP PULLUP_DISABLE +#define GPIO_210_PULLUP PULLUP_DISABLE +#define GPIO_211_PULLUP PULLUP_DISABLE +#define GPIO_212_PULLUP PULLUP_DISABLE +#define GPIO_213_PULLUP PULLUP_DISABLE +#define GPIO_214_PULLUP PULLUP_DISABLE +#define GPIO_215_PULLUP PULLUP_DISABLE +#define GPIO_216_PULLUP PULLUP_DISABLE +#define GPIO_217_PULLUP PULLUP_DISABLE +#define GPIO_218_PULLUP PULLUP_DISABLE +#define GPIO_219_PULLUP PULLUP_DISABLE +#define GPIO_220_PULLUP PULLUP_DISABLE +#define GPIO_221_PULLUP PULLUP_DISABLE +#define GPIO_222_PULLUP PULLUP_DISABLE +#define GPIO_223_PULLUP PULLUP_DISABLE +#define GPIO_224_PULLUP PULLUP_DISABLE +#define GPIO_225_PULLUP PULLUP_DISABLE +#define GPIO_226_PULLUP PULLUP_DISABLE +#define GPIO_227_PULLUP PULLUP_DISABLE +#define GPIO_228_PULLUP PULLUP_DISABLE +#define GPIO_229_PULLUP PULLUP_DISABLE + +#define PULLDOWN_ENABLE (1<<4) +#define PULLDOWN_DISABLE (0<<4) + +#define GPIO_00_PULLDOWN PULLDOWN_DISABLE +#define GPIO_01_PULLDOWN PULLDOWN_DISABLE +#define GPIO_02_PULLDOWN PULLDOWN_DISABLE +#define GPIO_03_PULLDOWN PULLDOWN_DISABLE +#define GPIO_04_PULLDOWN PULLDOWN_DISABLE +#define GPIO_05_PULLDOWN PULLDOWN_DISABLE +#define GPIO_06_PULLDOWN PULLDOWN_DISABLE +#define GPIO_07_PULLDOWN PULLDOWN_DISABLE +#define GPIO_08_PULLDOWN PULLDOWN_DISABLE +#define GPIO_09_PULLDOWN PULLDOWN_DISABLE +#define GPIO_10_PULLDOWN PULLDOWN_DISABLE +#define GPIO_11_PULLDOWN PULLDOWN_DISABLE +#define GPIO_12_PULLDOWN PULLDOWN_DISABLE +#define GPIO_13_PULLDOWN PULLDOWN_DISABLE +#define GPIO_14_PULLDOWN PULLDOWN_DISABLE +#define GPIO_15_PULLDOWN PULLDOWN_DISABLE +#define GPIO_16_PULLDOWN PULLDOWN_DISABLE +#define GPIO_17_PULLDOWN PULLDOWN_DISABLE +#define GPIO_18_PULLDOWN PULLDOWN_DISABLE +#define GPIO_19_PULLDOWN PULLDOWN_DISABLE +#define GPIO_20_PULLDOWN PULLDOWN_DISABLE +#define GPIO_21_PULLDOWN PULLDOWN_DISABLE +#define GPIO_22_PULLDOWN PULLDOWN_DISABLE +#define GPIO_23_PULLDOWN PULLDOWN_DISABLE +#define GPIO_24_PULLDOWN PULLDOWN_DISABLE +#define GPIO_25_PULLDOWN PULLDOWN_DISABLE +#define GPIO_26_PULLDOWN PULLDOWN_DISABLE +#define GPIO_27_PULLDOWN PULLDOWN_DISABLE +#define GPIO_28_PULLDOWN PULLDOWN_DISABLE +#define GPIO_29_PULLDOWN PULLDOWN_DISABLE +#define GPIO_30_PULLDOWN PULLDOWN_DISABLE +#define GPIO_31_PULLDOWN PULLDOWN_DISABLE +#define GPIO_32_PULLDOWN PULLDOWN_DISABLE +#define GPIO_33_PULLDOWN PULLDOWN_DISABLE +#define GPIO_34_PULLDOWN PULLDOWN_DISABLE +#define GPIO_35_PULLDOWN PULLDOWN_DISABLE +#define GPIO_36_PULLDOWN PULLDOWN_DISABLE +#define GPIO_37_PULLDOWN PULLDOWN_DISABLE +#define GPIO_38_PULLDOWN PULLDOWN_DISABLE +#define GPIO_39_PULLDOWN PULLDOWN_DISABLE +#define GPIO_40_PULLDOWN PULLDOWN_DISABLE +#define GPIO_41_PULLDOWN PULLDOWN_DISABLE +#define GPIO_42_PULLDOWN PULLDOWN_DISABLE +#define GPIO_43_PULLDOWN PULLDOWN_DISABLE +#define GPIO_44_PULLDOWN PULLDOWN_DISABLE +#define GPIO_45_PULLDOWN PULLDOWN_DISABLE +#define GPIO_46_PULLDOWN PULLDOWN_DISABLE +#define GPIO_47_PULLDOWN PULLDOWN_DISABLE +#define GPIO_48_PULLDOWN PULLDOWN_DISABLE +#define GPIO_49_PULLDOWN PULLDOWN_DISABLE +#define GPIO_50_PULLDOWN PULLDOWN_DISABLE +#define GPIO_51_PULLDOWN PULLDOWN_DISABLE +#define GPIO_52_PULLDOWN PULLDOWN_DISABLE +#define GPIO_53_PULLDOWN PULLDOWN_DISABLE +#define GPIO_54_PULLDOWN PULLDOWN_DISABLE +#define GPIO_55_PULLDOWN PULLDOWN_DISABLE +#define GPIO_56_PULLDOWN PULLDOWN_DISABLE +#define GPIO_57_PULLDOWN PULLDOWN_DISABLE +#define GPIO_58_PULLDOWN PULLDOWN_DISABLE +#define GPIO_59_PULLDOWN PULLDOWN_DISABLE +#define GPIO_60_PULLDOWN PULLDOWN_DISABLE +#define GPIO_61_PULLDOWN PULLDOWN_DISABLE +#define GPIO_62_PULLDOWN PULLDOWN_DISABLE +#define GPIO_63_PULLDOWN PULLDOWN_DISABLE +#define GPIO_64_PULLDOWN PULLDOWN_DISABLE +#define GPIO_65_PULLDOWN PULLDOWN_DISABLE +#define GPIO_66_PULLDOWN PULLDOWN_DISABLE +#define GPIO_67_PULLDOWN PULLDOWN_DISABLE +#define GPIO_68_PULLDOWN PULLDOWN_DISABLE +#define GPIO_69_PULLDOWN PULLDOWN_DISABLE +#define GPIO_70_PULLDOWN PULLDOWN_DISABLE +#define GPIO_71_PULLDOWN PULLDOWN_DISABLE +#define GPIO_72_PULLDOWN PULLDOWN_DISABLE +#define GPIO_73_PULLDOWN PULLDOWN_DISABLE +#define GPIO_74_PULLDOWN PULLDOWN_DISABLE +#define GPIO_75_PULLDOWN PULLDOWN_DISABLE +#define GPIO_76_PULLDOWN PULLDOWN_DISABLE +#define GPIO_77_PULLDOWN PULLDOWN_DISABLE +#define GPIO_78_PULLDOWN PULLDOWN_DISABLE +#define GPIO_79_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_81_PULLDOWN PULLDOWN_DISABLE +#define GPIO_82_PULLDOWN PULLDOWN_DISABLE +#define GPIO_83_PULLDOWN PULLDOWN_DISABLE +#define GPIO_84_PULLDOWN PULLDOWN_DISABLE +#define GPIO_85_PULLDOWN PULLDOWN_DISABLE +#define GPIO_86_PULLDOWN PULLDOWN_DISABLE +#define GPIO_87_PULLDOWN PULLDOWN_DISABLE +#define GPIO_88_PULLDOWN PULLDOWN_DISABLE +#define GPIO_89_PULLDOWN PULLDOWN_DISABLE +#define GPIO_90_PULLDOWN PULLDOWN_DISABLE +#define GPIO_91_PULLDOWN PULLDOWN_DISABLE +#define GPIO_92_PULLDOWN PULLDOWN_DISABLE +#define GPIO_93_PULLDOWN PULLDOWN_DISABLE +#define GPIO_94_PULLDOWN PULLDOWN_DISABLE +#define GPIO_95_PULLDOWN PULLDOWN_DISABLE +#define GPIO_96_PULLDOWN PULLDOWN_DISABLE +#define GPIO_97_PULLDOWN PULLDOWN_DISABLE +#define GPIO_98_PULLDOWN PULLDOWN_DISABLE +#define GPIO_99_PULLDOWN PULLDOWN_DISABLE +#define GPIO_100_PULLDOWN PULLDOWN_DISABLE +#define GPIO_101_PULLDOWN PULLDOWN_DISABLE +#define GPIO_102_PULLDOWN PULLDOWN_DISABLE +#define GPIO_103_PULLDOWN PULLDOWN_DISABLE +#define GPIO_104_PULLDOWN PULLDOWN_DISABLE +#define GPIO_105_PULLDOWN PULLDOWN_DISABLE +#define GPIO_106_PULLDOWN PULLDOWN_DISABLE +#define GPIO_107_PULLDOWN PULLDOWN_DISABLE +#define GPIO_108_PULLDOWN PULLDOWN_DISABLE +#define GPIO_109_PULLDOWN PULLDOWN_DISABLE +#define GPIO_110_PULLDOWN PULLDOWN_DISABLE +#define GPIO_111_PULLDOWN PULLDOWN_DISABLE +#define GPIO_112_PULLDOWN PULLDOWN_DISABLE +#define GPIO_113_PULLDOWN PULLDOWN_DISABLE +#define GPIO_114_PULLDOWN PULLDOWN_DISABLE +#define GPIO_115_PULLDOWN PULLDOWN_DISABLE +#define GPIO_116_PULLDOWN PULLDOWN_DISABLE +#define GPIO_117_PULLDOWN PULLDOWN_DISABLE +#define GPIO_118_PULLDOWN PULLDOWN_DISABLE +#define GPIO_119_PULLDOWN PULLDOWN_DISABLE +#define GPIO_120_PULLDOWN PULLDOWN_DISABLE +#define GPIO_121_PULLDOWN PULLDOWN_DISABLE +#define GPIO_122_PULLDOWN PULLDOWN_DISABLE +#define GPIO_123_PULLDOWN PULLDOWN_DISABLE +#define GPIO_124_PULLDOWN PULLDOWN_DISABLE +#define GPIO_125_PULLDOWN PULLDOWN_DISABLE +#define GPIO_126_PULLDOWN PULLDOWN_DISABLE +#define GPIO_127_PULLDOWN PULLDOWN_DISABLE +#define GPIO_128_PULLDOWN PULLDOWN_DISABLE +#define GPIO_129_PULLDOWN PULLDOWN_DISABLE +#define GPIO_130_PULLDOWN PULLDOWN_DISABLE +#define GPIO_131_PULLDOWN PULLDOWN_DISABLE +#define GPIO_132_PULLDOWN PULLDOWN_DISABLE +#define GPIO_133_PULLDOWN PULLDOWN_DISABLE +#define GPIO_134_PULLDOWN PULLDOWN_DISABLE +#define GPIO_135_PULLDOWN PULLDOWN_DISABLE +#define GPIO_136_PULLDOWN PULLDOWN_DISABLE +#define GPIO_137_PULLDOWN PULLDOWN_DISABLE +#define GPIO_138_PULLDOWN PULLDOWN_DISABLE +#define GPIO_139_PULLDOWN PULLDOWN_DISABLE +#define GPIO_140_PULLDOWN PULLDOWN_DISABLE +#define GPIO_141_PULLDOWN PULLDOWN_DISABLE +#define GPIO_142_PULLDOWN PULLDOWN_DISABLE +#define GPIO_143_PULLDOWN PULLDOWN_DISABLE +#define GPIO_144_PULLDOWN PULLDOWN_DISABLE +#define GPIO_145_PULLDOWN PULLDOWN_DISABLE +#define GPIO_146_PULLDOWN PULLDOWN_DISABLE +#define GPIO_147_PULLDOWN PULLDOWN_DISABLE +#define GPIO_148_PULLDOWN PULLDOWN_DISABLE +#define GPIO_149_PULLDOWN PULLDOWN_DISABLE +#define GPIO_150_PULLDOWN PULLDOWN_DISABLE +#define GPIO_151_PULLDOWN PULLDOWN_DISABLE +#define GPIO_152_PULLDOWN PULLDOWN_DISABLE +#define GPIO_153_PULLDOWN PULLDOWN_DISABLE +#define GPIO_154_PULLDOWN PULLDOWN_DISABLE +#define GPIO_155_PULLDOWN PULLDOWN_DISABLE +#define GPIO_156_PULLDOWN PULLDOWN_DISABLE +#define GPIO_157_PULLDOWN PULLDOWN_DISABLE +#define GPIO_158_PULLDOWN PULLDOWN_DISABLE +#define GPIO_159_PULLDOWN PULLDOWN_DISABLE +#define GPIO_160_PULLDOWN PULLDOWN_DISABLE +#define GPIO_161_PULLDOWN PULLDOWN_DISABLE +#define GPIO_162_PULLDOWN PULLDOWN_ENABLE +#define GPIO_163_PULLDOWN PULLDOWN_ENABLE +#define GPIO_164_PULLDOWN PULLDOWN_ENABLE +#define GPIO_165_PULLDOWN PULLDOWN_DISABLE +#define GPIO_166_PULLDOWN PULLDOWN_DISABLE +#define GPIO_167_PULLDOWN PULLDOWN_ENABLE +#define GPIO_168_PULLDOWN PULLDOWN_DISABLE +#define GPIO_169_PULLDOWN PULLDOWN_DISABLE +#define GPIO_170_PULLDOWN PULLDOWN_DISABLE +#define GPIO_171_PULLDOWN PULLDOWN_DISABLE +#define GPIO_172_PULLDOWN PULLDOWN_DISABLE +#define GPIO_173_PULLDOWN PULLDOWN_DISABLE +#define GPIO_174_PULLDOWN PULLDOWN_DISABLE +#define GPIO_175_PULLDOWN PULLDOWN_DISABLE +#define GPIO_176_PULLDOWN PULLDOWN_DISABLE +#define GPIO_177_PULLDOWN PULLDOWN_DISABLE +#define GPIO_178_PULLDOWN PULLDOWN_DISABLE +#define GPIO_179_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_181_PULLDOWN PULLDOWN_DISABLE +#define GPIO_182_PULLDOWN PULLDOWN_DISABLE +#define GPIO_183_PULLDOWN PULLDOWN_DISABLE +#define GPIO_184_PULLDOWN PULLDOWN_DISABLE +#define GPIO_185_PULLDOWN PULLDOWN_ENABLE +#define GPIO_186_PULLDOWN PULLDOWN_ENABLE +#define GPIO_187_PULLDOWN PULLDOWN_DISABLE +#define GPIO_188_PULLDOWN PULLDOWN_DISABLE +#define GPIO_189_PULLDOWN PULLDOWN_DISABLE +#define GPIO_190_PULLDOWN PULLDOWN_DISABLE +#define GPIO_191_PULLDOWN PULLDOWN_DISABLE +#define GPIO_192_PULLDOWN PULLDOWN_DISABLE +#define GPIO_193_PULLDOWN PULLDOWN_DISABLE +#define GPIO_194_PULLDOWN PULLDOWN_DISABLE +#define GPIO_195_PULLDOWN PULLDOWN_DISABLE +#define GPIO_196_PULLDOWN PULLDOWN_DISABLE +#define GPIO_197_PULLDOWN PULLDOWN_DISABLE +#define GPIO_198_PULLDOWN PULLDOWN_DISABLE +#define GPIO_199_PULLDOWN PULLDOWN_DISABLE +#define GPIO_200_PULLDOWN PULLDOWN_DISABLE +#define GPIO_201_PULLDOWN PULLDOWN_DISABLE +#define GPIO_202_PULLDOWN PULLDOWN_DISABLE +#define GPIO_203_PULLDOWN PULLDOWN_DISABLE +#define GPIO_204_PULLDOWN PULLDOWN_DISABLE +#define GPIO_205_PULLDOWN PULLDOWN_DISABLE +#define GPIO_206_PULLDOWN PULLDOWN_DISABLE +#define GPIO_207_PULLDOWN PULLDOWN_DISABLE +#define GPIO_208_PULLDOWN PULLDOWN_DISABLE +#define GPIO_209_PULLDOWN PULLDOWN_DISABLE +#define GPIO_210_PULLDOWN PULLDOWN_DISABLE +#define GPIO_211_PULLDOWN PULLDOWN_DISABLE +#define GPIO_212_PULLDOWN PULLDOWN_DISABLE +#define GPIO_213_PULLDOWN PULLDOWN_DISABLE +#define GPIO_214_PULLDOWN PULLDOWN_DISABLE +#define GPIO_215_PULLDOWN PULLDOWN_DISABLE +#define GPIO_216_PULLDOWN PULLDOWN_DISABLE +#define GPIO_217_PULLDOWN PULLDOWN_DISABLE +#define GPIO_218_PULLDOWN PULLDOWN_DISABLE +#define GPIO_219_PULLDOWN PULLDOWN_DISABLE +#define GPIO_220_PULLDOWN PULLDOWN_DISABLE +#define GPIO_221_PULLDOWN PULLDOWN_DISABLE +#define GPIO_222_PULLDOWN PULLDOWN_DISABLE +#define GPIO_223_PULLDOWN PULLDOWN_DISABLE +#define GPIO_224_PULLDOWN PULLDOWN_DISABLE +#define GPIO_225_PULLDOWN PULLDOWN_DISABLE +#define GPIO_226_PULLDOWN PULLDOWN_DISABLE +#define GPIO_227_PULLDOWN PULLDOWN_DISABLE +#define GPIO_228_PULLDOWN PULLDOWN_DISABLE +#define GPIO_229_PULLDOWN PULLDOWN_DISABLE + +#define EVENT_DISABLE 0 +#define EVENT_ENABLE 1 + +#define GEVENT_00_EVENTENABLE EVENT_DISABLE +#define GEVENT_01_EVENTENABLE EVENT_DISABLE +#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# +#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# +#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# +#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_06_EVENTENABLE EVENT_DISABLE +#define GEVENT_07_EVENTENABLE EVENT_DISABLE +#define GEVENT_08_EVENTENABLE EVENT_DISABLE +#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_10_EVENTENABLE EVENT_DISABLE +#define GEVENT_11_EVENTENABLE EVENT_DISABLE +#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_13_EVENTENABLE EVENT_DISABLE +#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# +#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# +#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA +#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_18_EVENTENABLE EVENT_DISABLE +#define GEVENT_19_EVENTENABLE EVENT_DISABLE +#define GEVENT_20_EVENTENABLE EVENT_DISABLE +#define GEVENT_21_EVENTENABLE EVENT_DISABLE +#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# +#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# + +#define SCITRIG_LOW 0 +#define SCITRIG_HI 1 + +#define GEVENT_00_SCITRIG SCITRIG_LOW +#define GEVENT_01_SCITRIG SCITRIG_LOW +#define GEVENT_02_SCITRIG SCITRIG_LOW +#define GEVENT_03_SCITRIG SCITRIG_LOW +#define GEVENT_04_SCITRIG SCITRIG_LOW +#define GEVENT_05_SCITRIG SCITRIG_LOW +#define GEVENT_06_SCITRIG SCITRIG_LOW +#define GEVENT_07_SCITRIG SCITRIG_LOW +#define GEVENT_08_SCITRIG SCITRIG_LOW +#define GEVENT_09_SCITRIG SCITRIG_LOW +#define GEVENT_10_SCITRIG SCITRIG_LOW +#define GEVENT_11_SCITRIG SCITRIG_LOW +#define GEVENT_12_SCITRIG SCITRIG_LOW +#define GEVENT_13_SCITRIG SCITRIG_LOW +#define GEVENT_14_SCITRIG SCITRIG_LOW +#define GEVENT_15_SCITRIG SCITRIG_LOW +#define GEVENT_16_SCITRIG SCITRIG_LOW +#define GEVENT_17_SCITRIG SCITRIG_HI +#define GEVENT_18_SCITRIG SCITRIG_LOW +#define GEVENT_19_SCITRIG SCITRIG_LOW +#define GEVENT_20_SCITRIG SCITRIG_LOW +#define GEVENT_21_SCITRIG SCITRIG_LOW +#define GEVENT_22_SCITRIG SCITRIG_LOW +#define GEVENT_23_SCITRIG SCITRIG_LOW + +#define SCILEVEL_EDGE 0 +#define SCILEVEL_LEVEL 1 + +#define GEVENT_00_SCILEVEL SCILEVEL_EDGE +#define GEVENT_01_SCILEVEL SCILEVEL_EDGE +#define GEVENT_02_SCILEVEL SCILEVEL_EDGE +#define GEVENT_03_SCILEVEL SCILEVEL_EDGE +#define GEVENT_04_SCILEVEL SCILEVEL_EDGE +#define GEVENT_05_SCILEVEL SCILEVEL_EDGE +#define GEVENT_06_SCILEVEL SCILEVEL_EDGE +#define GEVENT_07_SCILEVEL SCILEVEL_EDGE +#define GEVENT_08_SCILEVEL SCILEVEL_EDGE +#define GEVENT_09_SCILEVEL SCILEVEL_EDGE +#define GEVENT_10_SCILEVEL SCILEVEL_EDGE +#define GEVENT_11_SCILEVEL SCILEVEL_EDGE +#define GEVENT_12_SCILEVEL SCILEVEL_EDGE +#define GEVENT_13_SCILEVEL SCILEVEL_EDGE +#define GEVENT_14_SCILEVEL SCILEVEL_EDGE +#define GEVENT_15_SCILEVEL SCILEVEL_EDGE +#define GEVENT_16_SCILEVEL SCILEVEL_EDGE +#define GEVENT_17_SCILEVEL SCILEVEL_EDGE +#define GEVENT_18_SCILEVEL SCILEVEL_EDGE +#define GEVENT_19_SCILEVEL SCILEVEL_EDGE +#define GEVENT_20_SCILEVEL SCILEVEL_EDGE +#define GEVENT_21_SCILEVEL SCILEVEL_EDGE +#define GEVENT_22_SCILEVEL SCILEVEL_EDGE +#define GEVENT_23_SCILEVEL SCILEVEL_EDGE + +#define SMISCI_DISABLE 0 +#define SMISCI_ENABLE 1 + +#define GEVENT_00_SMISCIEN SMISCI_DISABLE +#define GEVENT_01_SMISCIEN SMISCI_DISABLE +#define GEVENT_02_SMISCIEN SMISCI_DISABLE +#define GEVENT_03_SMISCIEN SMISCI_DISABLE +#define GEVENT_04_SMISCIEN SMISCI_DISABLE +#define GEVENT_05_SMISCIEN SMISCI_DISABLE +#define GEVENT_06_SMISCIEN SMISCI_DISABLE +#define GEVENT_07_SMISCIEN SMISCI_DISABLE +#define GEVENT_08_SMISCIEN SMISCI_DISABLE +#define GEVENT_09_SMISCIEN SMISCI_DISABLE +#define GEVENT_10_SMISCIEN SMISCI_DISABLE +#define GEVENT_11_SMISCIEN SMISCI_DISABLE +#define GEVENT_12_SMISCIEN SMISCI_DISABLE +#define GEVENT_13_SMISCIEN SMISCI_DISABLE +#define GEVENT_14_SMISCIEN SMISCI_DISABLE +#define GEVENT_15_SMISCIEN SMISCI_DISABLE +#define GEVENT_16_SMISCIEN SMISCI_DISABLE +#define GEVENT_17_SMISCIEN SMISCI_DISABLE +#define GEVENT_18_SMISCIEN SMISCI_DISABLE +#define GEVENT_19_SMISCIEN SMISCI_DISABLE +#define GEVENT_20_SMISCIEN SMISCI_DISABLE +#define GEVENT_21_SMISCIEN SMISCI_DISABLE +#define GEVENT_22_SMISCIEN SMISCI_DISABLE +#define GEVENT_23_SMISCIEN SMISCI_DISABLE + +#define SCIS0_DISABLE 0 +#define SCIS0_ENABLE 1 + +#define GEVENT_00_SCIS0EN SCIS0_DISABLE +#define GEVENT_01_SCIS0EN SCIS0_DISABLE +#define GEVENT_02_SCIS0EN SCIS0_DISABLE +#define GEVENT_03_SCIS0EN SCIS0_DISABLE +#define GEVENT_04_SCIS0EN SCIS0_DISABLE +#define GEVENT_05_SCIS0EN SCIS0_DISABLE +#define GEVENT_06_SCIS0EN SCIS0_DISABLE +#define GEVENT_07_SCIS0EN SCIS0_DISABLE +#define GEVENT_08_SCIS0EN SCIS0_DISABLE +#define GEVENT_09_SCIS0EN SCIS0_DISABLE +#define GEVENT_10_SCIS0EN SCIS0_DISABLE +#define GEVENT_11_SCIS0EN SCIS0_DISABLE +#define GEVENT_12_SCIS0EN SCIS0_DISABLE +#define GEVENT_13_SCIS0EN SCIS0_DISABLE +#define GEVENT_14_SCIS0EN SCIS0_DISABLE +#define GEVENT_15_SCIS0EN SCIS0_DISABLE +#define GEVENT_16_SCIS0EN SCIS0_DISABLE +#define GEVENT_17_SCIS0EN SCIS0_DISABLE +#define GEVENT_18_SCIS0EN SCIS0_DISABLE +#define GEVENT_19_SCIS0EN SCIS0_DISABLE +#define GEVENT_20_SCIS0EN SCIS0_DISABLE +#define GEVENT_21_SCIS0EN SCIS0_DISABLE +#define GEVENT_22_SCIS0EN SCIS0_DISABLE +#define GEVENT_23_SCIS0EN SCIS0_DISABLE + +#define GEVENT_SCIMASK 0x1F +#define GEVENT_00_SCIMAP 0 +#define GEVENT_01_SCIMAP 1 +#define GEVENT_02_SCIMAP 2 +#define GEVENT_03_SCIMAP 3 +#define GEVENT_04_SCIMAP 4 +#define GEVENT_05_SCIMAP 5 +#define GEVENT_06_SCIMAP 6 +#define GEVENT_07_SCIMAP 7 +#define GEVENT_08_SCIMAP 8 +#define GEVENT_09_SCIMAP 9 +#define GEVENT_10_SCIMAP 10 +#define GEVENT_11_SCIMAP 11 +#define GEVENT_12_SCIMAP 12 +#define GEVENT_13_SCIMAP 13 +#define GEVENT_14_SCIMAP 14 +#define GEVENT_15_SCIMAP 15 +#define GEVENT_16_SCIMAP 16 +#define GEVENT_17_SCIMAP 17 +#define GEVENT_18_SCIMAP 18 +#define GEVENT_19_SCIMAP 19 +#define GEVENT_20_SCIMAP 20 +#define GEVENT_21_SCIMAP 21 +#define GEVENT_22_SCIMAP 22 +#define GEVENT_23_SCIMAP 23 + +#define SMITRIG_LOW 0 +#define SMITRIG_HI 1 + +#define GEVENT_00_SMITRIG SMITRIG_HI +#define GEVENT_01_SMITRIG SMITRIG_HI +#define GEVENT_02_SMITRIG SMITRIG_HI +#define GEVENT_03_SMITRIG SMITRIG_HI +#define GEVENT_04_SMITRIG SMITRIG_HI +#define GEVENT_05_SMITRIG SMITRIG_HI +#define GEVENT_06_SMITRIG SMITRIG_HI +#define GEVENT_07_SMITRIG SMITRIG_HI +#define GEVENT_08_SMITRIG SMITRIG_HI +#define GEVENT_09_SMITRIG SMITRIG_HI +#define GEVENT_10_SMITRIG SMITRIG_HI +#define GEVENT_11_SMITRIG SMITRIG_HI +#define GEVENT_12_SMITRIG SMITRIG_HI +#define GEVENT_13_SMITRIG SMITRIG_HI +#define GEVENT_14_SMITRIG SMITRIG_HI +#define GEVENT_15_SMITRIG SMITRIG_HI +#define GEVENT_16_SMITRIG SMITRIG_HI +#define GEVENT_17_SMITRIG SMITRIG_HI +#define GEVENT_18_SMITRIG SMITRIG_HI +#define GEVENT_19_SMITRIG SMITRIG_HI +#define GEVENT_20_SMITRIG SMITRIG_HI +#define GEVENT_21_SMITRIG SMITRIG_HI +#define GEVENT_22_SMITRIG SMITRIG_HI +#define GEVENT_23_SMITRIG SMITRIG_HI + +#define SMICONTROL_MASK 3 +#define SMICONTROL_DISABLE 0 +#define SMICONTROL_SMI 1 +#define SMICONTROL_NMI 2 +#define SMICONTROL_IRQ13 3 + +#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE + +#define GPIO_RSVD_ZONE0_S GPIO_81 +#define GPIO_RSVD_ZONE0_E GPIO_95 +#define GPIO_RSVD_ZONE1_S GPIO_120 +#define GPIO_RSVD_ZONE1_E GPIO_127 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef enum _GPIO_COUNT +{ + GPIO_00=0, + GPIO_01, + GPIO_02, + GPIO_03, + GPIO_04, + GPIO_05, + GPIO_06, + GPIO_07, + GPIO_08, + GPIO_09, + GPIO_10, + GPIO_11, + GPIO_12, + GPIO_13, + GPIO_14, + GPIO_15, + GPIO_16, + GPIO_17, + GPIO_18, + GPIO_19, + GPIO_20, + GPIO_21, + GPIO_22, + GPIO_23, + GPIO_24, + GPIO_25, + GPIO_26, + GPIO_27, + GPIO_28, + GPIO_29, + GPIO_30, + GPIO_31, + GPIO_32, + GPIO_33, + GPIO_34, + GPIO_35, + GPIO_36, + GPIO_37, + GPIO_38, + GPIO_39, + GPIO_40, + GPIO_41, + GPIO_42, + GPIO_43, + GPIO_44, + GPIO_45, + GPIO_46, + GPIO_47, + GPIO_48, + GPIO_49, + GPIO_50, + GPIO_51, + GPIO_52, + GPIO_53, + GPIO_54, + GPIO_55, + GPIO_56, + GPIO_57, + GPIO_58, + GPIO_59, + GPIO_60, + GPIO_61, + GPIO_62, + GPIO_63, + GPIO_64, + GPIO_65, + GPIO_66, + GPIO_67, + GPIO_68, + GPIO_69, + GPIO_70, + GPIO_71, + GPIO_72, + GPIO_73, + GPIO_74, + GPIO_75, + GPIO_76, + GPIO_77, + GPIO_78, + GPIO_79, + GPIO_80, + GPIO_81, + GPIO_82, + GPIO_83, + GPIO_84, + GPIO_85, + GPIO_86, + GPIO_87, + GPIO_88, + GPIO_89, + GPIO_90, + GPIO_91, + GPIO_92, + GPIO_93, + GPIO_94, + GPIO_95, + GPIO_96, + GPIO_97, + GPIO_98, + GPIO_99, + GPIO_100, + GPIO_101, + GPIO_102, + GPIO_103, + GPIO_104, + GPIO_105, + GPIO_106, + GPIO_107, + GPIO_108, + GPIO_109, + GPIO_110, + GPIO_111, + GPIO_112, + GPIO_113, + GPIO_114, + GPIO_115, + GPIO_116, + GPIO_117, + GPIO_118, + GPIO_119, + GPIO_120, + GPIO_121, + GPIO_122, + GPIO_123, + GPIO_124, + GPIO_125, + GPIO_126, + GPIO_127, + GPIO_128, + GPIO_129, + GPIO_130, + GPIO_131, + GPIO_132, + GPIO_133, + GPIO_134, + GPIO_135, + GPIO_136, + GPIO_137, + GPIO_138, + GPIO_139, + GPIO_140, + GPIO_141, + GPIO_142, + GPIO_143, + GPIO_144, + GPIO_145, + GPIO_146, + GPIO_147, + GPIO_148, + GPIO_149, + GPIO_150, + GPIO_151, + GPIO_152, + GPIO_153, + GPIO_154, + GPIO_155, + GPIO_156, + GPIO_157, + GPIO_158, + GPIO_159, + GPIO_160, + GPIO_161, + GPIO_162, + GPIO_163, + GPIO_164, + GPIO_165, + GPIO_166, + GPIO_167, + GPIO_168, + GPIO_169, + GPIO_170, + GPIO_171, + GPIO_172, + GPIO_173, + GPIO_174, + GPIO_175, + GPIO_176, + GPIO_177, + GPIO_178, + GPIO_179, + GPIO_180, + GPIO_181, + GPIO_182, + GPIO_183, + GPIO_184, + GPIO_185, + GPIO_186, + GPIO_187, + GPIO_188, + GPIO_189, + GPIO_190, + GPIO_191, + GPIO_192, + GPIO_193, + GPIO_194, + GPIO_195, + GPIO_196, + GPIO_197, + GPIO_198, + GPIO_199, + GPIO_200, + GPIO_201, + GPIO_202, + GPIO_203, + GPIO_204, + GPIO_205, + GPIO_206, + GPIO_207, + GPIO_208, + GPIO_209, + GPIO_210, + GPIO_211, + GPIO_212, + GPIO_213, + GPIO_214, + GPIO_215, + GPIO_216, + GPIO_217, + GPIO_218, + GPIO_219, + GPIO_220, + GPIO_221, + GPIO_222, + GPIO_223, + GPIO_224, + GPIO_225, + GPIO_226, + GPIO_227, + GPIO_228, + GPIO_229, + MAX_GPIO_NO +} GPIO_COUNT; + +typedef struct _GPIO_SETTINGS +{ + u8 select; + u8 type; + u8 value; + u8 NonGpioGevent; +} GPIO_SETTINGS; + +GPIO_SETTINGS gpio_table[]= +{ + {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT}, + {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT}, + {GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT}, + {GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT}, + {GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT}, + {GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT}, + {GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT}, + {GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT}, + {GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT}, + {GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT}, + {GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT}, + {GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT}, + {GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT}, + {GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT}, + {GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT}, + {GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT}, + {GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT}, + {GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT}, + {GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT}, + {GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT}, + {GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT}, + {GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT}, + {GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT}, + {GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT}, + {GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT}, + {GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT}, + {GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT}, + {GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT}, + {GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT}, + {GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT}, + {GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT}, + {GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT}, + {GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT}, + {GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT}, + {GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT}, + {GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT}, + {GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT}, + {GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT}, + {GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT}, + {GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT}, + {GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT}, + {GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT}, + {GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT}, + {GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT}, + {GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT}, + {GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT}, + {GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT}, + {GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT}, + {GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT}, + {GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT}, + {GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT}, + {GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT}, + {GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT}, + {GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT}, + {GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT}, + {GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT}, + {GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT}, + {GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT}, + {GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT}, + {GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT}, + {GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT}, + {GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT}, + {GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT}, + {GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT}, + {GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT}, + {GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT}, + {GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT}, + {GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT}, + {GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT}, + {GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT}, + {GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT}, + {GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT}, + {GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT}, + {GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT}, + {GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT}, + {GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT}, + {GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT}, + {GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT}, + {GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT}, + {GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT}, + {GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT}, + {GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT}, + {GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT}, + {GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT}, + {GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT}, + {GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT}, + {GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT}, + {GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT}, + {GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT}, + {GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT}, + {GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT}, + {GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT}, + {GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT}, + {GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT}, + {GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT}, + {GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT}, + {GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT}, + {GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT}, + {GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT}, + {GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT}, + {GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT}, + {GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT}, + {GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT}, + {GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT}, + {GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT}, + {GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT}, + {GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT}, + {GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT}, + {GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT}, + {GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT}, + {GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT}, + {GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT}, + {GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT}, + {GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT}, + {GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT}, + {GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT}, + {GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT}, + {GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT}, + {GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT}, + {GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT}, + {GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT}, + {GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT}, + {GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT}, + {GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT}, + {GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT}, + {GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT}, + {GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT}, + {GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT}, + {GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT}, + {GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT}, + {GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT}, + {GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT}, + {GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT}, + {GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT}, + {GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT}, + {GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT}, + {GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT}, + {GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT}, + {GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT}, + {GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT}, + {GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT}, + {GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT}, + {GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT}, + {GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT}, + {GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT}, + {GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT}, + {GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT}, + {GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT}, + {GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT}, + {GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT}, + {GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT}, + {GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT}, + {GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT}, + {GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT}, + {GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT}, + {GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT}, + {GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT}, + {GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT}, + {GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT}, + {GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT}, + {GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT}, + {GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT}, + {GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT}, + {GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT}, + {GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT}, + {GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT}, + {GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT}, + {GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT}, + {GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT}, + {GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT}, + {GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT}, + {GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT}, + {GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT}, + {GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT}, + {GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT}, + {GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT}, + {GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT}, + {GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT}, + {GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT}, + {GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT}, + {GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT}, + {GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT}, + {GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT}, + {GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT}, + {GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT}, + {GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT}, + {GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT}, + {GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT}, + {GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT}, + {GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT}, + {GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT}, + {GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT}, + {GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT}, + {GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT}, + {GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT}, + {GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT}, + {GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT}, + {GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT}, + {GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT}, + {GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT}, + {GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT}, + {GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT}, + {GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT}, + {GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT}, + {GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT}, + {GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT}, + {GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT}, + {GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT}, + {GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT}, + {GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT}, + {GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT}, + {GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT}, + {GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT}, + {GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT}, + {GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT}, + {GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT}, + {GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT}, + {GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT}, + {GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT}, + {GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT}, + {GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT}, + {GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT}, + {GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT}, + {GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT}, + {GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT}, + {GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT}, + {GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT}, + {GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT}, + {GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT}, + {GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT}, +}; + +typedef enum _GEVENT_COUNT +{ + GEVENT_00=0x60, + GEVENT_01, + GEVENT_02, + GEVENT_03, + GEVENT_04, + GEVENT_05, + GEVENT_06, + GEVENT_07, + GEVENT_08, + GEVENT_09, + GEVENT_10, + GEVENT_11, + GEVENT_12, + GEVENT_13, + GEVENT_14, + GEVENT_15, + GEVENT_16, + GEVENT_17, + GEVENT_18, + GEVENT_19, + GEVENT_20, + GEVENT_21, + GEVENT_22, + GEVENT_23 +} GEVENT_COUNT; + +typedef struct _GEVENT_SETTINGS +{ + u8 EventEnable; // 0: Disable, 1: Enable + u8 SciTrig; // 0: Falling Edge, 1: Rising Edge + u8 SciLevl; // 0: Edge trigger, 1: Level Trigger + u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI + u8 SciS0En; // 0: Disable, 1: Enable + u8 SciMap; // 0000b->1111b + u8 SmiTrig; // 0: Active Low, 1: Active High + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 +} GEVENT_SETTINGS; + +GEVENT_SETTINGS gevent_table[] = +{ + {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL}, + {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL}, + {GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL}, + {GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL}, + {GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL}, + {GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL}, + {GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL}, + {GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL}, + {GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL}, + {GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL}, + {GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL}, + {GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL}, + {GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL}, + {GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL}, + {GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL}, + {GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL}, + {GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL}, + {GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL}, + {GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL}, + {GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL}, + {GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL}, + {GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL}, + {GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL}, + {GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL}, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c new file mode 100644 index 0000000..afd8c67 --- /dev/null +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include + + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb700[2]; +extern unsigned long sbdn_sb700; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb700[0]; + pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c new file mode 100644 index 0000000..9d10390 --- /dev/null +++ b/src/mainboard/amd/dinar/mainboard.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define ONE_MB 0x100000 +//#define SMBUS_IO_BASE 0x6000 + +void set_pcie_reset(void *nbconfig); +void set_pcie_dereset(void *nbconfig); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void *nbconfig) +{ +} + +/** + * Mainboard specific RD890 CIMx callback + * Release Resets to PCIe Links + * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie + */ +void set_pcie_dereset(void *nbconfig) +{ + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; + + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } +} + +uint64_t uma_memory_base, uma_memory_size; + +/************************************************* + * enable the dedicated function in dinar board. + *************************************************/ +static void dinar_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeOR () */ + /* + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + */ + sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + uma_memory_size = 512 * ONE_MB; + } else if (sys_mem >= 1024 * ONE_MB) { + uma_memory_size = 256 * ONE_MB; + } else { + uma_memory_size = 64 * ONE_MB; + } + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ + uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ +#endif + +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME("AMD DINAR Mainboard") + .enable_dev = dinar_enable, +}; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c new file mode 100644 index 0000000..d988eb1 --- /dev/null +++ b/src/mainboard/amd/dinar/mptable.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_rd890[14]; +extern u8 bus_sb700[2]; +extern u32 bus_type[256]; +extern u32 sbdn_rd890; +extern u32 sbdn_sb700; + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicid_sb700; + u32 apicid_rd890; + device_t dev; + u32 dword; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + get_bus_conf(); + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. + dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + if (dev) { + /* Set sb700 IOAPIC ID */ + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb700, 0x20, dword); + +#ifdef UNUSED_CODE + u8 byte; + /* Initialize interrupt mapping */ + /* aza */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= 0; /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + /* SATA */ + dword = pci_read_config32(dev, 0xAC); + dword &= ~(7 << 26); + dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ + /* dword |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xAC, dword); +#endif + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + + /* Set RS5650 IOAPIC ID */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_rd890, 0x20, dword); + } + + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) + + /* SMBUS */ + //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x2, 0x10); + + /* USB */ + /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ + /* EHCI hard-wired to 02h, corresponding to using INTB# */ + /* USB1 */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ + PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ + PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ + + /* USB2 */ + PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ + PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ + PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ + + /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ + PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + + /* on board NIC & Slot PCIE. */ + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13); + */ + + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h new file mode 100644 index 0000000..8265f87 --- /dev/null +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c new file mode 100644 index 0000000..9518691 --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include +#include + +#ifndef __PRE_RAM__ +#include +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h new file mode 100644 index 0000000..a4f4e1a --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +#define RD890_IOAPIC_ADDR 0xC8000000 +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c new file mode 100644 index 0000000..4cc1efd --- /dev/null +++ b/src/mainboard/amd/dinar/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c new file mode 100644 index 0000000..39d8b45 --- /dev/null +++ b/src/mainboard/amd/dinar/romstage.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpu/x86/bist.h" +#include "superio/smsc/sch4037/sch4037_early_init.c" +#include "superio/smsc/sio1036/sio1036_early_init.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "pc80/i8254.c" +#include "pc80/i8259.c" +#include "nb_cimx.h" +#include "sb_cimx.h" +#include "Platform.h" +#include + +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +u32 agesawrapper_amdinitmmio (void); +u32 agesawrapper_amdinitreset (void); +u32 agesawrapper_amdinitearly (void); +u32 agesawrapper_amdinitenv (void); +u32 agesawrapper_amdinitlate (void); +u32 agesawrapper_amdinitpost (void); +u32 agesawrapper_amdinitmid (void); + + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + if (!cpu_init_detectedx && boot_cpu()) { + + post_code(0x30); + + sch4037_early_init (CONFIG_SIO_PORT); + + /* Detect SMSC SIO1036 LPC Debug Card status */ + if (detect_sio1036_chip(0x4E)) { + /* Found SMSC SIO1036 LPC Debug Card */ + sio1036_early_init(0x4E); + } + + post_code(0x31); + uart_init(); + console_init(); + + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + } + + post_code(0x32); + val = agesawrapper_amdinitmmio(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n"); + + /* Halt if there was a built in self test failure */ + post_code(0x33); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + if(boot_cpu()) { + post_code(0x34); + sb_Poweron_Init(); + } + + post_code(0x35); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); + + post_code(0x36); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + + post_code(0x37); + nb_Poweron_Init(); + post_code(0x38); + nb_Ht_Init(); + + + post_code(0x39); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x40); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x43); + print_debug("Disabling cache as ram "); + disable_cache_as_ram(); + print_debug("done\n"); + + post_code(0x44); + copy_and_run(0); + + post_code(0x45); // Should never see this post code. +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c new file mode 100644 index 0000000..36a453b --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h new file mode 100644 index 0000000..b405f0e --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_ From gerrit at coreboot.org Wed Feb 1 06:13:43 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:43 +0100 Subject: [coreboot] Patch set updated for coreboot: 69f2e61 SIO: Add smsc sio1036 superio References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/563 -gerrit commit 69f2e61ac499ca29e661dcbde4adf5ac6ec63fb7 Author: Kerry Sheh Date: Wed Feb 1 13:55:29 2012 +0800 SIO: Add smsc sio1036 superio Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1036/Makefile.inc | 21 ++++ src/superio/smsc/sio1036/chip.h | 34 +++++++ src/superio/smsc/sio1036/sio1036.h | 25 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 101 ++++++++++++++++++++ src/superio/smsc/sio1036/superio.c | 122 +++++++++++++++++++++++++ 7 files changed, 306 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index ddd5b96..d4f07ec 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,5 +40,7 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SIO1036 + bool config SUPERIO_SMSC_SCH4037 bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bfdc68e..d07afea 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,4 +29,5 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc new file mode 100644 index 0000000..4e48899 --- /dev/null +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c + diff --git a/src/superio/smsc/sio1036/chip.h b/src/superio/smsc/sio1036/chip.h new file mode 100644 index 0000000..abed430 --- /dev/null +++ b/src/superio/smsc/sio1036/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_SIO1036_CHIP_H +#define SUPERIO_SMSC_SIO1036_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_kbc1100_ops; + +struct superio_smsc_sio1036_config { + struct uart8250 com1; +}; + +#endif //SUPERIO_SMSC_SIO1036_CHIP_H + diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h new file mode 100644 index 0000000..cdd5a8b --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SIO1036_SP1 0 /* Com1 */ + +#define UART_POWER_DOWN (1 << 7) +#define LPT_POWER_DOWN (1 << 2) +#define IR_OUPUT_MUX (1 << 6) + diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c new file mode 100644 index 0000000..980e8c5 --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include "sio1036.h" + +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3F8 +#endif +static inline void sio1036_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static inline void sio1036_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static u8 detect_sio1036_chip(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + unsigned data; + sio1036_enter_conf_state (dev); + data = pnp_read_config (dev, 0x0D); + sio1036_exit_conf_state(dev); + /* detect smsc sio1036 chip */ + if (data == 0x82) { + /* Found SMSC SIO1036 chip */ + return 0; + } + else { + return -1; + }; +} + +static inline void sio1036_early_init(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + + if (detect_sio1036_chip(port) != 0) { + /* Not found SMSC SIO1036 */ + return; + } + sio1036_enter_conf_state (dev); + + /* Enable SMSC UART 0 */ + /* Valid configuration cycle */ + pnp_write_config (dev, 0x00, 0x28); + + /* PP power/mode/cr lock */ + pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN); + pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN); + + /*Auto power management*/ + pnp_write_config (dev, 0x07, 0x00 ); + + /*ECP FIFO threhod */ + pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX); + + /*GPIO direction register 2 */ + pnp_write_config (dev, 0x033, 0x00); + + /*UART Mode */ + pnp_write_config (dev, 0x0C, 0x02); + + /* GPIO polarity regisgter 2 */ + pnp_write_config (dev, 0x034, 0x00); + + /* Enable SMSC UART 0 */ + /*Set base io address */ + pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + + /* Set UART IRQ onto 0x04 */ + pnp_write_config (dev, 0x28, 0x04); + + sio1036_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c new file mode 100644 index 0000000..2522d92 --- /dev/null +++ b/src/superio/smsc/sio1036/superio.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC SIO1036 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sio1036.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sio1036_pnp_set_resources(device_t dev); +static void sio1036_pnp_enable_resources(device_t dev); +static void sio1036_pnp_enable(device_t dev); +static void sio1036_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sio1036_pnp_set_resources, + .enable_resources = sio1036_pnp_enable_resources, + .enable = sio1036_pnp_enable, + .init = sio1036_init, +}; + +static struct pnp_info pnp_dev_info[] = { + {}, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sio1036_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sio1036_init(device_t dev) +{ + struct superio_smsc_sio1036_config *conf = dev->chip_info; + struct resource *res0, *res1; + + + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + default: + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + From gerrit at coreboot.org Wed Feb 1 06:13:44 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:44 +0100 Subject: [coreboot] Patch set updated for coreboot: fbf9599 SIO: Add smsc/sch4037 superio support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit fbf959965fd4b88fe68017d931bec8fede1cf351 Author: Kerry Sheh Date: Wed Feb 1 13:55:28 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 +++ src/superio/smsc/sch4037/chip.h | 34 ++++ src/superio/smsc/sch4037/sch4037.h | 227 +++++++++++++++++++++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++ 7 files changed, 480 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..f429723 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + +/* BITS Define */ +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..1ff7aba --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /*Auto power management*/ + pnp_write_config (dev, 0x22, BIT3+BIT4+BIT5 ); + pnp_write_config (dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config (dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV (port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..af4040f --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} From gerrit at coreboot.org Wed Feb 1 06:13:45 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:45 +0100 Subject: [coreboot] Patch set updated for coreboot: 876830b SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/561 -gerrit commit 876830b1cb1ac3c89549318176e81b2dd2b86489 Author: Kerry Sheh Date: Wed Feb 1 13:55:26 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/southbridge/amd/Makefile.inc | 1 + src/southbridge/amd/cimx/Kconfig | 3 +- src/southbridge/amd/cimx/Makefile.inc | 3 +- src/southbridge/amd/cimx/sb700/Amd.h | 363 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/AmdSbLib.h | 181 +++++++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 63 +++++ src/southbridge/amd/cimx/sb700/Makefile.inc | 31 +++ src/southbridge/amd/cimx/sb700/Platform.h | 87 +++++++ src/southbridge/amd/cimx/sb700/bootblock.c | 97 +++++++ src/southbridge/amd/cimx/sb700/cbtypes.h | 53 ++++ src/southbridge/amd/cimx/sb700/chip.h | 42 +++ src/southbridge/amd/cimx/sb700/chip_name.c | 25 ++ src/southbridge/amd/cimx/sb700/early.c | 75 ++++++ src/southbridge/amd/cimx/sb700/late.c | 329 ++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.c | 195 ++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.h | 30 +++ src/southbridge/amd/cimx/sb700/sb_cimx.h | 49 ++++ src/southbridge/amd/cimx/sb700/smbus.c | 270 ++++++++++++++++++++ src/southbridge/amd/cimx/sb700/smbus.h | 82 ++++++ 19 files changed, 1977 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 406a0b3..54245f2 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -12,6 +12,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 8f12b90..f61b75a 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -21,5 +21,6 @@ config AMD_SB_CIMX bool default n +source src/southbridge/amd/cimx/sb700/Kconfig source src/southbridge/amd/cimx/sb800/Kconfig source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 421a11c..80c6378 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h new file mode 100644 index 0000000..fbd5531 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Amd.h @@ -0,0 +1,363 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +// AGESA Types and Definitions +#ifndef NULL +#define NULL 0 +#endif + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT + +#ifndef Int16FromChar +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#endif +#ifndef Int32FromChar +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +#endif + +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') + +typedef unsigned int AGESA_STATUS; + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h new file mode 100644 index 0000000..2812605 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef signed char *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + unsigned int AMDLogo; + unsigned long long CreatorID; + unsigned int Version1; + unsigned int Version2; + unsigned int Version3; + unsigned int ModuleInfoOffset; + unsigned int EntryPoint; + unsigned int ImageBase; + unsigned int RelocTableOffset; + unsigned int ImageSize; + unsigned short CheckSum; + unsigned char ImageType; + unsigned char Reserved2; +} CIMFILEHEADER; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS AmdSbDispatcher (IN void *pConfig); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig new file mode 100644 index 0000000..27338fc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_CIMX_SB700 + bool + select IOAPIC + select AMD_SB_CIMX + +if SOUTHBRIDGE_AMD_CIMX_SB700 +config SATA_CONTROLLER_MODE + hex + default 0x0 + help + 0x0 = Native IDE mode. + 0x1 = RAID mode. + 0x2 = AHCI mode. + 0x3 = Legacy IDE mode. + 0x4 = IDE->AHCI mode. + 0x5 = AHCI mode as 7804 ID (AMD driver). + 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). + +config PCIB_ENABLE + bool + default n + help + n = Disable PCI Bridge Device 14 Function 4. + y = Enable PCI Bridge Device 14 Function 4. + +config ACPI_SCI_IRQ + hex + default 0x9 + help + Set SCI IRQ to 9. +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/cimx/sb700/bootblock.c" + +config REDIRECT_SBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Southbridge CIMX Trace to serial console" + default n + help + This Option allows you to redirect the AMD Southbridge CIMX Trace + debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. +endif #SOUTHBRIDGE_AMD_CIMX_SB700 + diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..7929cf7 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# SB700 Platform Files + +romstage-y += early.c +romstage-y += smbus.c + +ramstage-y += late.c + +driver-y += smbus.c +driver-y += lpc.c + + diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h new file mode 100644 index 0000000..15e5b07 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_PLATFORM_H_ +#define _AMD_SB_CIMx_PLATFORM_H_ + +#pragma pack(push,1) + +#include "cbtypes.h" +#include +#include +#ifdef NULL +#undef NULL +#endif +#define NULL 0 + +typedef struct _EXT_PCI_ADDR{ + UINT32 Reg :16; + UINT32 Func:3; + UINT32 Dev :5; + UINT32 Bus :8; +}EXT_PCI_ADDR; + + +typedef union _PCI_ADDR{ + UINT32 ADDR; + EXT_PCI_ADDR Addr; +}PCI_ADDR; + + +#ifdef CIM_DEBUG + +#if CIM_DEBUG & 2 +void TraceDebug( UINT32 Level, CHAR8 *Format, ...); +#define TRACE(Arguments) TraceDebug Arguments +#else +#define TRACE(Arguments) +#endif + +#if CIM_DEBUG & 1 +void TraceCode ( UINT32 Level, UINT32 Code); +#define TRACECODE(Arguments) TraceCode Arguments +#else +#define TRACECODE(Arguments) +#endif +#else + #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL + #define TRACE(Arguments) printk Arguments + #else + #define TRACE(Arguments) do {} while(0) + #endif + #define TRACECODE(Arguments) +#endif + +#define FIXUP_PTR(ptr) ptr + +#pragma pack(pop) + +#include "OEM.h" +#include "Amd.h" +#include "ACPILIB.h" +#include "SBTYPE.h" +#include "sbAMDLIB.h" +#include "SBCMNLIB.h" +#include "SB700.h" +#include "SBDEF.h" + +#define DMSG_SB_TRACE 0x02 + +#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_ + diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c new file mode 100644 index 0000000..401c039 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include + + +#if CONFIG_CONSOLE_POST == 1 + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif // CONFIG_TTYS0_DIV + +#define UART_LCS CONFIG_TTYS0_LCS + +#endif // CONFIG_CONSOLE_POST == 1 + + +static void sb700_enable_rom(void) +{ + u32 word; + u32 dword; + device_t dev; + + dev = PCI_DEV(0, 0x14, 0x03); + /* SB700 LPC Bridge 0:20:3:44h. + * BIT6: Port Enable for serial port 0x3f8-0x3ff + * BIT29: Port Enable for KBC port 0x60 and 0x64 + * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 + */ + dword = pci_io_read_config32(dev, 0x44); + //dword |= (1<<6) | (1<<29) | (1<<30) ; + /*Turn on all of LPC IO Port decode enable */ + dword = 0xffffffff; + pci_io_write_config32(dev, 0x44, dword); + + /* SB700 LPC Bridge 0:20:3:48h. + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) + * BIT6: Port Enable for RTC IO 0x70-0x73 + * BIT21: Port Enable for Port 0x80 + */ + dword = pci_io_read_config32(dev, 0x48); + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + pci_io_write_config32(dev, 0x48, dword); + + /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Set the 4MB enable bits */ + word = pci_io_read_config16(dev, 0x6c); + word = 0xFFC0; + pci_io_write_config16(dev, 0x6c, word); +} + +static void bootblock_southbridge_init(void) +{ + /* Setup the rom access for 2M */ + sb700_enable_rom(); +} diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h new file mode 100644 index 0000000..d37e1e3 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/cbtypes.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include + +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN; +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +#endif diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h new file mode 100644 index 0000000..ef294f4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CIMX_SB700_CHIP_H_ +#define _CIMX_SB700_CHIP_H_ + +extern struct chip_operations southbridge_amd_cimx_sb700_ops; + +/* + * configuration set in mainboard/devicetree.cb + * boot_switch_sata_ide: + * 0 -set SATA as primary, PATA(IDE) as secondary. + * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, + * gpp_configuration - The configuration of General Purpose Port A/B/C/D + * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] + * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] + * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ +struct southbridge_amd_cimx_sb700_config +{ + u32 boot_switch_sata_ide : 1; + u8 gpp_configuration; +}; + +#endif /* _CIMX_SB700_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c new file mode 100644 index 0000000..13d2276 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("AMD South Bridge SB700") +}; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c new file mode 100644 index 0000000..bc3d944 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +//#include +#include +#include +#include /* inl, outl */ +#include /* device_t */ +#include "Platform.h" +#include "sb_cimx.h" +#include "sb700_cfg.h" /*sb700_cimx_config*/ +#include +#include +#include "smbus.h" + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus) +{ + device_t dev; + + printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - Start.\n"); + //dev = PCI_DEV(bus, 0x14, 0); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), + bus); + + printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - End.\n"); + return (dev >> 15) & 0x1f; +} +#endif + +/** + * @brief Enable A-Link Express Configuration DMA Access. + */ + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of sbPowerOnInit entry point. + */ +void sb_Poweron_Init(void) +{ + AMDSBCFG sb_early_cfg; + + printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() Start:\n", __func__); + /* Enable A-Link Base Address */ + //sb_enable_alink (); + + sb700_cimx_config(&sb_early_cfg); + sbPowerOnInit(&sb_early_cfg); + printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() End\n", __func__); +} + diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c new file mode 100644 index 0000000..8d13cd8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include /* device_t */ +#include /* device_operations */ +#include +#include +#include /* smbus_bus_operations */ +#include /* printk */ +#include "lpc.h" /* lpc_read_resources */ +#include "Platform.h" /* Platfrom Specific Definitions */ +#include "sb_cimx.h" +#include "sb700_cfg.h" /* sb700 Cimx configuration */ +#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ + + +/*implement in mainboard.c*/ +void set_pcie_reset(void); +void set_pcie_dereset(void); + +static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config +static AMDSBCFG *sb_config = &sb_late_cfg; + + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_config Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* config) +{ + u32 ret = 0; + + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n"); + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n"); + return ret; +} + + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static void lpc_enable_resources(device_t dev) +{ + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - Start.\n"); + pci_dev_enable_resources(dev); + lpc_enable_childrens_resources(dev); + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - End.\n"); +} + +static struct device_operations lpc_ops = { + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_LPC, +}; + + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390 +}; + +#if CONFIG_USBDEBUG +static void usb_set_resources(struct device *dev) +{ + struct resource *res; + u32 base; + u32 old_debug; + + printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - Start.\n"); + old_debug = get_ehci_debug(); + set_ehci_debug(0); + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x10); + set_ehci_debug(old_debug); + if (!res) + return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); + printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - End.\n"); +} +#endif + + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, +#if CONFIG_USBDEBUG + .set_resources = usb_set_resources, +#else + .set_resources = pci_dev_set_resources, +#endif + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +/* + * The pci id of usb ctrl 0 and 1 are the same. + */ +static const struct pci_driver usb_ohci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci3_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1, +}; + +static const struct pci_driver usb_ehci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci4_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */ +}; + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver azalia_driver __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_HDA, +}; + +#ifdef UNUSED_CODE +static struct device_operations gec_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; +#endif + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_PCI, +}; + + +static void sb700_enable(device_t dev) +{ + struct southbridge_amd_cimx_sb700_config *sb_chip = + (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info); + + printk(BIOS_DEBUG, "sb700_enable() "); + switch (dev->path.pci.devfn) { + case (0x11 << 3) | 0: /* 0:11.0 SATA */ + sb700_cimx_config(sb_config); + if (dev->enabled) { + sb_config->SataController = CIMX_OPTION_ENABLED; + if (1 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. + else if (0 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. + } else { + sb_config->SataController = CIMX_OPTION_DISABLED; + } + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + break; + + case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { +#if 1 + u32 ioapic_base; + printk(BIOS_DEBUG, "sm_init().\n"); + ioapic_base = IO_APIC_ADDR; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ +#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); +#elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); +#else +#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" +#endif +#endif + } + break; + + case (0x14 << 3) | 1: /* 0:14:1 IDE */ + break; + + case (0x14 << 3) | 2: /* 0:14:2 HDA */ + if (dev->enabled) { + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; + } + printk(BIOS_DEBUG, "hda enabled\n"); + } else { + sb_config->AzaliaController = AZALIA_DISABLE; + printk(BIOS_DEBUG, "hda disabled\n"); + } + break; + + + case (0x14 << 3) | 3: /* 0:14:3 LPC */ + break; + + case (0x14 << 3) | 4: /* 0:14:4 PCI */ + break; + + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + /* call CIMX entry after last device enable */ + sb_Before_Pci_Init(); + break; + + default: + break; + } +} + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("ATI SB700") + .enable_dev = sb700_enable, +}; + +/** + * @brief SB Cimx entry point sbBeforePciInit wrapper + */ +void sb_Before_Pci_Init(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbBeforePciInit(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} + +void sb_After_Pci_Init(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbAfterPciInit(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} + +void sb_Late_Post(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_LATE_POST_INIT; + //AmdSbDispatcher(sb_config); + sbLatePost(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c new file mode 100644 index 0000000..5d551cc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc.h" +#include +#include +#include /* printk */ +#include + +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xfc, i; + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} + +void lpc_read_resources(device_t dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - Start.\n"); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + + pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + compact_resources(dev); + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - End.\n"); +} + +void lpc_set_resources(struct device *dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - Start.\n"); + pci_dev_set_resources(dev); + + /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS); + pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - End.\n"); +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whos children's resources are to be enabled + * + */ +void lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); +/* + printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); +*/ + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + reg |= (1 << 29); + break; + case 0x3f8: /* COM1 */ + reg |= (1 << 6); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 7); + break; + case 0x378: /* Parallal 1 */ + reg |= (1 << 0); + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 26); + break; + case 0x220: /* Aduio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 18); + break; + case 0x400: + reg_x |= (1 << 16); + break; + case 0x480: + reg_x |= (1 << 17); + break; + case 0x500: + reg_x |= (1 << 18); + break; + case 0x580: + reg_x |= (1 << 19); + break; + case 0x4700: + reg_x |= (1 << 22); + break; + case 0xfd60: + reg_x |= (1 << 23); + break; + default: + if (var_num >= 3) + continue; /* only 3 var ; compact them ? */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + break; + case 1: + reg_x |= (1 << 24); + break; + case 2: + reg_x |= (1 << 25); + break; + } + reg_var[var_num++] = + base & 0xffff; + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 2: + pci_write_config16(dev, 0x90, reg_var[2]); + case 1: + pci_write_config16(dev, 0x66, reg_var[1]); + case 0: + //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata + break; + } + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - End.\n"); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h new file mode 100644 index 0000000..edb13f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_LPC_H_ +#define _SB700_LPC_H_ + + +#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ + +void lpc_read_resources(device_t dev); +void lpc_set_resources(device_t dev); +void lpc_enable_childrens_resources(device_t dev); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h new file mode 100644 index 0000000..84fe4d0 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_H_ +#define _CIMX_H_ + +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +#define REV_SB700_A11 0x11 +#define REV_SB700_A12 0x12 + + +/** + * AMD South Bridge CIMx entry point wrapper + */ +void sb_Poweron_Init(void); +void sb_Before_Pci_Init(void); +void sb_After_Pci_Init(void); +void sb_Mid_Post_Init(void); +void sb_Late_Post(void); + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c new file mode 100644 index 0000000..58dd012 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.c @@ -0,0 +1,270 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "smbus.h" +#include /* printk */ + +static inline void smbus_delay(void) +{ + outb(inb(0x80), 0x80); +} + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { /* ready now */ + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; /* mask off reserved bits */ + if (val & 0x1c) { + return -5; /* error */ + } + if (val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + return 0; + } + } while (--loops); + + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n"); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n"); + return byte; +} + +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n"); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n"); + return 0; +} + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n"); + return byte; +} + +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n"); + return 0; +} + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); +} + +/* space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n"); + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n"); +} + diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h new file mode 100644 index 0000000..10e0874 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_SMBUS_H_ +#define _SB700_SMBUS_H_ + +//#include +#include /* SMBUS0_BASE_ADDRESS */ +#ifndef SMBUS0_BASE_ADDRESS +#error SMBUS0_BASE_ADDRESS not define +#endif +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif //_SB700_SMBUS_H_ From gerrit at coreboot.org Wed Feb 1 06:13:46 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:46 +0100 Subject: [coreboot] Patch set updated for coreboot: 33b60dd SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/560 -gerrit commit 33b60ddb3d34150cd8d5a962758b02dcfd0e2127 Author: Kerry Sheh Date: Wed Feb 1 13:55:13 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code Support AMD SB700 and SP5100 chipsets. Change-Id: I0955abf7f48a79483f624b46a61b22711315f888 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/vendorcode/amd/cimx/Makefile.inc | 1 + src/vendorcode/amd/cimx/sb700/ACPILIB.c | 120 ++++ src/vendorcode/amd/cimx/sb700/ACPILIB.h | 61 ++ src/vendorcode/amd/cimx/sb700/AMDLIB.c | 434 ++++++++++++ src/vendorcode/amd/cimx/sb700/AMDSBLIB.c | 276 ++++++++ src/vendorcode/amd/cimx/sb700/AZALIA.c | 304 ++++++++ src/vendorcode/amd/cimx/sb700/DEBUG.c | 169 +++++ src/vendorcode/amd/cimx/sb700/DISPATCHER.c | 208 ++++++ src/vendorcode/amd/cimx/sb700/EC.c | 132 ++++ src/vendorcode/amd/cimx/sb700/FLASH.c | 58 ++ src/vendorcode/amd/cimx/sb700/LEGACY.c | 38 + src/vendorcode/amd/cimx/sb700/Makefile.inc | 77 ++ src/vendorcode/amd/cimx/sb700/OEM.h | 87 +++ src/vendorcode/amd/cimx/sb700/SATA.c | 453 ++++++++++++ src/vendorcode/amd/cimx/sb700/SB700.h | 1028 ++++++++++++++++++++++++++++ src/vendorcode/amd/cimx/sb700/SBCMN.c | 572 ++++++++++++++++ src/vendorcode/amd/cimx/sb700/SBCMNLIB.c | 108 +++ src/vendorcode/amd/cimx/sb700/SBCMNLIB.h | 89 +++ src/vendorcode/amd/cimx/sb700/SBDEF.h | 166 +++++ src/vendorcode/amd/cimx/sb700/SBMAIN.c | 289 ++++++++ src/vendorcode/amd/cimx/sb700/SBPOR.c | 441 ++++++++++++ src/vendorcode/amd/cimx/sb700/SBTYPE.h | 249 +++++++ src/vendorcode/amd/cimx/sb700/SMM.c | 91 +++ src/vendorcode/amd/cimx/sb700/USB.c | 187 +++++ src/vendorcode/amd/cimx/sb700/sbAMDLIB.h | 196 ++++++ 25 files changed, 5834 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc index 3622312..7051ea2 100644 --- a/src/vendorcode/amd/cimx/Makefile.inc +++ b/src/vendorcode/amd/cimx/Makefile.inc @@ -1,3 +1,4 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c new file mode 100644 index 0000000..807b166 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.c @@ -0,0 +1,120 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +/*++ + +Routine Description: + + Locate ACPI table + +Arguments: + + Signature - table signature + +Returns: + + pointer to ACPI table + +--*/ +void* ACPI_LocateTable( + UINT32 Signature +) +{ + UINT32 i; + UINT32* RsdPtr = (UINT32*)0xe0000; + UINT32* Rsdt = NULL; + DESCRIPTION_HEADER* CurrentTable; + do{ +// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){ + if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){ + Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress; + break; + } + RsdPtr+=4; + }while (RsdPtr <= (UINT32*)0xffff0); + if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){ + for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){ + CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4); + if (CurrentTable->Signature == Signature) return CurrentTable; + } + } + return NULL; +} + +/*++ + +Routine Description: + + Update table checksum + +Arguments: + + TablePtr - table pointer + +Returns: + + none + +--*/ +void ACPI_SetTableChecksum( + void* TablePtr +) +{ + UINT8 Checksum = 0; + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; + Checksum = ACPI_GetTableChecksum(TablePtr); + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum; +} + +/*++ + +Routine Description: + + Get table checksum + +Arguments: + + TablePtr - table pointer + +Returns: + + none + +--*/ +UINT8 ACPI_GetTableChecksum( + void* TablePtr +) +{ + return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length); +} + diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.h b/src/vendorcode/amd/cimx/sb700/ACPILIB.h new file mode 100644 index 0000000..5f2734f --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.h @@ -0,0 +1,61 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_ACPILIB_H_ +#define _AMD_ACPILIB_H_ + +typedef struct _RSDP{ + UINT64 Signature; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +}RSDP; + +typedef struct _DESCRIPTION_HEADER{ + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT8 OEMTableID[8]; + UINT32 OEMRevision; + UINT32 CreatorID; + UINT32 CreatorRevision; +}DESCRIPTION_HEADER; + +void* ACPI_LocateTable(UINT32 Signature); +void ACPI_SetTableChecksum(void* TablePtr); +UINT8 ACPI_GetTableChecksum(void* TablePtr); + +#endif //ifndef _AMD_ACPILIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/AMDLIB.c b/src/vendorcode/amd/cimx/sb700/AMDLIB.c new file mode 100644 index 0000000..b233259 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AMDLIB.c @@ -0,0 +1,434 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + + +#include "Platform.h" + +VOID +ReadIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *(UINT8*)Value = ReadIo8 (Address); + break; + case AccWidthUint16: + *(UINT16*)Value = ReadIo16 (Address); + break; + case AccWidthUint32: + *(UINT32*)Value = ReadIo32 (Address); + break; + default: + break; + } +} + +VOID +WriteIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + WriteIo8 (Address, *(UINT8*)Value); + break; + case AccWidthUint16: + WriteIo16 (Address, *(UINT16*)Value); + break; + case AccWidthUint32: + WriteIo32 (Address, *(UINT32*)Value); + break; + default: + break; + } +} + +VOID +RWIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadIO (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteIO (Address, OpFlag, &Result); +} + + +VOID +ReadPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +WritePCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +RWPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + Result = 0; + OpFlag = OpFlag & 0x7f; + ReadPCI (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WritePCI (Address, OpFlag, &Result); +} + +void +ReadIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +void* Value +) +{ + WritePCI(PciAddress,AccWidthUint32,&IndexAddress); + ReadPCI(PciAddress+4,AccWidthUint32,Value); +} + +void +WriteIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +UINT8 OpFlag, +void* Value +) +{ + + WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress); + WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value); +} + +void +RWIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +UINT8 OpFlag, +UINT32 Mask, +UINT32 Data +) +{ + UINT32 Result; + ReadIndexPCI32(PciAddress,IndexAddress,&Result); + Result = (Result & Mask)| Data; + WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result); + +} + +void +ReadMEM ( +UINT32 Address, +UINT8 OpFlag, +void* Value +) +{ + OpFlag = OpFlag & 0x7f; + switch (OpFlag){ + case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break; + case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break; + case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break; + } +} + +void +WriteMEM ( +UINT32 Address, +UINT8 OpFlag, +void* Value +) +{ + OpFlag = OpFlag & 0x7f; + switch (OpFlag){ + case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break; + case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break; + case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break; + } +} + +void +RWMEM ( +UINT32 Address, +UINT8 OpFlag, +UINT32 Mask, +UINT32 Data +) +{ + UINT32 Result; + ReadMEM(Address,OpFlag,&Result); + Result = (Result & Mask)| Data; + WriteMEM(Address,OpFlag,&Result); +} + + +void +RWMSR( +UINT32 Address, +UINT64 Mask, +UINT64 Value +) +{ + MsrWrite(Address,(MsrRead(Address)& Mask)|Value); +} + +UINT32 +IsFamily10() +{ + CPUID_DATA Cpuid; + CpuidRead(0x1,(CPUID_DATA *)&Cpuid); + + return Cpuid.REG_EAX & 0xff00000; +} + + +UINT8 GetNumberOfCpuCores(void) +{ + UINT8 Result=1; + Result=ReadNumberOfCpuCores(); + return Result; +} + + +void +Stall( +UINT32 uSec +) +{ + UINT16 timerAddr; + UINT32 startTime, elapsedTime; + ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr); + + if (timerAddr ==0){ + uSec = uSec/2; + while (uSec!=0){ + ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime)); + uSec--; + } + } + else{ + ReadIO(timerAddr, AccWidthUint32,&startTime); + while (1){ + ReadIO(timerAddr, AccWidthUint32,&elapsedTime); + if (elapsedTime < startTime) + elapsedTime = elapsedTime+0xFFFFFFFF-startTime; + else + elapsedTime = elapsedTime-startTime; + if ((elapsedTime*28/100)>uSec) + break; + } + } +} + + +void +Reset( +) +{ + RWIO(0xcf9,AccWidthUint8,0x0,0x06); +} + + +CIM_STATUS +RWSMBUSBlock( +UINT8 Controller, +UINT8 Address, +UINT8 Offset, +UINT8 BufferSize, +UINT8* BufferPrt +) +{ + UINT16 SmbusPort; + UINT8 i; + UINT8 Status; + ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort); + SmbusPort &= 0xfffe; + RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff); + RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address); + RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset); + RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14); + RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize); + if(!(Address & 0x1)){ + for (i = 0 ;i < BufferSize;i++){ + WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); + } + } + RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54); + do{ + ReadIO(SmbusPort + 0,AccWidthUint8,&Status); + if (Status & 0x1C) return CIM_ERROR; + if (Status & 0x02) break; + }while(!(Status & 0x1)); + + do{ + ReadIO(SmbusPort + 0,AccWidthUint8,&Status); + }while(Status & 0x1); + + if(Address & 0x1){ + for (i = 0 ;i < BufferSize;i++){ + ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); + } + } + return CIM_SUCCESS; +} + + + +void outPort80(UINT32 pcode) +{ + WriteIO(0x80, AccWidthUint8, &pcode); + return; +} + + +UINT8 +GetByteSum( + void* pData, + UINT32 Length +) +{ + UINT32 i; + UINT8 Checksum = 0; + for (i = 0;i < Length;i++){ + Checksum += *((UINT8*)pData+i); + } + return Checksum; +} + + +UINT32 +readAlink( + UINT32 Index +){ + UINT32 Data; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index=0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + return Data; +} + + +void +writeAlink( + UINT32 Index, + UINT32 Data +){ + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index=0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + +} + + +/** + * + * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server) + * + * A SP5100 is determined when both following two items are true: + * 1) Revision >= A14; + * 2) A server north bridge chipset is detected; + * + * A list of server north bridge chipset: + * + * Family DeviceID + * ---------------------- + * SR5690 0x5A10 + * SR5670 0x5A12 + * SR5650 0x5A13 + * + */ +UINT8 +IsServer (void){ + UINT16 DevID; + + if (getRevisionID () < SB700_A14) { + return 0; + } + ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID); + return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0; +} + +/** + * + * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge. + * + */ +UINT8 +IsLs2Mode (void) +{ + UINT32 HT3LinkTraining0; + + ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0); + return ( HT3LinkTraining0 & 0x100 )? 1: 0; +} diff --git a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c new file mode 100644 index 0000000..bf4f06a --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c @@ -0,0 +1,276 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +void +ReadPMIO ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 + } +} + + +void +WritePMIO ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 + } +} + + +void +RWPMIO ( +UINT8 Address, +UINT8 OpFlag, +UINT32 AndMask, +UINT32 OrMask +) +{ + UINT32 Result; + + OpFlag = OpFlag & 0x7f; + ReadPMIO(Address,OpFlag,&Result); + Result = (Result & AndMask)| OrMask; + WritePMIO(Address,OpFlag,&Result); +} + + +void +ReadPMIO2 ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 + } +} + + +void +WritePMIO2 ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 + } +} + + +void +RWPMIO2 ( +UINT8 Address, +UINT8 OpFlag, +UINT32 AndMask, +UINT32 OrMask +) +{ + UINT32 Result; + + OpFlag = OpFlag & 0x7f; + ReadPMIO2(Address,OpFlag,&Result); + Result = (Result & AndMask)| OrMask; + WritePMIO2(Address,OpFlag,&Result); +} + + +void +EnterEcConfig() +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); +} + +void +ExitEcConfig() +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); +} + + +void +ReadEC8 ( +UINT8 Address, +UINT8* Value +) +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 +} + + +void +WriteEC8 ( +UINT8 Address, +UINT8* Value +) +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 +} + + +void +RWEC8 ( +UINT8 Address, +UINT8 AndMask, +UINT8 OrMask +) +{ + UINT8 Result; + ReadEC8(Address,&Result); + Result = (Result & AndMask)| OrMask; + WriteEC8(Address, &Result); +} + + +void +programPciByteTable ( +REG8MASK* pPciByteTable, +UINT16 dwTableSize +) +{ + UINT8 i, dbBusNo, dbDevFnNo; + UINT32 ddBDFR; + + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + for (i = 1; i < dwTableSize; i++){ + if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){ + pPciByteTable++; + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + } + else{ + ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; + TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask)); + RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); + pPciByteTable++; + } + } +} + + +void +programPmioByteTable ( +REG8MASK* pPmioByteTable, +UINT16 dwTableSize +) +{ + UINT8 i; + for (i = 0; i < dwTableSize; i++){ + TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask)); + RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask); + pPmioByteTable++; + } +} + + +UINT8 +getClockMode ( +void +) +{ + UINT8 dbTemp=0; + + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp); + return(dbTemp&BIT4); +} + + +UINT16 +readStrapStatus ( +void +) +{ + UINT16 dwTemp=0; + + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp); + return(dwTemp); +} diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c new file mode 100644 index 0000000..cc72858 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AZALIA.c @@ -0,0 +1,304 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + + +#include "Platform.h" + +void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum); +void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0); + +//Pin Config for ALC880, ALC882 and ALC883: +CODECENTRY AzaliaCodecAlc882Table[] = { + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x01813080}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01441150}, + {0x1f, 0x01C46160}, + {0xff, 0xffffffff} +}; + + +//Pin Config for ALC262 +CODECENTRY AzaliaCodecAlc262Table[] = { + {0x14, 0x01014010}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, +// {0x17, 0x01012014}, + {0x18, 0x01A19830}, + {0x19, 0x02A19C40}, + {0x1a, 0x01813031}, + {0x1b, 0x02014C20}, + {0x1c, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x0144111E}, + {0x1f, 0x01C46150}, + {0xff, 0xffffffff} +}; + +//Pin Config for ALC0861: +CODECENTRY AzaliaCodecAlc861Table[] = { + {0x01, 0x8086C601}, + {0x0B, 0x01014110}, + {0x0C, 0x01813140}, + {0x0D, 0x01A19941}, + {0x0E, 0x411111F0}, + {0x0F, 0x02214420}, + {0x10, 0x02A1994E}, + {0x11, 0x99330142}, + {0x12, 0x01451130}, + {0x1F, 0x411111F0}, + {0x20, 0x411111F0}, + {0x23, 0x411111F0}, + {0xff, 0xffffffff} +}; + +//Pin Config for ADI1984: +CODECENTRY AzaliaCodecAd1984Table[] = { + {0x11, 0x0221401F}, + {0x12, 0x90170110}, + {0x13, 0x511301F0}, + {0x14, 0x02A15020}, + {0x15, 0x50A301F0}, + {0x16, 0x593301F0}, + {0x17, 0x55A601F0}, + {0x18, 0x55A601F0}, + {0x1A, 0x91F311F0}, + {0x1B, 0x014511A0}, + {0x1C, 0x599301F0}, + {0xff, 0xffffffff} +}; + + +CODECENTRY FrontPanelAzaliaCodecTableList[] = { + {0x19, 0x02A19040}, + {0x1b, 0x02214020}, + {0xff, 0xffffffff} +}; + + +CODECTBLLIST azaliaCodecTableList[] = { + {0x010ec0880, &AzaliaCodecAlc882Table[0]}, + {0x010ec0882, &AzaliaCodecAlc882Table[0]}, + {0x010ec0883, &AzaliaCodecAlc882Table[0]}, + {0x010ec0885, &AzaliaCodecAlc882Table[0]}, + {0x010ec0262, &AzaliaCodecAlc262Table[0]}, + {0x010ec0861, &AzaliaCodecAlc861Table[0]}, + {0x011d41984, &AzaliaCodecAd1984Table[0]}, + {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF} +}; + + +/*------------------------------------------------------------------------------- +; Procedure: azaliaInitAfterPciEnum +; +; Description: This routine detects Azalia and, if present, initializes Azalia +; This routine is called from atiSbAfterPciInit +; +; +; Exit: None +; +; Modified: None +; +;----------------------------------------------------------------------------- +*/ +void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){ + UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0; + UINT16 dwTempVariable = 0; + UINT32 ddBAR0, ddTempVariable = 0; + + if (pConfig->AzaliaController == 1) return; + + if (pConfig->AzaliaController != 1){ + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1); + ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); + + if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s. + if (ddBAR0 != 0xFFFFFFFF){ + ddBAR0 &= ~(0x03FFF); + dbEnableAzalia = 1; + TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n")); + } + } + } + + if (dbEnableAzalia){ //if Azalia is enabled + //Get SDIN Configuration + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable); + ddTempVariable |= (pConfig->AzaliaSdin3 << 6); + ddTempVariable |= (pConfig->AzaliaSdin2 << 4); + ddTempVariable |= (pConfig->AzaliaSdin1 << 2); + ddTempVariable |= pConfig->AzaliaSdin0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF)); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); + + i=11; + do{ + ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable |= BIT0; + WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + Stall(1000); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + i--; + } while ( (!(dbTempVariable & BIT0)) && (i > 0) ); + + if (i==0){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n")); + return; + } + + Stall(1000); + ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); + if (dwTempVariable & 0x0F){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n")); + //atleast one azalia codec found + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting); + do{ + if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) + configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum); + dbPinRouting >>= 2; + dbChannelNum++; + } while (dbChannelNum != 4); + } + else{ + TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n")); + //No Azalia codec found + if (pConfig->AzaliaController != 2) + dbEnableAzalia = 0; //set flag to disable Azalia + } + } + + if (dbEnableAzalia){ + //redo clear reset + do{ + dwTempVariable = 0; + WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable &= ~(UINT8)(BIT0); + WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + } while (dbTempVariable & BIT0); + + if (pConfig->AzaliaSnoop == 1) + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + } + else{ + //disable Azalia controller + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); + } +} + + +void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){ + UINT32 ddTempVariable, ddChannelNum; + CODECTBLLIST* ptempAzaliaOemCodecTablePtr; + CODECENTRY* tempAzaliaCodecEntryPtr; + + if ((pConfig->AzaliaPinCfg) != 1) + return; + + ddChannelNum = dbChannelNum << 28; + ddTempVariable = 0xF0000; + ddTempVariable |= ddChannelNum; + WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); + Stall(60); + ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); + + if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]); + else + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr; + + TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr)); + + while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ + if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable) + break; + else + ++ptempAzaliaOemCodecTablePtr; + } + + if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n")); + tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; + TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr)); + + if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr); + + configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + if (pConfig->AzaliaFrontPanel != 1){ + if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){ + if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF)) + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]); + else + tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr; + configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + } + } + } +} + + +void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){ + UINT8 dbtemp1,dbtemp2, i; + UINT32 ddtemp=0,ddtemp2=0; + + while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){ + dbtemp1=0x20; + if ((tempAzaliaCodecEntryPtr->Nid) == 0x1) + dbtemp1=0x24; + ddtemp = tempAzaliaCodecEntryPtr->Nid; + ddtemp &= 0xff; + ddtemp <<= 20; + ddtemp |= ddChannelNum; + ddtemp |= (0x700 << 8); + for(i=4; i>0; i--){ + do{ + ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); + } while (ddtemp2 & BIT0); + dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff; + ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2; + WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); + Stall(60); + } + ++tempAzaliaCodecEntryPtr; + } +} + diff --git a/src/vendorcode/amd/cimx/sb700/DEBUG.c b/src/vendorcode/amd/cimx/sb700/DEBUG.c new file mode 100644 index 0000000..f40682e --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/DEBUG.c @@ -0,0 +1,169 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#define COM_BASE_ADDRESS 0x3f8 +#define DIVISOR 115200 +#define LF 0x0a +#define CR 0x0d + + +#ifdef CIM_DEBUG + #ifndef CIM_DEBUG_LEVEL + #define CIM_DEBUG_LEVEL 0xf +#endif + +void +TraceCode( UINT32 Level, UINT32 Code){ + + if (!(Level & CIM_DEBUG_LEVEL)){ + return; + } +#if CIM_DEBUG & 1 + if (Code != 0xFF){ + WriteIO(0x80,AccWidthUint8,&Code); + } +#endif + +} + + +void +TraceDebug( UINT32 Level, CHAR8 *Format, ...){ + CHAR8 temp[16]; + va_list ArgList; + + if (!(Level & CIM_DEBUG_LEVEL)){ + return; + } + +#if CIM_DEBUG & 2 + ArgList = va_start(ArgList,Format); + Format= (CHAR8*) FIXUP_PTR(Format); + while (1){ + if (*Format == 0) break; + if (*Format == '%'){ + int Radix = 0; + if(*(Format+1)=='s'||*(Format+1)=='S'){ + SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*))); + Format+=2; + continue; + } + + if(*(Format+1)=='d'||*(Format+1)=='D'){ + Radix = 10; + } + if(*(Format+1)=='x'||*(Format+1)=='X'){ + Radix = 16; + } + if (Radix){ + ItoA(va_arg(ArgList,int),Radix,temp); + SendStringPort(temp); + Format+=2; + continue; + } + } + SendBytePort(*Format); + if(*(Format)==0x0a) SendBytePort(0x0d); + Format++; + } + va_end(ArgList); +#endif +} + + +void +ItoA( UINT32 Value, int Radix, char* pstr) +{ + char* tsptr = pstr; + char* rsptr = pstr; + char ch1,ch2; + unsigned int Reminder; +//Create String + do{ + Reminder = Value%Radix; + Value = Value/Radix; + if (Reminder<0xa) *tsptr=Reminder+'0'; + else *tsptr=Reminder-0xa+'a'; + tsptr++; + } while(Value); +//Reverse String + *tsptr = 0; + tsptr--; + while(tsptr>rsptr){ + ch1 = *tsptr; + ch2 = *rsptr; + *rsptr = ch1; + *tsptr = ch2; + tsptr--; + rsptr++; + } +} + +void +InitSerialOut(){ + UINT8 Data; + UINT16 Divisor; + Data = 0x87; + WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); + Divisor = 115200 / DIVISOR; + Data = Divisor & 0xFF; + WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); + Data = Divisor >> 8; + WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data); + Data = 0x07; + WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); +} + + +void +SendStringPort(char* pstr){ + + while (*pstr!=0){ + SendBytePort(*pstr); + pstr++; + } +} + +void +SendBytePort(UINT8 Data) +{ + int Count = 80; + UINT8 Status; + do { + ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status); + if(Status == 0xff) break; + // Loop port is ready + } while ( (Status & 0x20) == 0 && (--Count) != 0); + WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); +} +#endif diff --git a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c new file mode 100644 index 0000000..ae5f9b8 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c @@ -0,0 +1,208 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +void DispatcherEntry(void *pConfig){ + +#ifdef B1_IMAGE + void *pB2ImagePtr = NULL; + CIM_IMAGE_ENTRY pB2ImageEntry; +#endif + +//#if CIM_DEBUG +// InitSerialOut(); +//#endif + + TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n")); + +#ifdef B1_IMAGE + if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){ + if (((STDCFG*)pConfig)->pB2ImageBase) + pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase); + if (pB2ImagePtr == NULL) + pB2ImagePtr = LocateImage('007S'); + if (pB2ImagePtr!=NULL){ + TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n")); + ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr; + pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr); + (*pB2ImageEntry)(pConfig); + return; + } + } +#endif + saveConfigPointer(pConfig); + + if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT) + sbPowerOnInit((AMDSBCFG*)pConfig); + +#ifndef B1_IMAGE + if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT) + sbBeforePciInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT) + sbAfterPciInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT) + sbLatePost((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT) + sbBeforePciRestoreInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT) + sbAfterPciRestoreInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE) + { + // sbSmmService((AMDSBCFG*)pConfig); + } + if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION) + sbSmmAcpiOn((AMDSBCFG*)pConfig); +#endif + TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n")); +} + + +void* LocateImage(UINT32 Signature){ + void *Result; + UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1)); + while ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){ + Result = CheckImage(Signature,(void*)ImagePtr); + if (Result != NULL) + return Result; + ImagePtr -= IMAGE_ALIGN; + } + return NULL; +} + + +void* CheckImage(UINT32 Signature, void* ImagePtr){ + UINT8 *TempImagePtr; + UINT8 Sum = 0; + UINT32 i; +// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){ + if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){ + //GetImage Image size + TempImagePtr = (UINT8*)ImagePtr; + for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){ + Sum += *TempImagePtr; + TempImagePtr++; + } + if (Sum == 0) + return ImagePtr; + } + return NULL; +} + + +UINT32 GetPciebase(){ + AMDSBCFG* Result; + Result = getConfigPointer(); + return Result->StdHeader.pPcieBase; +} + + +void saveConfigPointer(AMDSBCFG* pConfig){ + UINT8 dbReg, i; + UINT32 ddValue; + + ddValue = ((UINT32) pConfig); + dbReg = SB_ECMOS_REG08; + + for (i=0; i<=3; i++){ + WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); + WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue); + ddValue >>= 8; + dbReg++; + } +} + + +AMDSBCFG* getConfigPointer(){ + UINT8 dbReg, dbValue, i; + UINT32 ddValue=0; + + dbReg = SB_ECMOS_REG08; + for (i=0; i<=3; i++){ + WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); + ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue); + ddValue |= (dbValue<<(i*8)); + dbReg++; + } + return( (AMDSBCFG*) ddValue); +} + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS +AmdSbDispatcher ( + IN VOID *pConfig + ) +{ + AGESA_STATUS Status = AGESA_SUCCESS; + + saveConfigPointer (pConfig); + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { + sbPowerOnInit ((AMDSBCFG*) pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { + sbBeforePciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { + sbAfterPciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { + sbLatePost ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { + sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { + sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { + sbSmmService ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { + sbSmmAcpiOn ((AMDSBCFG*)pConfig); + } + + return Status; +} diff --git a/src/vendorcode/amd/cimx/sb700/EC.c b/src/vendorcode/amd/cimx/sb700/EC.c new file mode 100644 index 0000000..3ad15e1 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/EC.c @@ -0,0 +1,132 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#ifndef NO_EC_SUPPORT + +REG8MASK sb710PorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. + {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D}, + {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 }, + {SB_SMBUS_REGE1, 0xFF, BIT1}, + {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2}, + {0xFF, 0xFF, 0xFF}, +}; + +REG8MASK sb710PorPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REGD7, 0xFF, BIT5}, + {SB_PMIO_REGBB, 0xFF, BIT5}, +}; + + +void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){ + UINT8 dbVar0, i=0; + + if (!(isEcPresent())) + return; //return if EC is not enabled + + for(i=0;i<0xFF;i++){ + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0); + if ( dbVar0 & BIT7 ) break; //break if EC is ready + Stall(500); //wait for EC to become ready + } + + if (getRevisionID() >= SB700_A14){ + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) ); + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) ); + } + + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC + + //Enable config mode + EnterEcConfig(); + + //Do settings for mailbox - logical device 0x09 + RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox) + RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port + RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port + RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 + + if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){ + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3); + //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC + RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0); + //Disable LPC Decoding of port 60/64 + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0); + //Enable logical device 0x07 (Keyboard controller) + RWEC8(0x07, 0x00, 0x07); + RWEC8(0x30, 0x00, 0x01); + } + + if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){ + //Logical device 0x08 + RWEC8(0x07, 0x00, 0x08); + RWEC8(0x60, 0x00, 0x00); + RWEC8(0x61, 0x00, 0x62); + RWEC8(0x30, 0x00, 0x01); //;Enable Device 8 + } + //Logical device 0x05 + RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8); + RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF)); + RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h + RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller + + RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS + ExitEcConfig(); +} + + +void ecInitBeforePciEnum(AMDSBCFG* pConfig){ + if (!(isEcPresent())) + return; //return if EC is not enabled +} + + +void ecInitLatePost(AMDSBCFG* pConfig){ + if (!(isEcPresent()) ) + return; //return if EC is not enabled + //Enable config mode + EnterEcConfig(); //Enable config mode + //for future use + ExitEcConfig(); +} + +#endif diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c new file mode 100644 index 0000000..0d84245 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/FLASH.c @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +void fcInitBeforePciEnum(AMDSBCFG* pConfig){ + + TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n")); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00); + + //Enable IDE and disable flash + //Enable IDE and disable flash + RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST + if (pConfig->IdeController){ + //Disabling IDE controller + RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + } + else{ + //Enable IDE controller + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); + } + + //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled + RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2); + //Slowdown the clock to FC if FC is not enabled, this is a power savings feature + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4); + RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0); +} diff --git a/src/vendorcode/amd/cimx/sb700/LEGACY.c b/src/vendorcode/amd/cimx/sb700/LEGACY.c new file mode 100644 index 0000000..c904d59 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/LEGACY.c @@ -0,0 +1,38 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +UINT32 GetFixUp(){ + STDCFG* Result; + Result = (STDCFG*) getConfigPointer(); + return Result->pImageBase; +} diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..8954133 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,77 @@ +#***************************************************************************** +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +# CIMX Root directory +CIMX_ROOT = $(src)/vendorcode/amd/cimx + +SB_CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) +SB_CIMX_INC += -I$(src)/southbridge/amd/cimx/sb700 +SB_CIMX_INC += -I$(CIMX_ROOT)/sb700 + +romstage-y += ACPILIB.c +romstage-y += AMDLIB.c +romstage-y += AMDSBLIB.c +romstage-y += AZALIA.c +romstage-y += DEBUG.c +romstage-y += DISPATCHER.c +romstage-y += EC.c +romstage-y += FLASH.c +romstage-y += SATA.c +romstage-y += SBCMN.c +romstage-y += SBCMNLIB.c +romstage-y += SBMAIN.c +romstage-y += SBPOR.c +romstage-y += SMM.c +romstage-y += USB.c + +ramstage-y += ACPILIB.c +ramstage-y += AMDLIB.c +ramstage-y += AMDSBLIB.c +ramstage-y += AZALIA.c +ramstage-y += DEBUG.c +ramstage-y += DISPATCHER.c +ramstage-y += EC.c +ramstage-y += FLASH.c +ramstage-y += SATA.c +ramstage-y += SBCMN.c +ramstage-y += SBCMNLIB.c +ramstage-y += SBMAIN.c +ramstage-y += SBPOR.c +ramstage-y += SMM.c +ramstage-y += USB.c +ramstage-y += LEGACY.c + +SB_CIMX_CFLAGS = +export CIMX_ROOT +export SB_CIMX_INC +export SB_CIMX_CFLAGS +CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC) + +####################################################################### + diff --git a/src/vendorcode/amd/cimx/sb700/OEM.h b/src/vendorcode/amd/cimx/sb700/OEM.h new file mode 100644 index 0000000..74604c0 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/OEM.h @@ -0,0 +1,87 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define BIOS_SIZE 0x04 //04 - 1MB +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 +#else + #define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c new file mode 100644 index 0000000..09d4923 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SATA.c @@ -0,0 +1,453 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +//Table for class code of SATA Controller in different modes +UINT32 sataIfCodeTable[] = { + 0x01018f00, //sata class ID of IDE + 0x01040000, //sata class ID of RAID + 0x01060100, //sata class ID of AHCI + 0x01018a00, //sata class ID of Legacy IDE + 0x01018f00, //sata class ID of IDE to AHCI mode + 0x01060100, //sata class ID of AMD-AHCI mode + 0x01018f00 //sata class ID of IDE to AMD-AHCI mode +}; + +//Table for device id of SATA Controller in different modes +UINT16 sataDeviceIDTable[] = { + 0x4390, //sata device ID of IDE + 0x4392, //sata device ID of RAID + 0x4391, //sata class ID of AHCI + 0x4390, //sata device ID of Legacy IDE + 0x4390, //sata device ID of IDE->AHCI mode + 0x4394, //sata device ID for AMD-AHCI mode + 0x4390 //sata device ID of IDE->AMDAHCI mode +}; + + +void sataInitBeforePciEnum(AMDSBCFG* pConfig){ + UINT32 ddValue, *tempptr; + UINT16 *pDeviceIdptr, dwDeviceId; + UINT8 dbValue, dbOrMask, dbAndMask; + + + dbAndMask=0; + dbOrMask=0; + // Enable/Disable Combined mode & do primary/secondary selections, enable/disable + if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3 + if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4 + if (pConfig->SataSmbus == 0) dbOrMask = BIT1; + + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask); + + if (pConfig->SataController == 0){ + // SATA Controller Disabled & set Power Saving mode to disabled + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1); + return; + } + + restrictSataCapabilities(pConfig); + + // Get the appropriate class code from the table and write it to PCI register 08h-0Bh + // Set the appropriate SATA class based on the input parameters + dbValue=pConfig->SataClass; + tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); + ddValue=tempptr[dbValue]; + + // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0 + // BIT4:disable fast boot + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0); + + // Write the class code to SATA PCI register 08h-0Bh + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + + if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE + //Set PATA controller to native mode + RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); + + //Change the appropriate device id + if (pConfig->SataClass == AMD_AHCI_MODE) { + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + } + pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); + if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){ + //if not (SB750 & RAID mode), then program the device id + dwDeviceId=pDeviceIdptr[dbValue]; + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); + } + + if (pConfig->AcpiS1Supported) + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability + else + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability + + if (getRevisionID() >= SB700_A13){ + //Enable test/enhancement mode for A13 + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00); + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80); + } + + if (getRevisionID() >= SB700_A14){ + //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6); + } + + // Disable write access to PCI header + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + + // RPR 6.5 SATA PHY Programming Sequence + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + + CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig); +} + +void sataInitAfterPciEnum(AMDSBCFG* pConfig){ + UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0; + UINT8 dbVar, dbPortNum; + + if (pConfig->SataController == 0) return; //return if SATA controller is disabled. + + //Enable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + //Disable AHCI enhancement function (RPR 7.2) + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + + restrictSataCapabilities(pConfig); + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + + if ( (ddBar5 == 0) || (ddBar5 == -1) ) { + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) + ddBar5 = 0xFEC01000; + else + ddBar5=pConfig->TempMMIO; + + WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + } + + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable + + ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0 + if (!pConfig->SataPortMultCap) + ddAndMask |= BIT12; + if (!pConfig->SataAggrLinkPmCap) + ddAndMask |= BIT11; + if (pConfig->SataSscPscCap) + ddOrMask |= BIT1; + + RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); + + + //Clear HPCP and ESP by default + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0); + + if (pConfig->SataHpcpButNonESP !=0) { + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP); + } + + // SATA ESP port setting + // These config bits are set for SATA driver to identify which ports are external SATA ports and need to + // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will + // not enable power management(HIPM & DIPM) for these ports. + if (pConfig->SataEspPort !=0) { + RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20); + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12)); + } + + if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) ) + RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages + + if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){ + RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0); + RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); + } + + for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ + if (pConfig->SataPortMode & (1 << dbPortNum)){ + //downgrade to GEN1 + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + Stall(1000); + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + } + } + + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. + if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) ) + sataDriveDetection(pConfig, ddBar5); + + if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) ) + sataPhyWorkaround(pConfig, ddBar5); + + // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly. + // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled. + if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) + RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) ); + + WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + + //Disable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); +} + + +void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){ + UINT32 ddVar0; + UINT8 dbPortNum, dbVar0; + UINT16 dwIoBase, dwVar0; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n")); + TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5)); + + if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){ + for (dbPortNum=0;dbPortNum<4;dbPortNum++){ + ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); + if ( ( ddVar0 & 0x0F ) == 0x03){ + if ( dbPortNum & BIT0) + //this port belongs to secondary channel + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); + else + //this port belongs to primary channel + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); + + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + if (pConfig->SataClass == LEGACY_IDE_MODE) + dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) ); + + if ( dbPortNum & BIT1) + //this port is slave + dbVar0=0xB0; + else + //this port is master + dbVar0=0xA0; + dwIoBase &= 0xFFF8; + WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0); + + //Wait in loop for 30s for the drive to become ready + for (dwVar0=0;dwVar0<3000;dwVar0++){ + ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0x88) == 0) + break; + Stall(10000); + } + } //end of if ( ( ddVar0 & 0x0F ) == 0x03) + } //for (dbPortNum=0;dbPortNum<4;dbPortNum++) + } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ) +} + + +//This patch is to workaround the SATA PHY logic hardware issue in the SB700. +//Internally this workaround is called as 7NewA +void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){ + + UINT8 dbPortNum, dbVar0; + + if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){ + for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ + ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0xF0) == 0x10){ + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum)); + } + + } + } + + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY + Stall(2000);// Wait for 2ms + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b + Stall(20000);// Wait 20ms + forceOOB(ddBar5);// Force OOB + + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00); +} + + +void forceOOB(UINT32 ddBar5){ + UINT8 dbPortNum; + for (dbPortNum=0;dbPortNum<=5;dbPortNum++) + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + Stall(2000); + for (dbPortNum=0;dbPortNum<=5;dbPortNum++) + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + Stall(2000);// Wait for 2ms +} + +/*++ + +Routine Description: + + SATA Late Configuration + + if the mode is selected as IDE->AHCI + { 1. Set class ID to AHCI + 2. Enable AHCI interrupt + } + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ +void sataInitLatePost(AMDSBCFG* pConfig){ + UINT32 ddBar5; + UINT8 dbVar; + + //Return immediately is sata controller is not enabled + if (pConfig->SataController == 0) return; + + restrictSataCapabilities(pConfig); + + //Get BAR5 value + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + + //Assign temporary BAR if is not already assigned + if ( (ddBar5 == 0) || (ddBar5 == -1) ){ + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) + ddBar5 = 0xFEC01000; + else + ddBar5=pConfig->TempMMIO; + WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + } + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Enable memory and io access + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); + //Enable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + + shutdownUnconnectedSataPortClock(pConfig, ddBar5); + + if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ + //program the AHCI class code + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); + //Set interrupt enable bit + RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1); + //program the correct device id for AHCI mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); + + if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) + //program the correct device id for AMD-AHCI mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + } + + //Disable write access to pci header and pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + //Clear error status + RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + //Restore memory and io access bits + WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); +} + + +void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){ + UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0; + UINT8 UnusedPortBitMap; + UINT8 SataType; + UINT8 ClockOffEnabled ; + + UnusedPortBitMap = 0; + + // First scan for all unused SATA ports + for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) { + ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); + if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) { + UnusedPortBitMap |= (1 << dbPortNum); + } + } + + // Decide if we need to shutdown the clock for all unused ports + SataType = pConfig->SataClass; + ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \ + (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \ + (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE))); + + if (ClockOffEnabled) { + //Shutdown the clock for the port and do the necessary port reporting changes. + TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap)); + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap); + RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00); + } + + // If all ports are in disabled state, report at least one + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + if ( (dbPortSataStatus & 0x3F) == 0) { + dbPortSataStatus = 1; + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus); + } + + // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time) + if (pConfig->SataHideUnusedPort && ClockOffEnabled) { + dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports + for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) { + if (dbPortSataStatus & (1 << dbPortNum)) + NumOfPorts++; + } + if (NumOfPorts == 0 ) { + NumOfPorts = 0x01; + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); + } +} + + +void restrictSataCapabilities(AMDSBCFG* pConfig){ + //Restrict capabilities + if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ + ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ + ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){ + pConfig->SataClass = NATIVE_IDE_MODE; + } +} diff --git a/src/vendorcode/amd/cimx/sb700/SB700.h b/src/vendorcode/amd/cimx/sb700/SB700.h new file mode 100644 index 0000000..f9e71e8 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SB700.h @@ -0,0 +1,1028 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SB700_H_ +#define _AMD_SB700_H_ + +#pragma pack(push,1) + +#define CIMx_Version 0x0660 +#define RC_Information 0x00 +#define Additional_Changes_Indicator 0x00 + +#define SB_POWERON_INIT 0x001 +#define OUTDEBUG_PORT 0x002 +#define SB_BEFORE_PCI_INIT 0x010 +#define SB_AFTER_PCI_INIT 0x020 +#define SB_LATE_POST_INIT 0x030 +#define SB_BEFORE_PCI_RESTORE_INIT 0x040 +#define SB_AFTER_PCI_RESTORE_INIT 0x050 +#define SB_SMM_SERVICE 0x060 +#define SB_SMM_ACPION 0x061 + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x100 +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC +#define ATI_AZALIA_ExtBlk_Addr 0x0F8 +#define ATI_AZALIA_ExtBlk_DATA 0x0FC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +#define SB7XX_DEVICE_ID 0x4385 + +#define SB700_A11 0x39 +#define SB700_A12 0x3A +#define SB700_A13 0x3B +#define SB700_A14 0x3C +#define SB700_A15 0x3D + +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define USB1_OHCI0_BUS_DEV_FUN ((0x12 << 3) + 0) +#define USB1_OHCI1_BUS_DEV_FUN ((0x12 << 3) + 1) +#define USB2_OHCI0_BUS_DEV_FUN ((0x13 << 3) + 0) +#define USB2_OHCI1_BUS_DEV_FUN ((0x13 << 3) + 1) +#define USB3_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) + +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define SBP2P_BUS_DEV_FUN ((0x14 << 3) + 4) +#define NB_BDF ((0 << 3) + 0) +#define HT_LINK_BUS_DEV_FUN ((0x18 << 3) + 0) +#define DCT1_BUS_DEV_FUN ((0x18 << 3) + 2) +#define DCT2_BUS_DEV_FUN ((0x19 << 3) + 2) +#define DCT3_BUS_DEV_FUN ((0x1A << 3) + 2) +#define DCT4_BUS_DEV_FUN ((0x1B << 3) + 2) + + +//Sata Controller Mode +#define NATIVE_IDE_MODE 0 +#define RAID_MODE 1 +#define AHCI_MODE 2 +#define LEGACY_IDE_MODE 3 +#define IDE_TO_AHCI_MODE 4 +#define AMD_AHCI_MODE 5 +#define IDE_TO_AMD_AHCI_MODE 6 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SB750_SATA_DEFAULT_DEVICE_ID 0x4393 + +#define SB_AX_INDXC_REG30 0x30 +#define SB_AX_DATAC_REG34 0x34 +#define SB_AX_INDXP_REG38 0x38 +#define SB_AX_DATAP_REG3C 0x3C + +#define AX_INDXC 0 +#define AX_INDXP 1 +#define AXCFG 2 +#define ABCFG 3 + +#define SB_AB_REG02 0x02 +#define SB_AB_REG04 0x04 +#define SB_AB_REG40 0x40 // +#define SB_AB_REG54 0x54 //;miscCtr54 +#define SB_AB_REG58 0x58 //;RAB Control - RW - 32 bits - [RegAddr:58] +#define SB_AB_REG60 0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:60] +#define SB_AB_REG64 0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] +#define SB_AB_REG6C 0x6C //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:6C] +#define SB_AB_REG80 0x80 //;DMA Prefetch Control Port 1 - RW - 32 bits - [RegAddr:80] +#define SB_AB_REG88 0x88 //;DMA Prefetch Control Port 2 - RW - 32 bits - [RegAddr:88] +#define SB_AB_REG8C 0x8C //;AB Enhancement - RW - 16 bits - [RegAddr:88] +#define SB_AB_REG90 0x90 //;BIF Control - RW - 32 bits - [RegAddr:90] +#define SB_AB_REG94 0x94 //;MSI Control - RW - 32 bits +#define SB_AB_REG98 0x98 //;BIF Control 1 - RW - 32 bits +#define SB_AB_REG9C 0x9C //; +#define SB_AB_REG10050 BIT16+0x50 +#define SB_AB_REG10054 BIT16+0x54 //;AL_Arb_Ctl, AL_Clk_Ctl +#define SB_AB_REG10060 BIT16+0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:10060] +#define SB_AB_REG10064 BIT16+0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] +#define SB_AB_REG10090 BIT16+0x90 //; +#define SB_AB_REG1009C BIT16+0x9C //; + + +#define SB_PMIO_REG00 0x000 // MiscControl +#define SB_PMIO_REG01 0x001 // MiscStatus +#define SB_PMIO_REG02 0x002 // SmiWakeUpEventEnable1 +#define SB_PMIO_REG03 0x003 // SmiWakeUpEventEnable2 +#define SB_PMIO_REG04 0x004 // SmiWakeUpEventEnable3 +#define SB_PMIO_REG05 0x005 // SmiWakeUpEventStatus1 +#define SB_PMIO_REG06 0x006 // SmiWakeUpEventStatus2 +#define SB_PMIO_REG07 0x007 // SmiWakeUpEventStatus3 +#define SB_PMIO_REG08 0x008 // InactiveTmrEventEnable1 +#define SB_PMIO_REG09 0x009 // InactiveTmrEventEnable2 +#define SB_PMIO_REG0A 0x00A // InactiveTmrEventEnable3 +#define SB_PMIO_REG0B 0x00B // PmTmr1InitValue +#define SB_PMIO_REG0C 0x00C // PmTmr1CurValue +#define SB_PMIO_REG0D 0x00D // PwrLedExtEvent +#define SB_PMIO_REG0E 0x00E // AcpiControl +#define SB_PMIO_REG0F 0x00F // AcpiStatus +#define SB_PMIO_REG10 0x010 // AcpiEn +#define SB_PMIO_REG11 0x011 // S1AgpStpEn +#define SB_PMIO_REG12 0x012 // PmTmr2InitValue +#define SB_PMIO_REG13 0x013 // PmTmr2CurValue +#define SB_PMIO_REG14 0x014 // Programlo0RangeLo +#define SB_PMIO_REG15 0x015 // ProgramIo0Rangei +#define SB_PMIO_REG16 0x016 // ProgramIo1RangeLo +#define SB_PMIO_REG17 0x017 // ProgramIo1Rangei +#define SB_PMIO_REG18 0x018 // ProgramIo2RangeLo +#define SB_PMIO_REG19 0x019 // ProgramIo2Rangei +#define SB_PMIO_REG1A 0x01A // ProgramIo3RangeLo +#define SB_PMIO_REG1B 0x01B // ProgramIo3Rangei +#define SB_PMIO_REG1C 0x01C // ProgramIoEnable +#define SB_PMIO_REG1D 0x01D // IOMonitorStatus +#define SB_PMIO_REG1E 0x01E // InactiveTmrEventEnable4 +#define SB_PMIO_REG20 0x020 // AcpiPm1EvtBlkLo +#define SB_PMIO_REG21 0x021 // AcpiPm1EvtBlki +#define SB_PMIO_REG22 0x022 // AcpiPm1CntBlkLo +#define SB_PMIO_REG23 0x023 // AcpiPm1CntBlki +#define SB_PMIO_REG24 0x024 // AcpiPmTmrBlkLo +#define SB_PMIO_REG25 0x025 // AcpiPmTmrBlki +#define SB_PMIO_REG26 0x026 // CpuControlLo +#define SB_PMIO_REG27 0x027 // CpuControli +#define SB_PMIO_REG28 0x028 // AcpiGpe0BlkLo +#define SB_PMIO_REG29 0x029 // AcpiGpe0Blki +#define SB_PMIO_REG2A 0x02A // AcpiSmiCmdLo +#define SB_PMIO_REG2B 0x02B // AcpiSmiCmdi +#define SB_PMIO_REG2C 0x02C // AcpiPmaCntBlkLo +#define SB_PMIO_REG2D 0x02D // AcpiPmaCntBlki +#define SB_PMIO_REG2E 0x02E // AcpiSsCntBlkLo +#define SB_PMIO_REG2F 0x02F // AcpiSsCntBlki +#define SB_PMIO_REG30 0x030 // GEvtConfig0 +#define SB_PMIO_REG31 0x031 // GEvtConfig1 +#define SB_PMIO_REG32 0x032 // GPMConfig0 +#define SB_PMIO_REG33 0x033 // GPMConfig1 +#define SB_PMIO_REG34 0x034 // GPMConfig2 +#define SB_PMIO_REG35 0x035 // GPMConfig3 +#define SB_PMIO_REG36 0x036 // GEvtLevelConfig +#define SB_PMIO_REG37 0x037 // GPMLevelConfig0 +#define SB_PMIO_REG38 0x038 // GPMLevelConfig1 +#define SB_PMIO_REG39 0x039 // GEvtStatus +#define SB_PMIO_REG3A 0x03A // PMEStatus0 +#define SB_PMIO_REG3B 0x03B // PMEStatus1 +#define SB_PMIO_REG3C 0x03C // OtersConfig +#define SB_PMIO_REG3E 0x03E // VRT_T1 +#define SB_PMIO_REG3F 0x03F // VRT_T2 +#define SB_PMIO_REG40 0x040 // Fan0DutyCycle +#define SB_PMIO_REG41 0x041 // Fan0Control +#define SB_PMIO_REG42 0x042 // Fan1DutyCycle +#define SB_PMIO_REG43 0x043 // Reserved for internal use +#define SB_PMIO_REG50 0x050 // PM_Enable +#define SB_PMIO_REG51 0x051 // TPRESET1 +#define SB_PMIO_REG52 0x052 // TPRESET2 +#define SB_PMIO_REG53 0x053 // TESTENABLE +#define SB_PMIO_REG54 0x054 // PWRBTTN_CLR +#define SB_PMIO_REG55 0x055 // SoftPciRst +#define SB_PMIO_REG56 0x056 // Reserved +#define SB_PMIO_REG59 0x059 // Ac97Mask +#define SB_PMIO_REG60 0x060 // Options_0 +#define SB_PMIO_REG61 0x061 // Options_1 +#define SB_PMIO_REG62 0x062 // Sadow_SCI +#define SB_PMIO_REG63 0x063 // SwitcVoltageTime +#define SB_PMIO_REG64 0x064 // SwitchGI_Time +#define SB_PMIO_REG65 0x065 // UsbPMControl +#define SB_PMIO_REG66 0x066 // MiscEnable66 +#define SB_PMIO_REG67 0x067 // MiscEnable67 +#define SB_PMIO_REG68 0x068 // MiscEnable68 +#define SB_PMIO_REG69 0x069 // WatcDogTimerControl +#define SB_PMIO_REG6C 0x06C // WatcDogTimerBase0 +#define SB_PMIO_REG6D 0x06D // WatcDogTimerBase1 +#define SB_PMIO_REG6E 0x06E // WatcDogTimerBase2 +#define SB_PMIO_REG6F 0x06F // WatcDogTimerBase3 +#define SB_PMIO_REG70 0x070 // S_LdtStartTime +#define SB_PMIO_REG71 0x071 // FidVidOption +#define SB_PMIO_REG72 0x072 // Spare4 +#define SB_PMIO_REG73 0x073 // Spare5 +#define SB_PMIO_REG74 0x074 // PwrFailSadow +#define SB_PMIO_REG75 0x075 // Tpreset1b +#define SB_PMIO_REG76 0x076 // S0S3ToS5Enable0 +#define SB_PMIO_REG77 0x077 // S0S3ToS5Enable1 +#define SB_PMIO_REG78 0x078 // S0S3ToS5Enable2 +#define SB_PMIO_REG79 0x079 // S0S3ToS5Enable3 +#define SB_PMIO_REG7A 0x07A // NoStatusControl0 +#define SB_PMIO_REG7B 0x07B // NoStatusControl1 +#define SB_PMIO_REG7C 0x07C // MiscEnable7C +#define SB_PMIO_REG80 0x080 // SMAF0 +#define SB_PMIO_REG81 0x081 // SMAF1 +#define SB_PMIO_REG82 0x082 // SMAF2 +#define SB_PMIO_REG83 0x083 // SMAF3 +#define SB_PMIO_REG84 0x084 // WakePinCntl +#define SB_PMIO_REG85 0x085 // CF9Rst +#define SB_PMIO_REG86 0x086 // ThermTrotCntl +#define SB_PMIO_REG87 0x087 // LdtStpCmd +#define SB_PMIO_REG88 0x088 // LdtStartTime +#define SB_PMIO_REG89 0x089 // AgpStartTime +#define SB_PMIO_REG8A 0x08A // LdtAgpTimeCntl +#define SB_PMIO_REG8B 0x08B // StutterTime +#define SB_PMIO_REG8C 0x08C // StpClkDlyTime +#define SB_PMIO_REG8D 0x08D // AbPmeCntl +#define SB_PMIO_REG8E 0x08E // FakeAsr +#define SB_PMIO_REG8F 0x08F // FakeAsrEn +#define SB_PMIO_REG90 0x090 // GEVENTOUT +#define SB_PMIO_REG91 0x091 // GEVENTEnable +#define SB_PMIO_REG92 0x092 // GEVENTIN +#define SB_PMIO_REG95 0x095 // GPM98EN +#define SB_PMIO_REG9A 0x09A // EnanceControl +#define SB_PMIO_REG9E 0x09E // EnanceControl +#define SB_PMIO_REG9F 0x09F // EnanceControl +#define SB_PMIO_REGA0 0x0A0 // Programlo4RangeLo +#define SB_PMIO_REGA1 0x0A1 // ProgramIo4Rangei +#define SB_PMIO_REGA2 0x0A2 // Programlo5RangeLo +#define SB_PMIO_REGA3 0x0A3 // ProgramIo5Rangei +#define SB_PMIO_REGA4 0x0A4 // Programlo6RangeLo +#define SB_PMIO_REGA5 0x0A5 // ProgramIo6Rangei +#define SB_PMIO_REGA6 0x0A6 // Programlo7RangeLo +#define SB_PMIO_REGA7 0x0A7 // ProgramIo7Rangei +#define SB_PMIO_REGA8 0x0A8 // PIO7654Enable +#define SB_PMIO_REGA9 0x0A9 // PIO7654Status +#define SB_PMIO_REGB0 0x0B0 +#define SB_PMIO_REGB1 0x0B1 +#define SB_PMIO_REGB2 0x0B2 // MiscControl3 +#define SB_PMIO_REGB4 0x0B4 // HPET BAR +#define SB_PMIO_REGB6 0x0B6 +#define SB_PMIO_REGB7 0x0B7 +#define SB_PMIO_REGBB 0x0BB // IMC_ACPI_Enable +#define SB_PMIO_REGBC 0x0BC // +#define SB_PMIO_REGBD 0x0BD // +#define SB_PMIO_REGC9 0x0C9 // MultiK8Control +#define SB_PMIO_REGCA 0x0CA // +#define SB_PMIO_REGCB 0x0CB // +#define SB_PMIO_REGCC 0x0CC // +#define SB_PMIO_REGCD 0x0CD // +#define SB_PMIO_REGD0 0x0D0 // +#define SB_PMIO_REGD2 0x0D2 // +#define SB_PMIO_REGD4 0x0D4 // +#define SB_PMIO_REGD7 0x0D7 // + + +#define SB_RTC_REG00 0x00 // Seconds - RW +#define SB_RTC_REG01 0x01 // Seconds Alarm - RW +#define SB_RTC_REG02 0x02 // Minutes - RW +#define SB_RTC_REG03 0x03 // Minutes Alarm - RW +#define SB_RTC_REG04 0x04 // ours - RW +#define SB_RTC_REG05 0x05 // ours Alarm- RW +#define SB_RTC_REG06 0x06 // Day of Week - RW +#define SB_RTC_REG07 0x07 // Date of Mont - RW +#define SB_RTC_REG08 0x08 // Mont - RW +#define SB_RTC_REG09 0x09 // Year - RW +#define SB_RTC_REG0A 0x0A // Register A - RW +#define SB_RTC_REG0B 0x0B // Register B - RW +#define SB_RTC_REG0C 0x0C // Register C - R +#define SB_RTC_REG0D 0x0D // DateAlarm - RW +#define SB_RTC_REG32 0x32 // AltCentury - RW +#define SB_RTC_REG48 0x48 // Century - RW +#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW +#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW +#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW +#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW + +#define B_ECMOS_REG00 0x00 // scratc-reg + //;BIT0=0 AsicDebug is enabled + //;BIT1=0 SLT S3 runs +#define SB_ECMOS_REG01 0x01 +#define SB_ECMOS_REG02 0x02 +#define SB_ECMOS_REG03 0x03 +#define SB_ECMOS_REG04 0x04 +#define SB_ECMOS_REG05 0x05 +#define SB_ECMOS_REG06 0x06 +#define SB_ECMOS_REG07 0x07 +#define SB_ECMOS_REG08 0x08 // save 32BIT Pysical address of Config structure +#define SB_ECMOS_REG09 0x09 +#define SB_ECMOS_REG0A 0x0A +#define SB_ECMOS_REG0B 0x0B + +#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID +#define SB_ECMOS_REG0D 0x0D //;Reserve for NB + +#define SB_IOMAP_REG00 0x000 // Dma_C 0 +#define SB_IOMAP_REG02 0x002 // Dma_C 1 +#define SB_IOMAP_REG04 0x004 // Dma_C 2 +#define SB_IOMAP_REG06 0x006 // Dma_C 3 +#define SB_IOMAP_REG08 0x008 // Dma_Status +#define SB_IOMAP_REG09 0x009 // Dma_WriteRest +#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask +#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode +#define SB_IOMAP_REG0C 0x00C // Dma_Clear +#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr +#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask +#define SB_IOMAP_REG0F 0x00F // Dma_AllMask +#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 +#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 +#define SB_IOMAP_REG40 0x040 // TimerC0 +#define SB_IOMAP_REG41 0x041 // TimerC1 +#define SB_IOMAP_REG42 0x042 // TimerC2 +#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord +#define SB_IOMAP_REG61 0x061 // Nmi_Status +#define SB_IOMAP_REG70 0x070 // Nmi_Enable +#define SB_IOMAP_REG71 0x071 // RtcDataPort +#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 +#define SB_IOMAP_REG81 0x081 // Dma_PageC2 +#define SB_IOMAP_REG82 0x082 // Dma_PageC3 +#define SB_IOMAP_REG83 0x083 // Dma_PageC1 +#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 +#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 +#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 +#define SB_IOMAP_REG87 0x087 // Dma_PageC0 +#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 +#define SB_IOMAP_REG89 0x089 // Dma_PageC6 +#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 +#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 +#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 +#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 +#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 +#define SB_IOMAP_REG8F 0x08F // Dma_Refres +#define SB_IOMAP_REG92 0x092 // FastInit +#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 +#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 +#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define SB_IOMAP_REGD0 0x0D0 // Dma_Status +#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear +#define SB_IOMAP_REGDA 0x0DA // Dma_Clear +#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define SB_IOMAP_REGF0 0x0F0 // NCP_Error +#define SB_IOMAP_REG40B 0x040B // DMA1_Extend +#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define SB_IOMAP_REGC14 0x0C14 // Pci_Error +#define SB_IOMAP_REGC50 0x0C50 // CMIndex +#define SB_IOMAP_REGC51 0x0C51 // CMData +#define SB_IOMAP_REGC52 0x0C52 // GpmPort +#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index +#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data +#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + + +#define SB_CM_REG02 0x002 // TempStatus (via SB_IOMAP_REGC50) +#define SB_CM_REG03 0x003 // TempInterrupt (via SB_IOMAP_REGC50) + +#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits +#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits +#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits +#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits +#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 +#define SB_SATA_REG0C 0x00C // Cace Line Size - R/W - 8bits +#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits +#define SB_SATA_REG0E 0x00E // eader Type - R - 8 bits +#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits +#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits +#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits +#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits +#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits +#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits +#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits +#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits +#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits +#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits +#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits +#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits +#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits +#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits +#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits +#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits +#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits +#define SB_SATA_REG48 0x048 +#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits +#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits +#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits +#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits +#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits +#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits +#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits +#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits +#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits +#define SB_SATA_REG68 0x068 // MSI Program Weigt - R/W - 8 bits +#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits +#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits +#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_REG86 0x086 // PY Global Control +#define SB_SATA_REG87 0x087 +#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG8A 0x08A +#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG8E 0x08E +#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG92 0x092 +#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG96 0x096 +#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_REGA0 0x0A0 // +#define SB_SATA_REGA4 0x0A4 // +#define SB_SATA_REGA5 0x0A5 //; +#define SB_SATA_REGA8 0x0A8 // +#define SB_SATA_REGAD 0x0AD //; +#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_REGB5 0x0B5 //; +#define SB_SATA_REGBD 0x0BD //; +#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits +#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits + +#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits +#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits +#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits +#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits +#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits +#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits +#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Aead Data - RW - 32 bits +#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits +#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits +#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits +#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Aead Data - RW - 32 bits +#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration +#define SB_SATA_BAR5_REGFC 0x0FC + +#define SB_SATA_BAR5_REG100 0x0100 //;Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define SB_SATA_BAR5_REG104 0x0104 //;Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define SB_SATA_BAR5_REG108 0x0108 //;Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define SB_SATA_BAR5_REG10C 0x010C //;Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define SB_SATA_BAR5_REG110 0x0110 // Port-N Interrupt Status +#define SB_SATA_BAR5_REG144 0x0144 //;Serial ATA PY Configuration - RW - 32 bits +#define SB_SATA_BAR5_REG148 0x0148 //;SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] +#define SB_SATA_BAR5_REG14C 0x014C //;SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] +#define SB_SATA_BAR5_REG120 0x0120 // Port Task Fike Data +#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control + +#define SB_SATA_BAR5_REG130 0x0130 +#define SB_SATA_BAR5_REG1B0 0x01B0 +#define SB_SATA_BAR5_REG230 0x0230 +#define SB_SATA_BAR5_REG2B0 0x02B0 + +#define SB_FC_REG00 0x00 // Device/Vendor ID - R +#define SB_FC_REG04 0x04 // Command - RW +#define SB_FC_REG10 0x10 // BAR + +#define SB_FC_MMIO_REG70 0x070 +#define SB_FC_MMIO_REG200 0x200 + +#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R +#define SB_OHCI_REG04 0x04 // Command - RW +#define SB_OHCI_REG06 0x06 // Status - R +#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_OHCI_REG10 0x10 // Bar_OCI - RW +#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define SB_OHCI_REG34 0x34 // Capability Pointer - R +#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW + +#define SB_OHCI_REG40 0x40 // Config Timers - RW +#define SB_OHCI_REG4C 0x4C // MSI Weigt - RW +#define SB_OHCI_REG50 0x50 // ATI Misc Control - RW +#define SB_OHCI_REG51 0x51 +#define SB_OHCI_REG58 0x58 // Over Current Control - RW +#define SB_OHCI_REG5C 0x5C // Over Current Control - RW +#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R +#define SB_OHCI_REG68 0x68 // Over Current Enable - RW +#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_OHCI_BAR_REG00 0x00 // cRevision - R +#define SB_OHCI_BAR_REG04 0x04 // cControl +#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus +#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define SB_OHCI_BAR_REG18 0x18 // HcCCA +#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define SB_OHCI_BAR_REG20 0x20 // HcControleadED +#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define SB_OHCI_BAR_REG30 0x30 // HcDoneead +#define SB_OHCI_BAR_REG34 0x34 // cFmInterval +#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining +#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber +#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold +#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define SB_OHCI_BAR_REG50 0x50 // HcRStatus +#define SB_OHCI_BAR_REG160 0x160 + +#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define SB_EHCI_REG04 0x04 // Command - RW +#define SB_EHCI_REG06 0x06 // Status - R +#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_EHCI_REG10 0x10 // BAR - RW +#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define SB_EHCI_REG34 0x34 // Capability Pointer - R +#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW +#define SB_EHCI_REG40 0x40 // Config Timers - RW +#define SB_EHCI_REG4C 0x4C // MSI Weigt - RW +#define SB_EHCI_REG50 0x50 // ATI Misc Control - RW +#define SB_EHCI_REG54 0x54 // ATI Misc Control - RW +#define SB_EHCI_REG58 0x58 // Over Current Control - R +#define SB_EHCI_REG60 0x60 // SBRN - R +#define SB_EHCI_REG61 0x61 // FLADJ - RW +#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW +#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_EHCI_REGDC 0x0DC // PME Control - RW +#define SB_EHCI_REGE0 0x0E0 // PME Data / Status - RW +#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R +#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define SB_EHCI_BAR_REG64 0x064 // PORTSC(1-N_PORTS) -RW - 32 bits +#define SB_EHCI_BAR_REG84 0x084 // Packet Buffer Thresold Values - RW - 32 bits +#define SB_EHCI_BAR_REG88 0x088 // Packet Buffer Dept Value - RW - 32 bits +#define SB_EHCI_BAR_REG94 0x094 // UTMI Control and Status - RW - 32 bits +#define SB_EHCI_BAR_REG98 0x098 // Bist Control - RW - 32 bits +#define SB_EHCI_BAR_REG9C 0x09C // ATI EOR Control - RW - 32 bits +#define SB_EHCI_BAR_REGA4 0x0A4 // USB IN/OUT FIFO Thresold Setting +#define SB_EHCI_BAR_REGBC 0x0BC // ECI misc Setting +#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Auto Calibration Setting + +#define SB_SMBUS_REG00 0x000 //;VendorID - R +#define SB_SMBUS_REG02 0x002 //;DeviceID - R +#define SB_SMBUS_REG04 0x004 // Command- RW +#define SB_SMBUS_REG05 0x005 // Command- RW +#define SB_SMBUS_REG06 0x006 // STATUS- RW +#define SB_SMBUS_REG08 0x008 // Revision ID/Class Code- R +#define SB_SMBUS_REG0A 0x00A //; +#define SB_SMBUS_REG0B 0x00B //; +#define SB_SMBUS_REG0C 0x00C // Cace Line Size- R +#define SB_SMBUS_REG0D 0x00D // Latency Timer- R +#define SB_SMBUS_REG0E 0x00E // eader Type- R +#define SB_SMBUS_REG0F 0x00F // BIST- R +#define SB_SMBUS_REG10 0x010 // Base Address 0- R +#define SB_SMBUS_REG11 0x011 //; +#define SB_SMBUS_REG12 0x012 //; +#define SB_SMBUS_REG13 0x013 //; +#define SB_SMBUS_REG14 0x014 // Base Address 1- R +#define SB_SMBUS_REG18 0x018 // Base Address 2- R +#define SB_SMBUS_REG1C 0x01C // Base Address 3- R +#define SB_SMBUS_REG20 0x020 // Base Address 4- R +#define SB_SMBUS_REG24 0x024 // Base Address 5- R +#define SB_SMBUS_REG28 0x028 // Cardbus CIS Pointer- R +#define SB_SMBUS_REG2C 0x02C // Subsystem Vendor ID- W +#define SB_SMBUS_REG2E 0x02E // Subsystem ID- W +#define SB_SMBUS_REG30 0x030 // Expansion ROM Base Address - R +#define SB_SMBUS_REG34 0x034 // Capability Pointer - R +#define SB_SMBUS_REG38 0x038 +#define SB_SMBUS_REG3C 0x03C // Interrupt Line - R +#define SB_SMBUS_REG3D 0x03D // Interrupt Pin - R +#define SB_SMBUS_REG3E 0x03E // Min_Gnt - R +#define SB_SMBUS_REG3F 0x03F // Max_Lat - R +#define SB_SMBUS_REG40 0x040 // PCI Control- RW +#define SB_SMBUS_REG41 0x041 // MiscFunction- RW +#define SB_SMBUS_REG42 0x042 // DmaLimit- RW +#define SB_SMBUS_REG43 0x043 // DmaEnanceEnable RW +#define SB_SMBUS_REG48 0x048 // ISA Address Decode Control Register #1- RW +#define SB_SMBUS_REG49 0x049 // ISA Address Decode Control Register #2- RW +#define SB_SMBUS_REG4A 0x04A // Scratc Pad- RW +#define SB_SMBUS_REG50 0x050 // PciGpioOutControl- RW +#define SB_SMBUS_REG54 0x054 // PciGpioConfig- RW +#define SB_SMBUS_REG58 0x058 // ASFSMBusIoBase +#define SB_SMBUS_REG59 0x059 //; +#define SB_SMBUS_REG5C 0x05C // Smart Power Control1 +#define SB_SMBUS_REG60 0x060 // MiscEnable- RW +#define SB_SMBUS_REG64 0x064 // Features Enable- RW +#define SB_SMBUS_REG68 0x068 // UsbEnable - RW +#define SB_SMBUS_REG6C 0x06C // TestMode- RW +#define SB_SMBUS_REG70 0x070 // RunTimeTest- R +#define SB_SMBUS_REG74 0x074 // IoApic_Conf- RW +#define SB_SMBUS_REG78 0x078 // IoAddrEnable - R/W +#define SB_SMBUS_REG79 0x079 //; +#define SB_SMBUS_REG7C 0x07C // RTC Control ;VSJ-2005-06-16 +#define SB_SMBUS_REG80 0x080 // GPIO_Out_Cntrl - RW +#define SB_SMBUS_REG81 0x081 // GPIO_Status - R +#define SB_SMBUS_REG90 0x090 // Smbus Base Address - R +#define SB_SMBUS_REG94 0x094 // Reserved - R +#define SB_SMBUS_REG98 0x098 // +#define SB_SMBUS_REGA0 0x0A0 // MoreGPIOIn +C R +#define SB_SMBUS_REGA4 0x0A4 // MoreGPIOIn +C R +#define SB_SMBUS_REGA8 0x0A8 // GPIOControl +C RW +#define SB_SMBUS_REGAC 0x0AC // MiscUsbEt - RW +#define SB_SMBUS_REGAD 0x0AD // MiscSata +#define SB_SMBUS_REGAE 0x0AE +#define SB_SMBUS_REGAF 0x0AF // SataIntMap - RW +#define SB_SMBUS_REGB0 0x0B0 // MSI Mapping Capability - R +#define SB_SMBUS_REGB4 0x0B4 //HPET BASE Address +#define SB_SMBUS_REGBC 0x0BC // PciIntGpio - RW +#define SB_SMBUS_REGBE 0x0BE // UsbIntMap - RW +#define SB_SMBUS_REGC0 0x0C0 // IokHiDrvSt - RW +#define SB_SMBUS_REGD0 0x0D0 // +#define SB_SMBUS_REGD2 0x0D2 // I2CbusConfig - RW +#define SB_SMBUS_REGD3 0x0D3 // I2CCommand - RW +#define SB_SMBUS_REGD4 0x0D4 // I2CSadow1- RW +#define SB_SMBUS_REGD5 0x0D5 // I2Csadow2- RW +#define SB_SMBUS_REGD6 0x0D6 // I2CBusRevision - RW +#define SB_SMBUS_REGE0 0x0E0 // MSI_Weigt +#define SB_SMBUS_REGE1 0x0E1 // MSI_Weigt +#define SB_SMBUS_REGF0 0x0F0 // AB_REG_BAR - RW +#define SB_SMBUS_REGF1 0x0F1 +#define SB_SMBUS_REGF4 0x0F4 // WakeIoAddr- RW +#define SB_SMBUS_REGF8 0x0F8 // ExtendedAddrPort- RW +#define SB_SMBUS_REGFC 0x0FC // ExtendedDataPort- RW + + +#define SB_IDE_REG00 0x00 // Vendor ID +#define SB_IDE_REG02 0x02 // Device ID +#define SB_IDE_REG04 0x04 // Command +#define SB_IDE_REG06 0x06 // Status +#define SB_IDE_REG08 0x08 // Revision ID/Class Code +#define SB_IDE_REG09 0x09 // Class Code +#define SB_IDE_REG0A 0x0A +#define SB_IDE_REG0C 0x0C // Cace Link Size +#define SB_IDE_REG0D 0x0D // Master Latency Timer +#define SB_IDE_REG0E 0x0E // eader Type +#define SB_IDE_REG0F 0x0F // BIST Mode Type +#define SB_IDE_REG10 0x10 // Base Address 0 +#define SB_IDE_REG14 0x14 // Base Address 1 +#define SB_IDE_REG18 0x18 // Base Address 2 +#define SB_IDE_REG1C 0x1C // Base Address 3 +#define SB_IDE_REG20 0x20 // Bus Master Interface Base Address +#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define SB_IDE_REG34 0x34 // MSI Capabilities Pointer +#define SB_IDE_REG3C 0x3C // Interrupt Line +#define SB_IDE_REG3D 0x3D // Interrupt Pin +#define SB_IDE_REG3E 0x3E // Min_gnt +#define SB_IDE_REG3F 0x3F // Max_latency +#define SB_IDE_REG40 0x40 // IDE PIO Timing +#define SB_IDE_REG44 0x44 // IDE Legacy DMA (Multi-words DMA) Timing Modes +#define SB_IDE_REG48 0x48 // IDE PIO Control +#define SB_IDE_REG4A 0x4A // IDE PIO Mode +#define SB_IDE_REG4C 0x4C // IDE Status +#define SB_IDE_REG54 0x54 // IDE Ultra DMAControl +#define SB_IDE_REG55 0x55 // IDE Ultra DMA Status +#define SB_IDE_REG56 0x56 // IDE Ultra DMA Mode +#define SB_IDE_REG60 0x60 // IDE PCI Retry Timing Counter +#define SB_IDE_REG61 0x61 // PCI Error Control +#define SB_IDE_REG62 0x62 // IDE Internal Control +#define SB_IDE_REG63 0x63 // IDE Internal Control +#define SB_IDE_REG64 0x64 // IDE PLL Control +#define SB_IDE_REG68 0x68 // IDE MSI Programmable Weigt +#define SB_IDE_REG6C 0x6C // IDE Dynamic Clocking +#define SB_IDE_REG70 0x70 // IDE MSI Control +#define SB_IDE_REG74 0x74 // IDE MSI Address Register +#define SB_IDE_REG78 0x78 // IDE MSI Data Register + + +#define SB_AZ_REG00 0x00 // Vendor ID - R +#define SB_AZ_REG02 0x02 // Device ID - R/W +#define SB_AZ_REG04 0x04 // PCI Command +#define SB_AZ_REG06 0x06 // PCI Status - R/W +#define SB_AZ_REG08 0x08 // Revision ID +#define SB_AZ_REG09 0x09 // Programming Interface +#define SB_AZ_REG0A 0x0A // Sub Class Code +#define SB_AZ_REG0B 0x0B // Base Class Code +#define SB_AZ_REG0C 0x0C // Cace Line Size - R/W +#define SB_AZ_REG0D 0x0D // Latency Timer +#define SB_AZ_REG0E 0x0E // eader Type +#define SB_AZ_REG0F 0x0F // BIST +#define SB_AZ_REG10 0x10 // Lower Base Address Register +#define SB_AZ_REG14 0x14 // Upper Base Address Register +#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID +#define SB_AZ_REG2D 0x2D // Subsystem ID +#define SB_AZ_REG34 0x34 // Capabilities Pointer +#define SB_AZ_REG3C 0x3C // Interrupt Line +#define SB_AZ_REG3D 0x3D // Interrupt Pin +#define SB_AZ_REG3E 0x3E // Minimum Grant +#define SB_AZ_REG3F 0x3F // Maximum Latency +#define SB_AZ_REG40 0x40 // Misc Control 1 +#define SB_AZ_REG42 0x42 // Misc Control 2 Register +#define SB_AZ_REG43 0x43 // Misc Control 3 Register +#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register +#define SB_AZ_REG46 0x46 // Debug Control Register +#define SB_AZ_REG4C 0x4C +#define SB_AZ_REG50 0x50 // Power Management Capability ID +#define SB_AZ_REG52 0x52 // Power Management Capabilities +#define SB_AZ_REG54 0x54 // Power Management Control/Status +#define SB_AZ_REG60 0x60 // MSI Capability ID +#define SB_AZ_REG62 0x62 // MSI Message Control +#define SB_AZ_REG64 0x64 // MSI Message Lower Address +#define SB_AZ_REG68 0x68 // MSI Message Upper Address +#define SB_AZ_REG6C 0x6C // MSI Message Data + +#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define SB_AZ_BAR_REG02 0x02 // Minor Version - R +#define SB_AZ_BAR_REG03 0x03 // Major Version - R +#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W +#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define SB_AZ_BAR_REG0E 0x0E // State Cange Status - R/W +#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W +#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define SB_AZ_BAR_REG38 0x38 // Stream Syncronization - R/W +#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + + +#define SB_LPC_REG00 0x00 // VID- R +#define SB_LPC_REG02 0x02 // DID- R +#define SB_LPC_REG04 0x04 // CMD- RW +#define SB_LPC_REG06 0x06 // STATUS- RW +#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R +#define SB_LPC_REG0C 0x0C // Cace Line Size - R +#define SB_LPC_REG0D 0x0D // Latency Timer - R +#define SB_LPC_REG0E 0x0E // eader Type - R +#define SB_LPC_REG0F 0x0F // BIST- R +#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define SB_LPC_REG40 0x40 // PCI Control - RW +#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define SB_LPC_REG4C 0x4C // Memory Range Register - RW +#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW +#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW +#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW +#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define SB_LPC_REG65 0x65 +#define SB_LPC_REG66 0x66 +#define SB_LPC_REG67 0x67 +#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define SB_LPC_REG69 0x69 +#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define SB_LPC_REG6B 0x6B +#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define SB_LPC_REG6D 0x6D +#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define SB_LPC_REG6F 0x6F +#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* +#define SB_LPC_REG71 0x71 +#define SB_LPC_REG72 0x72 +#define SB_LPC_REG73 0x73 +#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R +#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define SB_LPC_REG9C 0x9C +#define SB_LPC_REG80 0x80 // MSI Capability Register- R +#define SB_LPC_REG8C 0x8C +#define SB_LPC_REGA0 0x0A0 // SPI base address +#define SB_LPC_REGA1 0x0A1 // SPI base address +#define SB_LPC_REGA2 0x0A2 // SPI base address +#define SB_LPC_REGA3 0x0A3 // SPI base address +#define SB_LPC_REGA4 0x0A4 +#define SB_LPC_REGB8 0x0B8 +#define SB_LPC_REGBA 0x0BA // EcControl +#define SB_LPC_REGBB 0x0BB // HostControl + + +#define SB_P2P_REG00 0x00 // VID - R +#define SB_P2P_REG02 0x02 // DID - R +#define SB_P2P_REG04 0x04 // CMD- RW +#define SB_P2P_REG06 0x06 // STATUS- RW +#define SB_P2P_REG08 0x08 // Revision ID/Class Code- R +#define SB_P2P_REG0C 0x0C // CSIZE- RW +#define SB_P2P_REG0D 0x0D // LTIMER- RW +#define SB_P2P_REG0E 0x0E // TYPE- R +#define SB_P2P_REG18 0x18 // PBN- RW +#define SB_P2P_REG19 0x19 // SBN- RW +#define SB_P2P_REG1A 0x1A // SUBBN- RW +#define SB_P2P_REG1B 0x1B // SLTIMER- RW +#define SB_P2P_REG1C 0x1C // IOBASE- RW +#define SB_P2P_REG1D 0x1D // IOLMT- RW +#define SB_P2P_REG1E 0x1E // SSTATUS- RW +#define SB_P2P_REG20 0x20 // MBASE- RW +#define SB_P2P_REG21 0x21 +#define SB_P2P_REG22 0x22 // MLMT- RW +#define SB_P2P_REG23 0x23 +#define SB_P2P_REG24 0x24 // PMBASE- RW +#define SB_P2P_REG25 0x25 +#define SB_P2P_REG26 0x26 // PMLMT- RW +#define SB_P2P_REG27 0x27 +#define SB_P2P_REG30 0x30 // IOBU16- RW +#define SB_P2P_REG32 0x32 // IOLU16- RW +#define SB_P2P_REG34 0x34 // ECP_PTR- R +#define SB_P2P_REG3C 0x3C // INTLN- RW +#define SB_P2P_REG3D 0x3D // INTPN- R +#define SB_P2P_REG3E 0x3E // BCTRL- RW +#define SB_P2P_REG40 0x40 // CPCTRL- R/W +#define SB_P2P_REG41 0x41 // DCTRL- RW +#define SB_P2P_REG42 0x42 // CLKCTRL- R/W +#define SB_P2P_REG43 0x43 // ARCTRL- RW +#define SB_P2P_REG44 0x44 // SMLT_PERF- RW +#define SB_P2P_REG46 0x46 // PMLT_PERF- RW +#define SB_P2P_REG48 0x48 // PCDMA- RW +#define SB_P2P_REG49 0x49 // Additional Priority- Bits RW +#define SB_P2P_REG4A 0x4A // PCICLK Enable- Bits RW +#define SB_P2P_REG4B 0x4B // Misc Control RW +#define SB_P2P_REG4C 0x4C // AutoClockRun control RW +#define SB_P2P_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop +#define SB_P2P_REG54 0x54 // MSI Mapping Capability +#define SB_P2P_REG58 0x58 // Signature Register of Microsoft Rework +#define SB_P2P_REG64 0x64 // Misc Control Register +#define SB_P2P_REG65 0x65 // Misc Control Register + +#define SB_PMIO2_REG00 0x00 +#define SB_PMIO2_REG01 0x01 +#define SB_PMIO2_REG31 0x31 +#define SB_PMIO2_REG32 0x32 +#define SB_PMIO2_REG33 0x33 +#define SB_PMIO2_REG34 0x34 +#define SB_PMIO2_REG35 0x35 +#define SB_PMIO2_REG36 0x36 +#define SB_PMIO2_REG37 0x37 +#define SB_PMIO2_REG38 0x38 +#define SB_PMIO2_REG39 0x39 +#define SB_PMIO2_REG3A 0x3A +#define SB_PMIO2_REG3B 0x3B +#define SB_PMIO2_REG3C 0x3C +#define SB_PMIO2_REG3D 0x3D +#define SB_PMIO2_REG3E 0x3E +#define SB_PMIO2_REG3F 0x3F +#define SB_PMIO2_REG40 0x40 +#define SB_PMIO2_REG41 0x41 +#define SB_PMIO2_REG42 0x42 +#define SB_PMIO2_REG43 0x43 +#define SB_PMIO2_REG44 0x44 +#define SB_PMIO2_REG45 0x45 +#define SB_PMIO2_REG46 0x46 +#define SB_PMIO2_REG47 0x47 +#define SB_PMIO2_REG48 0x48 +#define SB_PMIO2_REG49 0x49 +#define SB_PMIO2_REG54 0x54 +#define SB_PMIO2_REG58 0x58 +#define SB_PMIO2_REG59 0x59 +#define SB_PMIO2_REG5A 0x5A +#define SB_PMIO2_REG5B 0x5B +#define SB_PMIO2_REG5C 0x5C +#define SB_PMIO2_REG70 0x70 +#define SB_PMIO2_REGE5 0xE5 + +#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register + + +//Bus 0 Device 0x18 Function 0 HyperTransfer +//Link Frequency/Revision Register 0x88/0xA8/0xC8/0xE8 - 32 bits. +#define HT_LINK_REG89 0x89 +#define HT_LINK_REGA9 0xA9 +#define HT_LINK_REGC9 0xC9 +#define HT_LINK_REGE9 0xE9 + +//Link Type Register 0x98/0xB8/0xD8/0xF8 - 32 bits. +#define HT_LINK_REG98 0x98 +#define HT_LINK_REGB8 0xB8 +#define HT_LINK_REGD8 0xD8 +#define HT_LINK_REGF8 0xF8 + +//Link Frequency Extension Register 0x9C/0xBC/0xDC/0xFC - 32 bits. +#define HT_LINK_REG9C 0x9C +#define HT_LINK_REGBC 0xBC +#define HT_LINK_REGDC 0xDC +#define HT_LINK_REGFC 0xFC + +//DRAM CS Base Address Register D18F2x40/x48/x50/x58 +#define DCT_REG40 0x40 +#define DCT_REG48 0x48 +#define DCT_REG50 0x50 +#define DCT_REG58 0x58 + +//DRAM Configuration Low Register D18F2x90/x91/x92/x93 +#define DCT_REG90 0x90 +#define DCT_REG91 0x91 +#define DCT_REG92 0x92 +#define DCT_REG93 0x93 + +#pragma pack(pop) + +#endif //#ifndef _AMD_SB700_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c new file mode 100644 index 0000000..7d5b4f4 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c @@ -0,0 +1,572 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +REG8MASK sbEarlyPostByteInitTable[]={ + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible. + {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information + {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)}, + {SB_SMBUS_REG24+2, 0x00, RC_Information}, + {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible. + {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer. + // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts + {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled, + // Combined mode enabled, SATA as primary, power saving enable + {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG# + {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection + {0xFF, 0xFF, 0xFF}, + + // IDE Device(Bus 0, Dev 20, Func 1) + {0x00, IDE_BUS_DEV_FUN, 0}, + {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 + // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 + {0xFF, 0xFF, 0xFF}, + + // Azalia Device(Bus 0, Dev 20, Func 2) + {0x00, AZALIA_BUS_DEV_FUN, 0}, + {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0}, + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + + {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2] + {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability + {0xFF, 0xFF, 0xFF}, + + // P2P Bridge(Bus 0, Dev 20, Func 4) + {0x00, SBP2P_BUS_DEV_FUN, 0}, + + {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01 + //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01 + {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] + + {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership + {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. + + {0xFF, 0xFF, 0xFF}, + + // SATA Device(Bus 0, Dev 17, Func 0) + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post + {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1 + {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1 + {SB_SATA_REG48+3, 0xff, BIT0}, + {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out. + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbEarlyPostPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b + {SB_PMIO_REG01, 0xff, BIT1}, + {SB_PMIO_REG0E, 0xff, BIT2 + BIT3}, + {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn + {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB + {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0 + {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status + {SB_PMIO_REG05, 0xFF, 0xFF }, + {SB_PMIO_REG06, 0xFF, 0xFF }, + {SB_PMIO_REG07, 0xFF, 0xFF }, + {SB_PMIO_REG0F, 0xFF, 0x1F }, + {SB_PMIO_REG1D, 0xFF, 0xFF }, + {SB_PMIO_REG39, 0xFF, 0xFF }, + {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED + {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state + {SB_PMIO_REG68, 0x38, 0x84}, + {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure + {SB_PMIO_REG84, 0xFD, BIT3+BIT0}, + {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock + //is either 25 or 100Mhz and so the default acpi clock is actually + //running at 12.5Mhz and so the system time will run slow. We have + //generated another internal clock which runs at 14.318Mhz which is the + //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1 + //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period + //increase to 30.8 ns. + {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller + //to sleep for 6 uframes in stead of the standard 10us to + //improve power saving. + {SB_PMIO_REGD7, 0xFF, BIT6+BIT1}, + +}; + + +// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also +void commonInitEarlyBoot(AMDSBCFG* pConfig) { + UINT16 dwTempVar; + CPUID_DATA CpuId; + CPUID_DATA CpuId_Brand; + UINT8 dbValue; + UINT32 ddValue; + UINT8 Family, Model, Stepping; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n")); + CpuidRead (0x01, &CpuId); + CpuidRead (0x80000001, &CpuId_Brand); //BrandID + + //Early post initialization of pci config space + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) ); + + // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4); + + + #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot. + //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before + //changing it. + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar); + if ( (dwTempVar == 0x08) || (dwTempVar == 0x00)) + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF + #endif + + if (pConfig->AzaliaController == 1) + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); + else + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + + //Disable or Enable PCI Clks based on input + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) ); + ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch + RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter + + abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers + // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package + ddValue = CpuId.REG_EAX & 0x00FF00F0; + dbValue = 1; + + if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) { + if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { + //Orochi processor G34/C32, set to 10us + dbValue = 10; + } + else { + // Orochi processor AM3, set to 5us + dbValue = 5; + } + } + + if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) { + //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us + dbValue = 10; + } + + + RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue); + + // Enable/Disable watchdog timer + RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable)); + + // Per SB700/SP5100 RPR 2.5 + // + // Enable C1e stutter timer for any system with chip revision >= A14 + // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms + // + + if (getRevisionID() >= SB700_A14) { + dwTempVar = 0x0010; + + // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable + // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment + RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5); + + Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16); + Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4); + Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f); + + // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled: + // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah + // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms + if (IsLs2Mode() && (Family == 0x10)) { + switch( Model ){ + case 0x4: + case 0x5: + if( Stepping >= 3 ) dwTempVar = 0x14; + break; + case 0x6: + if( Stepping >= 2 ) dwTempVar = 0x14; + break; + case 0x8: + if( Stepping >= 1 ) dwTempVar = 0x14; + break; + case 0x9: + if( Stepping >= 1 ) dwTempVar = 0x14; + break; + case 0xA: + dwTempVar = 0x14; + break; + } + } + // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7); + } + + //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor. + ddValue = CpuId.REG_EAX; + if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) { + // + // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a + // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically + // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the + // BM_STS bit to be set and therefore causing the C state logic to exit. + // + // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic + // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5); + + // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT# + RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2); + + // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e + // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry + RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4); + + + // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER + // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic. + // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the + // HALT_EXIT message as a break event. + // + // Set ServerCEn + RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + + // Enable counting HALT + // PMIO:0xc9[4] = CountHaltMsgEn + // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message + RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1); + } + + c3PopupSetting(pConfig); + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n")); +} + + +void commonInitEarlyPost(AMDSBCFG* pConfig){ + //early post initialization of pmio space + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) ); + CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); +} + + +// AB-Link Configuration Table +ABTBLENTRY abTblEntry600[]={ + // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1 + // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of + // SMI# and IO is important for the IO trap to work properly. + {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 }, + // Enabling UpStream DMA Access AXCFG: 0x04[2]=1 + {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 }, + // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1 + {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 }, + // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions) + // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation + // Enabling Additional Address Bits Checking in Downstream Register Programming + // ABCFG 0x9C[1] = 1 + {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 }, + // Enabling IDE/PCIB Prefetch for Performance Enhancement + // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1 + // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 + {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable + {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable + // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 + // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] + {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE }, + // Programming cycle delay for AB and BIF clock gating + // Enabling AB and BIF Clock Gating + // Enabling AB Int_Arbiter Enhancement + // Enabling Requester ID + {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF }, + {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1 +// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 }, + {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 }, + + {ABCFG,0,0,-1}, // This dummy entry is to clear ab index + {-1, -1, -1, -1 }, +}; + + +// AB-Link Configuration Table +ABTBLENTRY abTblForA15[]={ + + //SMI Reordering fix + {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 }, + {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5}, + + //Posted pass NP Downstream feature + {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 }, + {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6}, + {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4}, + + //Posted pass NP upstream feature + {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11}, + + //64 bit Non-posted memory write support + {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 }, + + {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9}, + + {ABCFG,0,0,-1}, // This dummy entry is to clear ab index + {-1, -1, -1, -1 }, +}; + + +// abLinkInitBeforePciEnum - Set ABCFG registers +void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){ + ABTBLENTRY *pAbTblPtr; + + // disable PMIO decoding when AB is set + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0); + + pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]); + abcfgTbl(pAbTblPtr); + + if (getRevisionID() > SB700_A11){ + //Enable OHCI Prefetch + writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0); + //Register bit to maintain correct ordering of SMI and IO write completion + writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8); + } + + if (getRevisionID() >= SB700_A14){ + //Enable fix for TT SB01345 + writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17); + //Disable IO Write and SMI ordering enhancement + writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF)); + } + + if (getRevisionID() >= SB700_A15) { + pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]); + abcfgTbl(pAbTblPtr); + } + + + // enable pmio decoding after ab is configured + // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); +} + + +void abcfgTbl(ABTBLENTRY* pABTbl){ + UINT32 ddValue; + + while ((pABTbl->regType) != 0xFF){ + TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData)); + if (pABTbl->regType > AX_INDXP){ + ddValue = pABTbl->regIndex | (pABTbl->regType << 30); + writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); + } + else{ + ddValue = 0x30 | (pABTbl->regType << 30); + writeAlink(ddValue, pABTbl->regIndex); + ddValue = 0x34 | (pABTbl->regType << 30); + writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); + } + ++pABTbl; + } + + //Clear ALink Access Index + ddValue = 0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); + TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n")); +} + + +// programSubSystemIDs - Config Subsystem ID for all SB devices. +void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){ + UINT32 ddTempVar; + UINT16 dwDeviceId; + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid); + RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid); + RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid); + + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid); + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid); + RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid); + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid); + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid); + + ddTempVar = pStaticOptions->SataIDESsid; + if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) ) + ddTempVar = pStaticOptions->SataAHCISsid; + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); + if ((pConfig->SataClass) == RAID_MODE){ + ddTempVar = pStaticOptions->SataRAIDSsid; + if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) + ddTempVar = pStaticOptions->SataRAID5Ssid; + } + + if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) { + ddTempVar = pStaticOptions->SataAHCISsid; + } + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); +} + +void commonInitLateBoot(AMDSBCFG* pConfig){ + UINT8 dbValue; + UINT32 ddVar; + + // We need to do the following setting in late post also because some bios core pci enumeration changes these values + // programmed during early post. + // RPR 4.5 Master Latency Timer + // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40 + // Enables the PCIB to retain ownership of the bus on the + // Primary side and on the Secondary side when GNT# is deasserted. + //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h + //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h + dbValue = 0x40; + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue); + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue); + + //SB P2P AutoClock control settings. + ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow); + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar); + ddVar = (pConfig->PcibClkStopOverride); + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); + + if (pConfig->MobilePowerSavings){ + //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to + //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off. + RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4); + if (!getClockMode()){ + if (!(pConfig->UsbIntClock) ){ + //If the external clock is used, the second PLL should be shut down + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0); + // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1 + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7); + //Disable unused clocks + RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E); + } + } + writeAlink(0x30, SB_AB_REG40); + writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A); + + } + else{ + //Don't shutoff RTC clock + RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0); + //Dont disable second PLL + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); + //Enable the 25Mhz oscillator + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0); + RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00); + } +} + + +void +hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions) +{ + DESCRIPTION_HEADER* pHpetTable; + + if (pConfig->HpetTimer == 1) { + UINT8 dbTemp; + + RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7); + // Program the HPET BAR address + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase); + + // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1 + // Enable HPET MSI support only when HpetMsiDis == 0 + dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp); + // Program HPET default clock period + if (getRevisionID() >= SB700_A13) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E); + } + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + // Enable High Precision Event Timer (also called Multimedia Timer) interrupt + RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); + } + else { + if (!(pConfig->S3Resume)) { +// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH'); + pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H')); + if (pHpetTable != NULL) { +// pHpetTable->Signature = 'HPET'; + pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H'); + } + } + } +} + + +void c3PopupSetting(AMDSBCFG* pConfig){ + UINT8 dbTemp; + CPUID_DATA CpuId; + + CpuidRead (0x01, &CpuId); + //RPR 2.3 C-State and VID/FID Change + dbTemp = GetNumberOfCpuCores(); + if (dbTemp > 1){ + //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. + //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD + //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert + //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. + RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2); + } + + //SB700 needs to changed for RD790 support + //PM_IO 0x8F [4] = 0 for system with RS690 + //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. + //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. + //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB + RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5); + + //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that + //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also + //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT + //link is disconnected. + //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same + dbTemp = (IsServer())? 0x14 : 0x10; + RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp); + + //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The + //delay will allow USB DMA to go on in a continous manner + RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10); + + //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time + RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7); + +} + diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c new file mode 100644 index 0000000..130dbc4 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c @@ -0,0 +1,108 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +UINT8 isEcPresent(){ + UINT8 dbFlag; + UINT16 dwVar0; + + //Read the EC configuration register base address from LPCCfg_A4[15:1] + //Write 0x5A to the EC config index register to unlock the access + //Write 0x20 to the EC config index register to select the device ID register + //Read the value of device ID register from the EC config data register + //If the value read is 0xB7, then EC is enabled. + //Write 0xA5 to re-lock the EC config index register if EC is enabled. + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0); + dwVar0 &= 0xFFFE; + RWIO(dwVar0, AccWidthUint8, 0, 0x5A); + RWIO(dwVar0, AccWidthUint8, 0, 0x20); + ReadIO(dwVar0+1, AccWidthUint8, &dbFlag); + RWIO(dwVar0, AccWidthUint8, 0, 0xA5); + + return ( dbFlag == 0xB7); +} + +void +getSbInformation ( +SB_INFORMATION *sbInfo){ + UINT16 dwDevId; + UINT8 dbRev; + + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev); + sbInfo->sbModelMask = SB_MODEL_UNKNOWN; + if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){ + sbInfo->sbModelMask |= SB_MODEL_SB700; + sbInfo->sbModelMask |= SB_MODEL_SR5690; + sbInfo->sbRev = dbRev; + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev); + if (dbRev & 01) + sbInfo->sbModelMask |= SB_MODEL_SB750; + if (isEcPresent()) + sbInfo->sbModelMask |= SB_MODEL_SB710; + return; + } +} + + +SB_CAPABILITY_SETTING +getSbCapability ( +SB_CAPABILITY_ITEM sbCapabilityItem +) +{ + SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN; + UINT32 ddTemp0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + + if (sbCapabilityItem < Sb_Unknown_Capability) + sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03); + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + return sbCapSetting; +} + + +void +setSbCapability ( +SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting +) +{ + UINT32 ddTemp0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) ) + ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1)); + WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); +} diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h new file mode 100644 index 0000000..e737bc9 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h @@ -0,0 +1,89 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBLIB_H_ +#define _AMD_SBLIB_H_ + +//SB7xx Family +#define SB7xx_DEVICE_ID 0x4385 +#define SB700 0x00 +#define SB750 0x01 +#define SB710 0x02 + +//SB800 Family +#define SB800 0x10 + +#define SB_UNKNOWN 0xFF + +//SB700 Revision IDs +#define SB700_A11 0x39 +#define SB700_A12 0x3A +#define SB700_A13 0x3B +#define SB700_A14 0x3C + +#define SB_Rev_Sb7xx_A11 0x39 +#define SB_Rev_Sb7xx_A12 0x3A +#define SB_Rev_Sb7xx_A13 0x3B +#define SB_Rev_Sb7xx_A14 0x3C + + +typedef enum { + Sb_Raid0_1_Capability, /// + Sb_Raid5_Capability, /// + Sb_Ahci_Capability, /// + Sb_Unknown_Capability +} SB_CAPABILITY_ITEM; + + +typedef enum { + Sb_Cap_Setting_Auto, + Sb_Cap_Setting_Enabled, + Sb_Cap_Setting_Disabled, + Sb_Cap_Setting_Unknown +} SB_CAPABILITY_SETTING; + + +#define SB_MODEL_SB700 BIT0 +#define SB_MODEL_SB750 BIT1 +#define SB_MODEL_SB710 BIT2 +#define SB_MODEL_SR5690 BIT3 +#define SB_MODEL_UNKNOWN BIT31 + +typedef struct +{ + UINT32 sbModelMask; + UINT8 sbRev; +}SB_INFORMATION; + + +void getSbInformation (SB_INFORMATION *sbInfo); +SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem); +void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting); + +#endif //#ifndef _AMD_SBLIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBDEF.h b/src/vendorcode/amd/cimx/sb700/SBDEF.h new file mode 100644 index 0000000..01fc1b5 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBDEF.h @@ -0,0 +1,166 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBDEF_H_ +#define _AMD_SBDEF_H_ + +//AMD Library Routines + +UINT64 +MsrRead ( + IN UINT32 MsrAddress + ); + +VOID +MsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 Value + ); + +void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value); +void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value); +void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value); +void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value); +void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value); +void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value); +void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data); +void ReadMEM(UINT32 Address,UINT8 OpFlag, void* Value); +void WriteMEM(UINT32 Address,UINT8 OpFlag, void* Value); +void RWMEM(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +UINT32 IsFamily10(void); +UINT64 ReadMSR(UINT32 Address); +void WriteMSR(UINT32 Address,UINT64 Value); +void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value); +void* LocateImage(UINT32 Signature); +void* CheckImage( UINT32 Signature, void* ImagePtr); +void Stall(UINT32 uSec); +void Reset(void); +CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt); +void InitSerialOut(void); +void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value); +void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value); +void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); +void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value); +void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value); +void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); +void outPort80(UINT32 pcode); +UINT8 GetNumberOfCpuCores(void); +UINT8 ReadNumberOfCpuCores(void); +UINT8 GetByteSum(void* pData, UINT32 Length); +UINT32 readAlink(UINT32 Index); +void writeAlink(UINT32 Index,UINT32 Data); + +//---------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------- +void azaliaInitAfterPciEnum (AMDSBCFG* pConfig); + +void SendBytePort(UINT8 Data); +void SendStringPort(char* pstr); +void ItoA(UINT32 Value,int Radix,char* pstr); +AMDSBCFG* getConfigPointer(void); +void saveConfigPointer(AMDSBCFG* pConfig); + + +UINT32 GetFixUp(void); + +void sataInitAfterPciEnum(AMDSBCFG* pConfig); +void sataInitBeforePciEnum(AMDSBCFG* pConfig); +void sataInitLatePost(AMDSBCFG* pConfig); +void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5); +void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5); +void forceOOB(UINT32 ddBar5); +void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5); +void restrictSataCapabilities(AMDSBCFG* pConfig); + + +void commonInitEarlyBoot(AMDSBCFG* pConfig); +void commonInitEarlyPost(AMDSBCFG* pConfig); +void setRevisionID(void); +UINT8 getRevisionID(void); +UINT8 IsServer (void); +UINT8 IsLs2Mode (void); +void abLinkInitBeforePciEnum(AMDSBCFG* pConfig); +void abcfgTbl(ABTBLENTRY* pABTbl); +void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); +void commonInitLateBoot(AMDSBCFG* pConfig); +void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); +void c3PopupSetting(AMDSBCFG* pConfig); + +void sbBeforePciInit (AMDSBCFG* pConfig); +void sbAfterPciInit(AMDSBCFG* pConfig); +void sbLatePost(AMDSBCFG* pConfig); +void sbBeforePciRestoreInit(AMDSBCFG* pConfig); +void sbAfterPciRestoreInit(AMDSBCFG* pConfig); +void sbSmmAcpiOn(AMDSBCFG* pConfig); +UINT32 GetPciebase(void); +UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig); +void sbSmmService(AMDSBCFG* pConfig); +void softwareSMIservice(void); + +void sbPowerOnInit (AMDSBCFG *pConfig); +void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize); +void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize); +UINT8 getClockMode(void); +UINT16 readStrapStatus (void); + +void usbInitBeforePciEnum(AMDSBCFG* pConfig); +void usbInitAfterPciInit(AMDSBCFG* pConfig); +void usbInitMidPost(AMDSBCFG* pConfig); +void programOhciMmioForEmulation(void); + +void fcInitBeforePciEnum(AMDSBCFG* pConfig); + +unsigned char ReadIo8 (IN unsigned short Address); +unsigned short ReadIo16 (IN unsigned short Address); +unsigned int ReadIo32 (IN unsigned short Address); +void WriteIo8 (IN unsigned short Address, IN unsigned char Data); +void WriteIo16 (IN unsigned short Address, IN unsigned short Data); +void WriteIo32 (IN unsigned short Address, IN unsigned int Data); +unsigned long long ReadTSC (void); +void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data); + +#ifndef NO_EC_SUPPORT +void EnterEcConfig(void); +void ExitEcConfig(void); +void ReadEC8(UINT8 Address, UINT8* Value); +void WriteEC8(UINT8 Address, UINT8* Value); +void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask); +void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig); +void ecInitBeforePciEnum(AMDSBCFG* pConfig); +void ecInitLatePost(AMDSBCFG* pConfig); +#endif +UINT8 isEcPresent(void); + +void DispatcherEntry(void *pConfig); +AGESA_STATUS AmdSbDispatcher(void *pConfig); +void AMDFamily15CpuLdtStopReq(void); + +#endif //#ifndef _AMD_SBDEF_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c new file mode 100644 index 0000000..7468eb2 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBMAIN.c @@ -0,0 +1,289 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#ifndef B1_IMAGE + +BUILDPARAM DfltStaticOptions={ + BIOS_SIZE, // BIOS Size + LEGACY_FREE, // Legacy Free Option + 0x00, // Dummy space holder + + 0x00, // ECKbd disable/enable + 0x00, // EcChannel0 disable/enable + 0x00, // Dummy space holder1 + + SMBUS0_BASE_ADDRESS, // Smbus Base Address; + SMBUS1_BASE_ADDRESS, // Smbus Base Address; + SIO_PME_BASE_ADDRESS, // SIO PME Base Address + WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address + SPI_BASE_ADDRESS, + + PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr; + PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr; + PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr; + CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr; + GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr; + SMI_CMD_PORT, // SmiCmdPortAddr; + ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr; + + EC_LDN5_MAILBOX_ADDRESS, + EC_LDN5_IRQ, + EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address + RESERVED_VALUE, + RESERVED_VALUE, + RESERVED_VALUE, + RESERVED_VALUE, + + HPET_BASE_ADDRESS, // HPET Base address + + SATA_IDE_MODE_SSID, + SATA_RAID_MODE_SSID, + SATA_RAID5_MODE_SSID, + SATA_AHCI_SSID, + + OHCI0_SSID, + OHCI1_SSID, + EHCI0_SSID, + OHCI2_SSID, + OHCI3_SSID, + EHCI1_SSID, + OHCI4_SSID, + SMBUS_SSID, + IDE_SSID, + AZALIA_SSID, + LPC_SSID, + P2P_SSID, +}; + + +/********************************************************************************* +* +* Routine Description: Config SB Before PCI INIT +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: +* +* void +* +**********************************************************************************/ +void sbBeforePciInit (AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n")); + commonInitEarlyBoot(pConfig); + commonInitEarlyPost(pConfig); +#ifndef NO_EC_SUPPORT + ecInitBeforePciEnum(pConfig); +#endif + usbInitBeforePciEnum(pConfig); // USB POST TIME Only + fcInitBeforePciEnum(pConfig); // Preinit flash controller + sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY + programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n")); +} + + +/********************************************************************************* +* +* Routine Description: Config SB After PCI INIT +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: atiSbAfterPciInit +* +**********************************************************************************/ +void sbAfterPciInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n")); + + pStaticOptions = &pConfig->BuildParameters; + usbInitMidPost(pConfig); //usb initialization which is required only during post + usbInitAfterPciInit(pConfig); // Init USB MMIO + sataInitAfterPciEnum(pConfig); // SATA port enumeration + azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n")); +} + + +/********************************************************************************* +* +* Routine Description: Config SB during late POST +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: atiSbLatePost +* +**********************************************************************************/ +void sbLatePost(AMDSBCFG* pConfig){ + UINT16 dwVar; + BUILDPARAM *pStaticOptions; + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n")); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar); + if (dwVar != SB7XX_DEVICE_ID){ + // Display message that the SB is wrong and stop the system + TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n")); + for(;;); + } + commonInitLateBoot(pConfig); + sataInitLatePost(pConfig); + hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit +#ifndef NO_EC_SUPPORT + ecInitLatePost(pConfig); +#endif +} + +/********************************************************************************* +* +* Routine Description: Config SB before ACPI S3 resume PCI config device restore +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: AtiSbBfPciRestore +* +**********************************************************************************/ +void sbBeforePciRestoreInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n")); + + pConfig->S3Resume = 1; + + pStaticOptions = &pConfig->BuildParameters; + commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB + abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers + usbInitBeforePciEnum(pConfig); // USB POST TIME Only + fcInitBeforePciEnum(pConfig); // Preinit flash controller + sataInitBeforePciEnum(pConfig); + programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID +} + + +/********************************************************************************* +* +* Routine Description: Config SB after ACPI S3 resume PCI config device restore +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: AtiSbAfPciRestore +* +**********************************************************************************/ +void sbAfterPciRestoreInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + pConfig->S3Resume = 1; + + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n")); + + commonInitLateBoot(pConfig); + sataInitAfterPciEnum(pConfig); + azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio + hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit + sataInitLatePost(pConfig); + sbSmmAcpiOn(pConfig); +} + + +/*++ + +Routine Description: + + SB config hook during ACPI_ON + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ + +void sbSmmAcpiOn(AMDSBCFG* pConfig){ + UINT32 ddBar5; + UINT8 dbPort; + + //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); + if (getRevisionID() >= SB700_A13) + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0); + programOhciMmioForEmulation(); + + // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ + for (dbPort = 0; dbPort <= 5; dbPort++) { + RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF); + } + } +} + + +UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){ + UINT32 Result=0; + TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data)); + if (pConfig->StdHeader.pCallBack==NULL) + return Result; + Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig); + TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result)); + return Result; +} + +#endif diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c new file mode 100644 index 0000000..6c5740b --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c @@ -0,0 +1,441 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +REG8MASK sbPorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REGD0+2, 0x00, 0x01}, + {SB_SMBUS_REG40, 0x00, 0x44}, + {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control. + {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU + {SB_SMBUS_REG64+1, 0x00, 0x78}, + {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E}, + {SB_SMBUS_REG64+3, 0x0F, 0x02}, + {SB_SMBUS_REG68+1, 0x00, 0x90}, + {SB_SMBUS_REG6C, 0x00, 0x20}, + {SB_SMBUS_REG78, 0x00, 0xFF}, + {SB_SMBUS_REG04, 0x00, 0x07}, + {SB_SMBUS_REG04+1, 0x00, 0x04}, + {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control" + {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1}, + {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB + // can request SMI# to be sent out early before IO completion. + // Some applications may have problems with this feature. The BIOS should set this bit + // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1. + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG40, 0x00, 0x04}, + {SB_LPC_REG48, 0x00, 0x07}, + {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h. + {SB_LPC_REG78, ~(UINT8)BIT0, 0x00}, + {SB_LPC_REG7C, 0x00, 0x05}, + {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus" + {0xFF, 0xFF, 0xFF}, + + // P2P Bridge(Bus 0, Dev 20, Func 4) + {0x00, SBP2P_BUS_DEV_FUN, 0}, + {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access + {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4}, + {SB_P2P_REG1C, 0x00, 0x11}, + {SB_P2P_REG1D, 0x00, 0x11}, + {SB_P2P_REG04, 0x00, 0x21}, + {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbA13PorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. + {SB_SMBUS_REG38, (UINT8)~BIT7, 00}, + {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode + {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbA14PorInitPciTable[] = { + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00}, + {0xFF, 0xFF, 0xFF}, +}; + +REG8MASK sbPorPmioInitTbl[] = { + // index andmask ormask + {SB_PMIO_REG67, 0xFF, 0x02}, + {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge + {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP + {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker + {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB + {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety + {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset + {SB_PMIO_REGB2, 0xFF, BIT7}, + {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding + {SB_PMIO_REGD7, 0xF6, 0x80}, + {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register + + {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown + {SB_PMIO_REG52, 0xC0, 0x08}, + + {SB_PMIO_REG8B, 0x00, 0x10}, + {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms +}; + +REG8MASK sbA13PorPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly) + {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly) + // Always clear [7] to begin with SP5100 C1e disabled + +// {SB_PMIO_REG65, 0xFF, BIT7}, +// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown +// {SB_PMIO_REG52, 0xC0, 0x02}, + +}; + + +void sbPowerOnInit (AMDSBCFG *pConfig){ + UINT8 dbVar0, dbVar1, dbValue; + UINT16 dwTempVar; + BUILDPARAM *pBuildOptPtr; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n")); + + setRevisionID(); + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar); + if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID) + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01); + + // Set A-Link bridge access address. This address is set at device 14h, function 0, + // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry. + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); + + writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access + writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. + writeAlink(0x34, readAlink(0x34) | BIT9); + + if (!(pConfig->ResetCpuOnSyncFlood)){ + //Enable reset on sync flood + writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)), + (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) )); + } + + pBuildOptPtr = &(pConfig->BuildParameters); + + WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) ); + + dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0; + if( dwTempVar != 0 ){ + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0)); + // Disable ASF Slave controller on SB700 rev A15. + if (getRevisionID() == SB700_A15) { + RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6); + } + } + + WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress)); + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress)); + + WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr)); + WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr)); + WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr)); + WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr)); + WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr)); + WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr)); + WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr)); + RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8); + WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase)); + + //Program power on pci init table + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) ); + //Program power on pmio init table + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) ); + + dbValue = 0x00; + ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); + dbValue &= 0xF3; + WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); + + dbValue = 0x0A; + WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + dbValue &= 0xEF; + WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + + + if (getRevisionID() >= SB700_A13){ + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) ); + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) ); + } + + if ((getRevisionID() >= SB700_A14) ) + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) ); + + if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){ + ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1); + if (!(dbVar1 & BIT6)){ + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6); + pConfig->RebootRequired=1; + } + } + + if (getRevisionID() > SB700_A11) { + if (pConfig->PciClk5 == 1) + RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12 + } + + dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7; + if (dbVar0 > 4) { + dbVar0 = 0; + } + //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); + + if (pConfig->Spi33Mhz) + //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios + RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12); + + //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed + //from the existing value. + ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0); + if (pConfig->SpreadSpectrum != (dbVar0 >> 7) ) + pConfig->RebootRequired = 1; + if (pConfig->SpreadSpectrum) + RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7); + else + RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0); + + if ( !(pConfig->S3Resume) ){ + //To detect whether internal clock chip is used, do the following procedure + //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode. + //if it is 0, we are using clock chip on board. + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + + //Do the following programming only for SB700-A11. + //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values. + //2. Set PMIO_B2 [7]=0 + //3. Write the saved values from step 1, back to B0 and B1. + //4. Set PMIO_B2 [6]=1. + ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); + if (getRevisionID() == SB700_A11){ + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00); + WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6); + } + + if (!(dwTempVar & BIT4)){ + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2 + + //we are in external clock chip on the board + if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ + //Configure usb clock to come from internal PLL + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 + } + else{ + //Configure usb clock to come from external clock + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2 + } + } + else{ + //we are using internal clock chip on this board + if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ + //Configure usb clock to come from internal PLL + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 + } + else{ + //Configure usb clock to come from external clock + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2 + } + } + + ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0); + RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5)); + //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot. + if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1; + } + + if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); + else + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); + + if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){ + RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7); + RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0); + RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1); + } + + if (getRevisionID() >= SB700_A15) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); + //Enable unconditional shutdown fix in A15 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0); + } + + // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled + if (isEcPresent()) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5); + } + + //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement + // to program VID/FID LDTSTP# duration selection register + AMDFamily15CpuLdtStopReq(); + +#ifndef NO_EC_SUPPORT + ecPowerOnInit(pBuildOptPtr, pConfig); +#endif +} + + +void setRevisionID(void){ + UINT8 dbVar0, dbVar1; + + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); + ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1); + if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){ + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0); + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12); + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00); + } + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); +} + + +UINT8 getRevisionID(void){ + UINT8 dbVar0; + + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); + return dbVar0; +} + + +void AMDFamily15CpuLdtStopReq(void) { + CPUID_DATA CpuId; + CPUID_DATA CpuId_Brand; + UINT8 dbVar0, dbVar1, dbVar2; + + //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement + //to program VID/FID LDTSTP# duration selection register + //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us: + // 1. Any link in the system operating at a Gen 1 Frequency. + // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) + + CpuidRead (0x01, &CpuId); + CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type + if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) { + + //Program to Gen 3 default value - 001b + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b + + //Any link in the system operating at a Gen 1 Frequency. + //Check Link 0 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + + if(dbVar2 == 0x01) { + //Check Link 0 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 1 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 1 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 2 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 2 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 3 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 3 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) + if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + +} + diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h new file mode 100644 index 0000000..faeae5d --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -0,0 +1,249 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBTYPE_H_ +#define _AMD_SBTYPE_H_ + +#pragma pack(push,1) + +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef void (*SMM_SERVICE_ROUTINE) (void); + +typedef struct _STDCFG{ + UINT32 pImageBase; + UINT32 pPcieBase; + UINT8 Func; + CIM_HOOK_ENTRY pCallBack; + UINT32 pB2ImageBase; +}STDCFG; //Size of stdcfg is 17 bytes + +typedef struct _BUILDPARAM +{ + UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved + UINT16 LegacyFree:1; + UINT16 Dummy0:12; + + UINT16 EcKbd:1; + UINT16 EcChannel0:1; + UINT16 Dummy1:14; + + UINT32 Smbus0BaseAddress; + UINT16 Smbus1BaseAddress; + UINT32 SioPmeBaseAddress; + UINT32 WatchDogTimerBase; + UINT32 SpiRomBaseAddress; + + UINT16 AcpiPm1EvtBlkAddr; + UINT16 AcpiPm1CntBlkAddr; + UINT16 AcpiPmTmrBlkAddr; + UINT16 CpuControlBlkAddr; + UINT16 AcpiGpe0BlkAddr; + UINT16 SmiCmdPortAddr; + UINT16 AcpiPmaCntBlkAddr; + + UINT16 EcLdn5MailBoxAddr; + UINT8 EcLdn5Irq; + UINT16 EcLdn9MailBoxAddr; + UINT32 ReservedDword0; + UINT32 ReservedDword1; + UINT32 ReservedDword2; + UINT32 ReservedDword3; + + UINT32 HpetBase; //HPET Base address + + UINT32 SataIDESsid; + UINT32 SataRAIDSsid; + UINT32 SataRAID5Ssid; + UINT32 SataAHCISsid; + + UINT32 Ohci0Ssid; + UINT32 Ohci1Ssid; + UINT32 Ehci0Ssid; + UINT32 Ohci2Ssid; + UINT32 Ohci3Ssid; + UINT32 Ehci1Ssid; + UINT32 Ohci4Ssid; + UINT32 SmbusSsid; + UINT32 IdeSsid; + UINT32 AzaliaSsid; + UINT32 LpcSsid; + UINT32 P2PSsid; +}BUILDPARAM; + +typedef struct _CODECENTRY{ + UINT8 Nid; + UINT32 Byte40; +}CODECENTRY; + +typedef struct _CODECTBLLIST{ + UINT32 CodecID; + CODECENTRY* CodecTablePtr; +}CODECTBLLIST; + +typedef struct _AMDSBCFG +{ + STDCFG StdHeader; //offset 0:16 - 17 bytes + //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes + UINT32 S3Resume:1; + UINT32 RebootRequired:1; + UINT32 Spi33Mhz:1; + UINT32 SpreadSpectrum:1; + UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock + UINT32 PciClk5:1; //0:disable, 1:enable + UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12, + //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz + //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100 + UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood + UINT32 MsgXchgBiosCimxDummyBB:23; + + /** BuildParameters - The STATIC platform information for CIMx Module. */ + BUILDPARAM BuildParameters; + + //SATA Configuration + UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes + UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI + UINT32 SataSmbus :1; //4, 0:disable 1:enable* + UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON + UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON + UINT32 SataReserved :2; //8:7, Reserved + UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled + UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled + UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary + UINT32 SataReserved1 :6; //17:12, Not used currently + UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:) + UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode + UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port + UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled + + //Flash Configuration //offset 29:30 - 2 bytes + UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE + UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone + UINT16 FlashHcCrc:1; //2, + UINT16 FlashErrorMode:1; //3 + UINT16 FlashNumOfBankMode:1; //4 + UINT16 FlashDummy:11; //5:15 + + //USB Configuration //offset 31:32 - 2 bytes + UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0 + UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1 + UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2 + UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0 + UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1 + UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2 + UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5 + UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled + UINT16 UsbDummy :8; //8:15 + + //Azalia Configuration //offset 33:36 - 4 bytes + UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable + UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable + UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable + UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected + UINT32 AzaliaSdin0 :2; //6 + UINT32 AzaliaSdin1 :2; //8 + UINT32 AzaliaSdin2 :2; //10 + UINT32 AzaliaSdin3 :2; //12 + UINT32 AzaliaDummy :18; //14:31 + + CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes + UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes + + //Miscellaneous Configuration //offset 45:48 - 4 bytes + UINT32 MiscReserved0:1; //0 + UINT32 HpetTimer:1; //1, 0:disable 1:enable + UINT32 PciClks:5; //2:6, 0:disable, 1:enable + UINT32 MiscReserved1:3; //9:7, Reserved + UINT32 IdeController:1; //10, 0:Enable, 1:Disabled + UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform + UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock + UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported + UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform + UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled + UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled + UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable + UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */ + UINT32 MiscDummy:13; + + UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes + UINT32 AsmAslInfoExchange1; //offset 53:56 + + //DebugOptions_1 //offset 57:60 + UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode + UINT32 UsbPhyPowerDown :1; //1 + UINT32 PcibClkStopOverride :10; //11:2 + UINT32 Debug1Reserved0:4; //15:11 + UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable + UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability + UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1 + UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable + UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO + UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable + UINT32 Debug1Dummy:3; // + + //DebugOptions_2 + UINT32 PcibAutoClkCtrlLow:16; + UINT32 PcibAutoClkCtrlHigh:16; + + //TempMMIO + UINT32 TempMMIO:32; + +}AMDSBCFG; + +typedef struct _SMMSERVICESTRUC +{ + UINT8 enableRegNum; + UINT8 enableBit; + UINT8 statusRegNum; + UINT8 statusBit; + CHAR8 *debugMessage; + SMM_SERVICE_ROUTINE serviceRoutine; +}SMMSERVICESTRUC; + +typedef struct _ABTblEntry +{ + UINT8 regType; + UINT32 regIndex; + UINT32 regMask; + UINT32 regData; +}ABTBLENTRY; + +#define PCI_ADDRESS(bus,dev,func,reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +typedef UINT32 CIM_STATUS; +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 + +#pragma pack(pop) + +#define CIMX_OPTION_DISABLED 0 +#define CIMX_OPTION_ENABLED 1 + +#endif // _AMD_SBTYPE_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c new file mode 100644 index 0000000..0d752fb --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SMM.c @@ -0,0 +1,91 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +SMMSERVICESTRUC smmItemsTable[]={ + {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice}, + {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL}, + {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL}, + {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL}, + {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL}, + {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL}, + {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL}, +}; + + +/*++ + +Routine Description: + + SB SMI service + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ + +void sbSmmService(AMDSBCFG* pConfig){ + UINT8 i, dbEnableValue, dbStatusValue; + SMMSERVICESTRUC *pSmmItems; + SMM_SERVICE_ROUTINE serviceRoutine; + + pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]); + TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n")); + for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){ + dbEnableValue = pSmmItems->enableRegNum; + ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue); + ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue); + if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){ + TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage)); + TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue)); + TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue)); + if ( (pSmmItems->serviceRoutine)!= NULL){ + serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine); + serviceRoutine(); + } + } + } + TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n")); +} + + +void softwareSMIservice(void){ + UINT16 dwSmiCmdPort, dwVar; + ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort); + ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar); + TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar)); +} diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c new file mode 100644 index 0000000..9c5e7b3 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/USB.c @@ -0,0 +1,187 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +void usbInitBeforePciEnum(AMDSBCFG* pConfig){ + UINT8 dbVar=0; + + TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n")); + if (pConfig->Usb1Ohci0){ + dbVar = (pConfig->Usb1Ehci << 2); + dbVar |= ((pConfig->Usb1Ohci0) << 0); + dbVar |= ((pConfig->Usb1Ohci1) << 1); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar ); + } + if (pConfig->Usb2Ohci0){ + dbVar = (pConfig->Usb2Ehci << 6) ; + dbVar |= ((pConfig->Usb2Ohci0) << 4); + dbVar |= ((pConfig->Usb2Ohci1) << 5); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar ); + } + if (pConfig->Usb3Ohci) + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) ); + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4); +} + + +void usbInitAfterPciInit(AMDSBCFG* pConfig){ + UINT32 ddBarAddress, ddVar; + + ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD + //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + //RPR - EHCI dynamic clock gating feature + //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. + // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); + } + + ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD + //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + //RPR - EHCI dynamic clock gating feature + //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. + // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); + } + + if (pConfig->UsbPhyPowerDown) + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0); + else + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + + // Disable the MSI capability of USB host controllers + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE" + //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux. + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + //RPR recommended setting "EHCI Async Park Mode" + //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support" + // RPR recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); + + //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[16] = 1 + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + if (getRevisionID() >= SB700_A14){ + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25); + } + + if (getRevisionID() >= SB700_A15) { + //USB PID Error checking + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); + } + + // RPR 6.25 - Optionally disable OHCI isochronous out prefetch + if (pConfig->OhciIsoOutPrefetchDis) { + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + } + + if ( pConfig->EhciDataCacheDis ) { + // Disable Async Data Cache, EHCI_pci_configx50[26]='1' + RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); + RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); + } +} + + +void usbInitMidPost(AMDSBCFG* pConfig){ + if (pConfig->UsbOhciLegacyEmulation == 0){ + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + } + else{ + programOhciMmioForEmulation(); + } +} + + +void programOhciMmioForEmulation(void){ + UINT32 ddBarAddress; + + ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + ddBarAddress &= 0xFFFFF000; + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } + + ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + ddBarAddress &= 0xFFFFF000; + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } + + ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } +} diff --git a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h new file mode 100644 index 0000000..e8f6b38 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h @@ -0,0 +1,196 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_AMDLIB_H_ +#define _AMD_AMDLIB_H_ + +typedef CHAR8 *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start +#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) ) +#endif +#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + +#ifndef CIMx_DEBUG + #define CIMx_DEBUG 0 +#endif + + +#pragma pack(push,1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY)(void* pConfig); + +//Hook Call + +typedef struct _Reg8Mask +{ + UINT8 bRegIndex; + UINT8 bANDMask; + UINT8 bORMask; +}REG8MASK; + + +typedef struct _CIMFILEHEADER{ + UINT32 AtiLogo; + UINT32 EntryPoint; + UINT32 ModuleLogo; + UINT32 ImageSize; + UINT16 Version; + UINT8 CheckSum; + UINT8 Reserved1; + UINT32 Reserved2; +}CIMFILEHEADER; + +typedef struct _CPUID_DATA{ + UINT32 REG_EAX; + UINT32 REG_EBX; + UINT32 REG_ECX; + UINT32 REG_EDX; +}CPUID_DATA; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#define PCI_ADDRESS(bus,dev,func,reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +#pragma pack(pop) + +typedef enum { + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +#endif //#ifndef _AMD_AMDLIB_H_ From gerrit at coreboot.org Wed Feb 1 06:13:47 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:47 +0100 Subject: [coreboot] Patch set updated for coreboot: 4b5a0b1 RD890: AMD RD890/SR56X0 CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit 4b5a0b16088db08659d5d7176b33977f7538b5f6 Author: Kerry Sheh Date: Wed Feb 1 13:55:12 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 269 +++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1171 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..5eaefd1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include + +#include "amd.h" //cimx typedef +#include +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; /// + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..62a842a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rx780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RX780_HT, +}; + +static const struct pci_driver ht_driver_rd780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD780_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ + From gerrit at coreboot.org Wed Feb 1 06:13:48 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:48 +0100 Subject: [coreboot] Patch set updated for coreboot: c298afa HWM: Nuvoton W83795G/ADG HWM support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569 -gerrit commit c298afadb883e6738cca4feca92e18e32a0ee335 Author: Kerry Sheh Date: Wed Feb 1 13:59:31 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/supermicro/h8qgi/Makefile.inc | 1 + src/mainboard/supermicro/h8qgi/romstage.c | 9 + src/mainboard/supermicro/h8qgi/w83795.c | 236 +++++++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/w83795.h | 75 +++++++++ 4 files changed, 321 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index 82264a4..ef81caf 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += w83795.c romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 119593e..4d48474 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -33,6 +33,7 @@ #include #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" +#include "w83795.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ @@ -119,6 +120,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); + w83627dhg_enable_serial(PNP_DEV(0x2E, W83627DHG_SP1), CONFIG_TTYS0_BASE); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ diff --git a/src/mainboard/supermicro/h8qgi/w83795.c b/src/mainboard/supermicro/h8qgi/w83795.c new file mode 100644 index 0000000..22828db --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/w83795.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include "w83795.h" + +static u32 w83795_set_bank(u8 bank) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); +} + +static u8 w83795_read(u16 reg) +{ + u32 ret; + + ret = w83795_set_bank(reg >> 8); + if (ret < 0) { + printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8); + return -1; + } + + ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff); + return ret; +} + +static u8 w83795_write(u16 reg, u8 value) +{ + u32 err; + + err = w83795_set_bank(reg >> 8); + if (err < 0) { + printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8); + return -1; + } + + err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value); + return err; +} + +#if 0 +static void w83795_set_speed(void) +{ + +} + +static void w83795_set_ttti(void)//KR it works +{ + u32 i; + for (i = 0; i < 6; i++) { + //w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40 + //w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80 + } +} +#endif + +/* + * Enable Digital Temperature Sensor + */ +static void w83795_dts_enable(u8 dts_src) +{ + u8 val; + + /* DIS */ + val = w83795_read(W83795_REG_DTSC); + val |= (dts_src & 0x01); + w83795_write(W83795_REG_DTSC, val); + + /* DTSE */ + val = w83795_read(W83795_REG_DTSE); + val |= 0xFF; + w83795_write(W83795_REG_DTSE, val); + + /* store bank3 regs first before enable DTS */ + + /* + * TD/TR1-4 termal diode by default + * 0x00 Disable + * 0x01 thermistors on motherboard + * 0x10 different mode voltage + * 0x11 CPU internal thermal diode output + * + * TR5-6 thermistors by default TRn + */ + val = 0x55; /* thermal diode */ + w83795_write(W83795_REG_TEMP_CTRL2, val); + + /* Enable Digital Temperature Sensor */ + val = w83795_read(W83795_REG_TEMP_CTRL1); + val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */ + w83795_write(W83795_REG_TEMP_CTRL1, val); +} + +static void w83795_set_tfmr(w83795_fan_mode_t mode) +{ + u8 val; + u8 i; + + if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) { + val = 0xFF; + } else { + val = 0x00; + } + + for (i = 0; i < 6; i++) + w83795_write(W83795_REG_TFMR(i), val); +} + +static u32 w83795_set_fan_mode(w83795_fan_mode_t mode) +{ + if (mode == SPEED_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS1, 0xFF); + printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n"); + } else { + w83795_write(W83795_REG_FCMS1, 0x00); + if (mode == THERMAL_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS2, 0x00); + printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n"); + } else if (mode == SMART_FAN_MODE) { + w83795_write(W83795_REG_FCMS2, 0x3F); + printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n"); + } else { + printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n"); + return -1; + } + } + + return 0; +} + +static void w83795_set_tss(void) +{ + u8 val; + + val = 0x00; + w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */ + w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */ + w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */ +} + +static void w83795_set_fan(w83795_fan_mode_t mode) +{ + u8 i; + + /* select temperature sensor (TSS)*/ + w83795_set_tss(); + + /* select Temperature to Fan mapping Relationships (TFMR)*/ + w83795_set_tfmr(mode); + + /* set fan output controlled mode (FCMS)*/ + w83795_set_fan_mode(mode); + + /* Set Critical Temperature to Full Speed all fan (CTFS) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */ + } + + if (mode == THERMAL_CRUISE_MODE) { + /* Set Target Temperature of Temperature Inputs (TTTI) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */ + } + } else if (mode == SMART_FAN_MODE) { + /* Set the Relative Register-at SMART FAN IV Control Mode Table */ + //SFIV TODO + } + + /* Set Hystersis of Temperature (HT) */ +} + +void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +{ + u8 i; + u8 val; + + if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + printk(BIOS_INFO, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } + val = w83795_read(W83795_REG_CONFIG); + if ((val & W83795_REG_CONFIG_CONFIG48) == 0) + printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); + else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); + + /* Reset */ + val |= W83795_REG_CONFIG_INIT; + w83795_write(W83795_REG_CONFIG, val); + + /* Fan monitoring setting */ + val = 0xFF; /* FAN1-FAN8 */ + w83795_write(W83795_REG_FANIN_CTRL1, val); + val = 0x3F; /* FAN9-FAN14 */ + w83795_write(W83795_REG_FANIN_CTRL2, val); + + /* enable monitoring operations */ + val = w83795_read(W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(W83795_REG_CONFIG, val); + + w83795_dts_enable(dts_src); + w83795_set_fan(mode); + + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + for (i = 0; i < 6; i++) { + val = w83795_read(W83795_REG_CTFS(i)); + printk(BIOS_INFO, " %x %d", i, val); + val = w83795_read(W83795_REG_TTTI(i)); + printk(BIOS_INFO, " %d\n", val); + } + + /* Temperature ReadOut */ + for (i = 0; i < 9; i++) { + val = w83795_read(W83795_REG_DTS(i)); + printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val); + } +} + diff --git a/src/mainboard/supermicro/h8qgi/w83795.h b/src/mainboard/supermicro/h8qgi/w83795.h new file mode 100644 index 0000000..abc4d62 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/w83795.h @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _W83795_H_ +#define _W83795_H_ + +#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ + +#define W83795_REG_I2C_ADDR 0xFC +#define W83795_REG_BANKSEL 0x00 +#define W83795_REG_CONFIG 0x01 +#define W83795_REG_CONFIG_START 0x01 +#define W83795_REG_CONFIG_CONFIG48 0x04 +#define W83795_REG_CONFIG_INIT 0x80 + +#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ +#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ +#define W83795_REG_FANIN_CTRL1 0x06 +#define W83795_REG_FANIN_CTRL2 0x07 +#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ +#define DTS_SRC_INTEL_PECI (0 << 0) +#define DTS_SRC_AMD_SBTSI (1 << 0) + +#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ +#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ +#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ +#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ +#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ + +#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ +#define W83795_REG_DTS(n) (0x26 + (n)) +#define W83795_REG_VRLSB 0x3C + +#define W83795_TEMP_REG_TR1 0x21 +#define W83795_TEMP_REG_TR2 0x22 +#define W83795_TEMP_REG_TR3 0x23 +#define W83795_TEMP_REG_TR4 0x24 +#define W83795_TEMP_REG_TR5 0x1F +#define W83795_TEMP_REG_TR6 0x20 + +#define W83795_REG_FCMS1 0x201 +#define W83795_REG_FCMS2 0x208 +#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ +#define W83795_REG_DFSP 0x20C + +#define W83795_REG_FTSH(n) (0x240 + (n) * 2) +#define W83795_REG_FTSL(n) (0x241 + (n) * 2) +#define W83795_REG_TFTS 0x250 + +typedef enum w83795_fan_mode { + SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range + THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI + SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed + MANUAL_MODE, ///< control manually +} w83795_fan_mode_t; + +void w83795_init(w83795_fan_mode_t mode, u8 dts_src); + +#endif From gerrit at coreboot.org Wed Feb 1 06:13:49 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 06:13:49 +0100 Subject: [coreboot] Patch set updated for coreboot: 924ba67 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568 -gerrit commit 924ba67980e3674deca16d39b960198357ebabbc Author: Kerry Sheh Date: Wed Feb 1 13:59:30 2012 +0800 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. For mainboard using AMD AGESA framework, lots of AGESA code will be compiled into romstage, so romstage becomes larger, especially for mainboard support 2 or more processor families. H8QGI support both f10 and f15 CPUs, 512K default xip size is not enough, so increase to 1M Bytes. Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/supermicro/h8qgi/Kconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..201df45 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -123,5 +123,19 @@ config VGA_BIOS_ID depends on VGA_BIOS default "102b,0532" +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 kinds of processor family, + Compiling 2 cpu families agesa code will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + endif # BOARD_SUPERMICRO_H8QGI From gerrit at coreboot.org Wed Feb 1 11:50:16 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Wed, 1 Feb 2012 11:50:16 +0100 Subject: [coreboot] New patch to review for coreboot: f81d7bd i3100: configure pci irqs References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/603 -gerrit commit f81d7bd250944c585a0cdcdf614f4ba4878b22db Author: Sven Schnelle Date: Wed Feb 1 11:47:29 2012 +0100 i3100: configure pci irqs without it, you can't boot from PCI devices like scsi controllers which require an interrupt set. So preconfigure all pci devices. Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194 Signed-off-by: Sven Schnelle --- src/southbridge/intel/i3100/lpc.c | 46 +++++++++++++++++++++++++++++++++--- 1 files changed, 42 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 1544ecd..2dcdb04 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include "i3100.h" @@ -196,17 +197,51 @@ static void set_i3100_gpio_inv( static void i3100_pirq_init(device_t dev) { + device_t irq_dev; config_t *config; /* Get the chip configuration */ config = dev->chip_info; - if(config->pirq_a_d) { + if(config->pirq_a_d) pci_write_config32(dev, 0x60, config->pirq_a_d); - } - if(config->pirq_e_h) { + + if(config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - } + + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + switch (int_pin) { + case 1: /* INTA# */ + int_line = config->pirq_a_d & 0xff; + break; + + case 2: /* INTB# */ + int_line = (config->pirq_a_d >> 8) & 0xff; + break; + + case 3: /* INTC# */ + int_line = (config->pirq_a_d >> 16) & 0xff; + break; + + case 4: /* INTD# */ + int_line = (config->pirq_a_d >> 24) & 0xff; + break; + } + + if (!int_line) + continue; + + printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } + + } static void i3100_power_options(device_t dev) { @@ -343,6 +378,9 @@ static void lpc_init(struct device *dev) /* Initialize isa dma */ isa_dma_init(); + + setup_i8259(); + i8259_configure_irq_trigger(9, 1); } static void i3100_lpc_read_resources(device_t dev) From gerrit at coreboot.org Wed Feb 1 11:51:53 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 11:51:53 +0100 Subject: [coreboot] Patch set updated for coreboot: f301c1b Mainboard: Supermicro/h8qgi mainboard update References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567 -gerrit commit f301c1ba962ca7f87190ae10d1af654583e4cf39 Author: Kerry Sheh Date: Wed Feb 1 16:05:47 2012 +0800 Mainboard: Supermicro/h8qgi mainboard update 1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 2 +- src/mainboard/supermicro/h8qgi/Kconfig | 20 +- src/mainboard/supermicro/h8qgi/Makefile.inc | 18 ++- src/mainboard/supermicro/h8qgi/OptionsIds.h | 2 +- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/ide.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/routing.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/sata.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/usb.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi_tables.c | 95 +++++--- src/mainboard/supermicro/h8qgi/agesawrapper.c | 147 ++++++++----- src/mainboard/supermicro/h8qgi/agesawrapper.h | 2 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 124 +++++++++-- src/mainboard/supermicro/h8qgi/chip.h | 2 +- src/mainboard/supermicro/h8qgi/cmos.layout | 2 +- src/mainboard/supermicro/h8qgi/devicetree.cb | 86 ++------ src/mainboard/supermicro/h8qgi/dimmSpd.c | 85 ++++---- src/mainboard/supermicro/h8qgi/dsdt.asl | 217 +++++++----------- src/mainboard/supermicro/h8qgi/fadt.c | 61 ++---- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 30 +-- src/mainboard/supermicro/h8qgi/irq_tables.c | 8 +- src/mainboard/supermicro/h8qgi/mainboard.c | 40 +++-- src/mainboard/supermicro/h8qgi/mptable.c | 59 +++--- src/mainboard/supermicro/h8qgi/platform_cfg.h | 54 +++++ src/mainboard/supermicro/h8qgi/platform_oem.c | 4 +- src/mainboard/supermicro/h8qgi/platform_oem.h | 29 --- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 274 +++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/rd890_cfg.h | 174 ++++++++++++++ src/mainboard/supermicro/h8qgi/reset.c | 66 ++++++ src/mainboard/supermicro/h8qgi/romstage.c | 79 +++++-- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 142 ++++++++++++ src/mainboard/supermicro/h8qgi/sb700_cfg.h | 237 ++++++++++++++++++++ 33 files changed, 1524 insertions(+), 547 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index b7f0124..e83d1f0 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h index 24a05fb..aa2d451 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig old mode 100755 new mode 100644 index 5df0bb4..e900ea8 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select CPU_AMD_AGESA_FAMILY10 - select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX - select NORTHBRIDGE_AMD_AGESA_FAMILY10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_HARD_RESET select SERIAL_CPU_INIT - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 + select TINY_BOOTBLOCK #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default supermicro/h8qgi diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc old mode 100755 new mode 100644 index b09c5ca..82264a4 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,15 +17,31 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c +ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += platform_oem.c +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx +AGESA_ROOT ?= $(AGESA_PREFIX)/f15 +NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890 +SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700 + +subdirs-y += ../../../../$(AGESA_ROOT) +#subdirs-y += ../../../../$(NB_CIMX_ROOT) +#subdirs-y += ../../../../$(SB_CIMX_ROOT) + diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h index eb756df..c4441e9 100644 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl old mode 100755 new mode 100644 index 5eca9cc..2cb7aeb --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl old mode 100755 new mode 100644 index c79c18c..45303c0 --- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl old mode 100755 new mode 100644 index 8bc06f6..817f0f7 --- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl old mode 100755 new mode 100644 index bd4acf0..9ce8650 --- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl old mode 100755 new mode 100644 index 81ea9a2..099e7ac --- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index b8ce0b0..7314283 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end) #endif extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) #else apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif - apicid_sr5650 = apicid_sp5100 + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -89,18 +89,18 @@ unsigned long acpi_fill_madt(unsigned long current) 0 ); - /* IOAPIC on rs5690 */ - gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, dword, gsi_base ); - } + } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, //BUS @@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - //acpi_header_t *ssdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - /* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */ -#ifdef UNUSED_CODE - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); ssdt = (acpi_header_t *) current; - current += ssdt->length; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } - else { + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #endif - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 5bb4a9d..dbdd9d7 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,7 +34,6 @@ #include "Dispatcher.h" #include "cpuCacheInit.h" #include "amdlib.h" -#include "platform_oem.h" #include "Filecode.h" #include "heapManager.h" #include /* CPU_SPECIFIC_SERVICES */ @@ -54,7 +53,7 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -//VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL; /*---------------------------------------------------------------------------------------- @@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); static UINT32 agesawrapper_amdinitcpuio(VOID) { @@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) UINT32 node; UINT32 sblink; UINT32 i; + UINT32 TOM; /* get the number of coherent nodes in the system */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); @@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) PciData = 0x00000A03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set F0000000-FFFFFFFF to Node0 sbLink. */ + /* Set TOM1-FFFFFFFF to Node0 sbLink. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); PciData = 0x00FFFF00; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciData = 0x00F00000 | 0x03; + TOM = (UINT32)MsrRead(TOP_MEM); + PciData = (TOM >> 8) | 0x03; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */ + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x0000E000; + PciData = 0x00FFF000; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00009033; + PciData = 0x00000033; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800; + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; @@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID) AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdResetParams.HtConfig.Depth = 0; //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default @@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly(AmdEarlyParamsPtr); - status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + status = AmdInitEarly(AmdEarlyParamsPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID) UINT16 i; UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr; UINT32 TscRateInMhz; CPU_SPECIFIC_SERVICES *FamilySpecificServices; @@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + if (status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + } AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID) BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParams; LibAmdMemFill(&AmdParamStruct, 0, @@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitEnv(EnvParams); if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return (UINT32)status; @@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick) return AcpiWheaMce; case PICK_WHEA_CMC: return AcpiWheaCmc; -/* case PICK_ALIB: return AcpiAlib; -*/ default: return NULL; } @@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); @@ -405,34 +426,49 @@ UINT32 agesawrapper_amdinitmid(VOID) UINT32 agesawrapper_amdinitlate(VOID) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - Status = AmdInitLate(&AmdLateParams); + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); ASSERT(Status == AGESA_SUCCESS); } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - //AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } @@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr) ASSERT(Status <= AGESA_UNSUPPORTED); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - // AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } @@ -784,9 +811,9 @@ static void agesa_error(EVENT_PARAMS *event) printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); break; - case MEM_ERROR_ECC_DIS: - printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); - break; +// case MEM_ERROR_ECC_DIS: +// printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); +// break; case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); @@ -1141,6 +1168,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) */ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) { + printk(BIOS_DEBUG, "enter in %s\n", __func__); AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; @@ -1164,6 +1192,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } + printk(BIOS_DEBUG, "exit %s \n", __func__); return (UINT32)Status; } diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h index 43c7d10..c1eb012 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 02cf79b..480c7b6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -70,7 +70,10 @@ ////#define BLDOPT_REMOVE_SLIT TRUE //#define BLDOPT_REMOVE_WHEA TRUE //#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + +/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + //#define BLDOPT_REMOVE_HT_ASSIST TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE @@ -107,7 +110,7 @@ #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] = {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + /* Coherent link deemphasis. */ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3}, @@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] = {HT_SOCKET3, HT_LINK1B, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3A, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, - }; CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = { - {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull}, + {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818}, {CPU_LIST_TERMINAL} }; @@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET FALSE//TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE #define AGESA_ENTRY_INIT_RECOVERY FALSE #define AGESA_ENTRY_INIT_EARLY TRUE #define AGESA_ENTRY_INIT_POST TRUE @@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +/* +#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#endif +#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#endif +*/ + +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ #include "MaranelloInstall.h" /*---------------------------------------------------------------------------------------- @@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = *---------------------------------------------------------------------------------------- */ +//reference BKDG Table87: works +#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM. +#define SEED_A 0x54 +#define SEED_B 0x4D +#define SEED_C 0x45 +#define SEED_D 0x40 + +#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM. +//4B 41 51 + /* * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable @@ -486,6 +528,53 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // +#if 0//CONFIG_CPU_AMD_AGESA_FAMILY10 + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, + * Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, F10_WL_SEED, F10_WL_SEED, + F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, + F10_WL_SEED, F10_WL_SEED, F10_WL_SEED), +#endif + +#if 0 //CONFIG_CPU_AMD_AGESA_FAMILY15 + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED), + + /* HW_RXEN_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + */ + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_B, ALL_DIMMS, + SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, + SEED_B), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_C, ALL_DIMMS, + SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, + SEED_C), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_D, ALL_DIMMS, + SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, + SEED_D), +#endif + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 PSO_END }; @@ -493,7 +582,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { /* * These tables are optional and may be used to adjust memory timing settings */ - //HY Customer table UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h index a252705..1181130 100644 --- a/src/mainboard/supermicro/h8qgi/chip.h +++ b/src/mainboard/supermicro/h8qgi/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout old mode 100755 new mode 100644 index 3b98cbb..0fd4708 --- a/src/mainboard/supermicro/h8qgi/cmos.layout +++ b/src/mainboard/supermicro/h8qgi/cmos.layout @@ -2,7 +2,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb old mode 100755 new mode 100644 index 9afaac7..9d77a73 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,20 +16,18 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa/family10/root_complex +chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa/family10 - device lapic 0x10 on end + chip cpu/amd/agesa/family15 + device lapic 0x20 on end #f15 + #device lapic 0x10 on end #f10 end end device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3 - chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 @@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 register "port_enable" = "0x2104" - end #southbridge/amd/sr5650 - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB1 device pci 12.1 on end # USB1 @@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex device pci 13.1 on end # USB2 device pci 13.2 on end # USB2 device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec. + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8qgi not have codec. device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy @@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/sp5100 + end # southbridge/amd/cimx/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - - - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3 - end - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - - device pci 1b.0 on end - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - - - device pci 1c.0 on end - device pci 1c.1 on end - device pci 1c.2 on end - device pci 1c.3 on end - device pci 1c.4 on end - - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.4 on end - - - device pci 1e.0 on end - device pci 1e.1 on end - device pci 1e.2 on end - device pci 1e.3 on end - device pci 1e.4 on end - - device pci 1f.0 on end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.4 on end - - end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex + device pci 18.5 on end #f15 + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #pci_domain -end #northbridge/amd/agesa/family10/root_complex +end #northbridge/amd/agesa/family15/root_complex diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c index 4ff21ee..db7d6b7 100644 --- a/src/mainboard/supermicro/h8qgi/dimmSpd.c +++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,17 +35,27 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * @param reg -GPIO Cntrl Register * @param out -GPIO bitmap * @param out -GPIO enable bitmap + * @return old setting */ -static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) +static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable) { - u8 value; - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS - - value = pci_read_config8(sm_dev, reg); - value &= ~(enable); - value |= out; - value &= ~(enable << 4); - pci_write_config8(sm_dev, reg, value); + u8 value, ret; + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + + value = pci_read_config8(sm_dev, reg); + ret = value; + value &= ~(enable); + value |= out; + value &= ~(enable << 4); + pci_write_config8(sm_dev, reg, value); + + return ret; +} + +static void sp5100_restore_gpio(u8 reg, u8 value) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); + pci_write_config8(sm_dev, reg, value); } /*----------------------------------------------------------------------------- @@ -55,31 +65,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm /* socket 0 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 1 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 2 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 3 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, }; @@ -177,25 +187,17 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) return 0; } -static void writePmReg (int reg, int data) -{ - outb(reg, 0xCD6); - outb(data, 0xCD7); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz + outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */ } AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { + AGESA_STATUS status; int spdAddress, ioBase; u8 i2c_channel; + u8 backup; device_t sm_dev; if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; @@ -211,7 +213,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * 1 0 channel 3 (Socket3) * 1 1 channel 4 (Socket4) */ - sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03); + backup = sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03); spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) @@ -219,11 +221,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA /* * SMBus Base Address was set during southbridge early setup. - * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000 + * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default */ sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0); ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0); setupFch(ioBase); - return readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + sp5100_restore_gpio(SP5100_GPIO53_56, backup); + + return status; } diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl old mode 100755 new mode 100644 index ebdb1eb..3f10012 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -988,73 +988,58 @@ DefinitionBlock ( Scope(\_GPE) { /* Start Scope GPE */ /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L00) { + //DBGO("\\_GPE\\_L00\n") + } /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L01) { + //DBGO("\\_GPE\\_L01\n") + } /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L02) { + //DBGO("\\_GPE\\_L02\n") + } /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ + //DBGO("\\_GPE\\_L00\n") Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L04) { + //DBGO("\\_GPE\\_L04\n") + } /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L05) { + //DBGO("\\_GPE\\_L05\n") + } - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ + /* _L06 General event 6 - Used for GPM6, moved to USB.asl */ + /* _L07 General event 7 - Used for GPM7, moved to USB.asl */ /* Legacy PM event */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ + //DBGO("\\_GPE\\_L08\n") } /* Temp warning (TWarn) event */ Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ + //DBGO("\\_GPE\\_L09\n") Notify (\_TZ.TZ00, 0x80) } /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ + Method(_L0A) { + //DBGO("\\_GPE\\_L0A\n") + } /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ + //DBGO("\\_GPE\\_L0B\n") Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -1065,126 +1050,81 @@ DefinitionBlock ( } /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ + Method(_L0C) { + //DBGO("\\_GPE\\_L0C\n") + } /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ + Method(_L0D) { + //DBGO("\\_GPE\\_L0D\n") + } - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ + /* _L0E GPM9 SCI event - Moved to USB.asl */ /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ + Method(_L0F) { + //DBGO("\\_GPE\\_L0F\n") + } /* ExtEvent0 SCI event */ Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ + //DBGO("\\_GPE\\_L10\n") } /* ExtEvent1 SCI event */ Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ + //DBGO("\\_GPE\\_L11\n") } /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ + Method(_L12) { + //DBGO("\\_GPE\\_L12\n") + } - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ + /* _L13 GPM0 SCI event - Moved to USB.asl */ + /* _L14 GPM1 SCI event - Moved to USB.asl */ + /* _L15 GPM2 SCI event - Moved to USB.asl */ + /* _L16 GPM3 SCI event - Moved to USB.asl */ + /* _L17 GPM8 SCI event - Moved to USB.asl */ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ + //DBGO("\\_GPE\\_L18\n") Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ + /* _L19 GPM4 SCI event - Moved to USB.asl */ + /* _L1A GPM5 SCI event - Moved to USB.asl */ /* Azalia SCI event */ Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ + //DBGO("\\_GPE\\_L1B\n") Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ + Method(_L1C) { + //DBGO("\\_GPE\\_L1C\n") + } /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ + Method(_L1D) { + //DBGO("\\_GPE\\_L1D\n") + } /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ + Method(_L1E) { + //DBGO("\\_GPE\\_L1E\n") + } - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ + /* _L1F SATA SCI event - Moved to sata.asl */ } /* End Scope GPE */ @@ -1569,7 +1509,7 @@ DefinitionBlock ( 0x0CF8, // Range Maximum 0x01, // Alignment 0x08, // Length - ) + ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity @@ -1602,10 +1542,10 @@ DefinitionBlock ( ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity - 0x9000, // Range Minimum - 0xefff, // Range Maximum + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum 0x0000, // Translation Offset - 0x6000, // Length + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space @@ -1613,21 +1553,26 @@ DefinitionBlock ( 0xE0000000, // Address Base 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Granularity - 0xF0000000, // Range Minimum - 0xFFFFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x10000000, // Length - ,, , AddressRangeMemory, TypeStatic) }) Method (_CRS, 0, NotSerialized) { CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - Store (PCBA, BAS1) - Store (PCLN, LEN1) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, BAS1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) + //DBGO(TOM1) Return (CRS) } diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index c2f714d..0c63162 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,21 +28,17 @@ #include #include #include -#include "southbridge/amd/sb700/sb700.h" +#include "Platform.h" /*sb700 platform header*/ -u16 pm_base = SB700_ACPI_IO_BASE; -/* pm_base should be set in sb acpi */ -/* pm_base should be got from bar2 of sb700. Here I compact ACPI - * registers into 32 bytes limit. - * */ +#ifndef ACPI_BLK_BASE + #define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); @@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8); - - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ fadt->pm1_evt_len = 4; @@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; @@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; @@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; @@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; @@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 14e6bca..8c31cbf 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,8 +23,10 @@ #include #include #include -#include #include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -34,22 +36,6 @@ u8 bus_isa; u8 bus_sp5100[2]; u8 bus_sr5650[14]; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* - * HT Chain device num, actually it is unit id base of every ht device in chain, - * assume every chain only have 4 ht device at most - */ -u32 hcdnx[] = { - 0x20202020, -}; u32 bus_type[256]; @@ -106,8 +92,7 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff; - // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sr5650[0] = 0; bus_sp5100[0] = bus_sr5650[0]; /* sp5100 */ @@ -151,4 +136,9 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Late_Post(); +#endif } diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 640a0a6..11e5256 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,9 +27,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index f00b5a0..675c87f 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,36 +25,48 @@ #include #include #include -#include "southbridge/amd/sr5650/cmn.h" +#include #include "chip.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); +void set_pcie_dereset(void *nbconfig); +void set_pcie_reset(void *nbconfig); /** * */ -void set_pcie_reset(void) +void set_pcie_reset(void *nbconfig) { } /** + * Mainboard specific RD890 CIMx callback * Release Resets to PCIe Links - * PCIE_RESET_GPIO1,2,4,5 + * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie */ -void set_pcie_dereset(void) +void set_pcie_dereset(void *nbconfig) { - device_t pcie_core_dev; + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007); + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } } /************************************************* -* enable the dedicated function in h8qgi board. -*************************************************/ + * enable the dedicated function in h8qgi board. + *************************************************/ static void h8qgi_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -69,5 +81,5 @@ int add_mainboard_resources(struct lb_memory *mem) struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") - .enable_dev = h8qgi_enable, + .enable_dev = h8qgi_enable, }; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5c01994..92771bd 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,17 +33,16 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; +extern u8 bus_isa; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; device_t dev; u32 dword; - u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); @@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v) #if CONFIG_MAX_CPUS >= 16 apicid_sp5100 = 0x0; #else - apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif apicid_sr5650 = apicid_sp5100 + 1; - //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); +#ifdef UNUSED_CODE + u8 byte; /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); @@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v) dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); +#endif /* * 00:12.0: PROG SATA : INT F @@ -102,11 +103,11 @@ static void *smp_write_config_table(void *v) /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); - } + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); + } } @@ -155,27 +156,27 @@ static void *smp_write_config_table(void *v) * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); + /* PCI_SLOT 0. */ + PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h new file mode 100644 index 0000000..bbc4ad7 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c index f36b0d8..883cad1 100644 --- a/src/mainboard/supermicro/h8qgi/platform_oem.c +++ b/src/mainboard/supermicro/h8qgi/platform_oem.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,6 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "platform_oem.h" #include "Filecode.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -43,6 +42,7 @@ * **/ /*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h deleted file mode 100644 index ab0d6df..0000000 --- a/src/mainboard/supermicro/h8qgi/platform_oem.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_OEM_H_ -#define _PLATFORM_OEM_H_ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -#endif //_PLATFORM_OEM_H_ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c new file mode 100644 index 0000000..7a947b3 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include +#include + +#ifndef __PRE_RAM__ +#include +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h new file mode 100644 index 0000000..8f45019 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c new file mode 100644 index 0000000..68a39f2 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 08b0eb2..119593e 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,34 +29,54 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" -#include "southbridge/amd/sr5650/sr5650.h" -#include "southbridge/amd/sb700/sb700.h" +#include +#include #include "superio/nuvoton/wpcm450/wpcm450.h" +#include "superio/winbond/w83627dhg/w83627dhg.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ +//TODO: should not put here +static void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, base); + reg8 = pci_read_config8(dev, 0x48); + reg8 |= 1 << 2; + pci_write_config8(dev, 0x48, reg8); +} + +static void sb7xx_51xx_disable_wideio(u8 wio_index) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, 0); + reg8 = pci_read_config8(dev, 0x48); + reg8 &= ~(1 << 2); + pci_write_config8(dev, 0x48, reg8); +} + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + post_code(0x30); agesawrapper_amdinitmmio(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - post_code(0x31); - sb7xx_51xx_lpc_port80(); - post_code(0x32); - } + post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); @@ -78,7 +98,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } - post_code(0x38); + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x38); + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + post_code(0x39); + nb_Poweron_Init(); + post_code(0x3A); + sb_Poweron_Init(); + } + post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); @@ -86,12 +118,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } - sr5650_early_setup(); - post_code(0x39); - - sb7xx_51xx_early_setup(); - sr5650_htinit(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + post_code(0x3C); + nb_Ht_Init(); + post_code(0x3D); + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); @@ -103,8 +133,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } - printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); post_code(0x41); val = agesawrapper_amdinitenv(); @@ -114,8 +145,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); post_code(0x50); print_debug("Disabling cache as ram "); diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c new file mode 100644 index 0000000..4cbb8ca --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h new file mode 100644 index 0000000..aac61ec --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_ From gerrit at coreboot.org Wed Feb 1 11:52:19 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 11:52:19 +0100 Subject: [coreboot] Patch set updated for coreboot: 52ae40f HWM: Nuvoton W83795G/ADG HWM support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569 -gerrit commit 52ae40f1de1b2e7c637858cbc80561a3a26de7da Author: Kerry Sheh Date: Wed Feb 1 19:43:52 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/drivers/i2c/Kconfig | 1 + src/drivers/i2c/Makefile.inc | 1 + src/drivers/i2c/w83795/Kconfig | 2 + src/drivers/i2c/w83795/Makefile.inc | 1 + src/drivers/i2c/w83795/chip.h | 4 + src/drivers/i2c/w83795/w83795.c | 276 ++++++++++++++++++++++++++ src/drivers/i2c/w83795/w83795.h | 73 +++++++ src/mainboard/supermicro/h8qgi/Kconfig | 1 + src/mainboard/supermicro/h8qgi/devicetree.cb | 8 +- src/mainboard/supermicro/h8qgi/romstage.c | 6 + 10 files changed, 371 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig index 91ad025..09c306b 100644 --- a/src/drivers/i2c/Kconfig +++ b/src/drivers/i2c/Kconfig @@ -4,3 +4,4 @@ source src/drivers/i2c/adt7463/Kconfig source src/drivers/i2c/i2cmux/Kconfig source src/drivers/i2c/i2cmux2/Kconfig source src/drivers/i2c/lm63/Kconfig +source src/drivers/i2c/w83795/Kconfig diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc index d462b69..97e9729 100644 --- a/src/drivers/i2c/Makefile.inc +++ b/src/drivers/i2c/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += adt7463 subdirs-y += i2cmux subdirs-y += i2cmux2 subdirs-y += lm63 +subdirs-y += w83795 diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig new file mode 100644 index 0000000..80856e2 --- /dev/null +++ b/src/drivers/i2c/w83795/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_W83795 + bool diff --git a/src/drivers/i2c/w83795/Makefile.inc b/src/drivers/i2c/w83795/Makefile.inc new file mode 100644 index 0000000..708a170 --- /dev/null +++ b/src/drivers/i2c/w83795/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h new file mode 100644 index 0000000..2900636 --- /dev/null +++ b/src/drivers/i2c/w83795/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations drivers_i2c_w83795_ops; + +struct drivers_i2c_w83795_config { +}; diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c new file mode 100644 index 0000000..cf2a97e --- /dev/null +++ b/src/drivers/i2c/w83795/w83795.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include "w83795.h" + +static u32 w83795_set_bank(u8 bank) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); +} + +static u8 w83795_read(u16 reg) +{ + u32 ret; + + ret = w83795_set_bank(reg >> 8); + if (ret < 0) { + printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8); + return -1; + } + + ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff); + return ret; +} + +static u8 w83795_write(u16 reg, u8 value) +{ + u32 err; + + err = w83795_set_bank(reg >> 8); + if (err < 0) { + printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8); + return -1; + } + + err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value); + return err; +} + +#if 0 +static void w83795_set_speed(void) +{ + +} + +static void w83795_set_ttti(void)//KR it works +{ + u32 i; + for (i = 0; i < 6; i++) { + //w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40 + //w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80 + } +} +#endif + +/* + * Enable Digital Temperature Sensor + */ +static void w83795_dts_enable(u8 dts_src) +{ + u8 val; + + /* DIS */ + val = w83795_read(W83795_REG_DTSC); + val |= (dts_src & 0x01); + w83795_write(W83795_REG_DTSC, val); + + /* DTSE */ + val = w83795_read(W83795_REG_DTSE); + val |= 0xFF; + w83795_write(W83795_REG_DTSE, val); + + /* store bank3 regs first before enable DTS */ + + /* + * TD/TR1-4 termal diode by default + * 0x00 Disable + * 0x01 thermistors on motherboard + * 0x10 different mode voltage + * 0x11 CPU internal thermal diode output + * + * TR5-6 thermistors by default TRn + */ + val = 0x55; /* thermal diode */ + w83795_write(W83795_REG_TEMP_CTRL2, val); + + /* Enable Digital Temperature Sensor */ + val = w83795_read(W83795_REG_TEMP_CTRL1); + val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */ + w83795_write(W83795_REG_TEMP_CTRL1, val); +} + +static void w83795_set_tfmr(w83795_fan_mode_t mode) +{ + u8 val; + u8 i; + + if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) { + val = 0xFF; + } else { + val = 0x00; + } + + for (i = 0; i < 6; i++) + w83795_write(W83795_REG_TFMR(i), val); +} + +static u32 w83795_set_fan_mode(w83795_fan_mode_t mode) +{ + if (mode == SPEED_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS1, 0xFF); + printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n"); + } else { + w83795_write(W83795_REG_FCMS1, 0x00); + if (mode == THERMAL_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS2, 0x00); + printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n"); + } else if (mode == SMART_FAN_MODE) { + w83795_write(W83795_REG_FCMS2, 0x3F); + printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n"); + } else { + printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n"); + return -1; + } + } + + return 0; +} + +static void w83795_set_tss(void) +{ + u8 val; + + val = 0x00; + w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */ + w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */ + w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */ +} + +static void w83795_set_fan(w83795_fan_mode_t mode) +{ + u8 i; + + /* select temperature sensor (TSS)*/ + w83795_set_tss(); + + /* select Temperature to Fan mapping Relationships (TFMR)*/ + w83795_set_tfmr(mode); + + /* set fan output controlled mode (FCMS)*/ + w83795_set_fan_mode(mode); + + /* Set Critical Temperature to Full Speed all fan (CTFS) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */ + } + + if (mode == THERMAL_CRUISE_MODE) { + /* Set Target Temperature of Temperature Inputs (TTTI) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */ + } + } else if (mode == SMART_FAN_MODE) { + /* Set the Relative Register-at SMART FAN IV Control Mode Table */ + //SFIV TODO + } + + /* Set Hystersis of Temperature (HT) */ +} + +static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +{ + u8 i; + u8 val; + + if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } + val = w83795_read(W83795_REG_CONFIG); + if ((val & W83795_REG_CONFIG_CONFIG48) == 0) + printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); + else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); + + /* Reset */ + val |= W83795_REG_CONFIG_INIT; + w83795_write(W83795_REG_CONFIG, val); + + /* Fan monitoring setting */ + val = 0xFF; /* FAN1-FAN8 */ + w83795_write(W83795_REG_FANIN_CTRL1, val); + val = 0x3F; /* FAN9-FAN14 */ + w83795_write(W83795_REG_FANIN_CTRL2, val); + + /* enable monitoring operations */ + val = w83795_read(W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(W83795_REG_CONFIG, val); + + w83795_dts_enable(dts_src); + w83795_set_fan(mode); + + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + for (i = 0; i < 6; i++) { + val = w83795_read(W83795_REG_CTFS(i)); + printk(BIOS_INFO, " %x %d", i, val); + val = w83795_read(W83795_REG_TTTI(i)); + printk(BIOS_INFO, " %d\n", val); + } + + /* Temperature ReadOut */ + for (i = 0; i < 9; i++) { + val = w83795_read(W83795_REG_DTS(i)); + printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val); + } +} + +static void w83795_hwm_init(device_t dev) +{ + struct device *cpu; + struct cpu_info *info; + + info = cpu_info(); + cpu = info->cpu; + if (!cpu) + die("CPU: missing cpu device structure"); + + if (cpu->vendor == X86_VENDOR_AMD) + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); + else if (cpu->vendor == X86_VENDOR_INTEL) + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_INTEL_PECI); + else + printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); +} + +static void w83795_noop(device_t dummy) +{ +} + +static struct device_operations w83795_operations = { + .read_resources = w83795_noop, + .set_resources = w83795_noop, + .enable_resources = w83795_noop, + .init = w83795_hwm_init, +}; + +static void enable_dev(device_t dev) +{ + dev->ops = &w83795_operations; +} + +struct chip_operations drivers_i2c_w83795_ops = { + CHIP_NAME("Nuvoton W83795G/ADG Hardware Monitor") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h new file mode 100644 index 0000000..de0a554 --- /dev/null +++ b/src/drivers/i2c/w83795/w83795.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _W83795_H_ +#define _W83795_H_ + +#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ + +#define W83795_REG_I2C_ADDR 0xFC +#define W83795_REG_BANKSEL 0x00 +#define W83795_REG_CONFIG 0x01 +#define W83795_REG_CONFIG_START 0x01 +#define W83795_REG_CONFIG_CONFIG48 0x04 +#define W83795_REG_CONFIG_INIT 0x80 + +#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ +#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ +#define W83795_REG_FANIN_CTRL1 0x06 +#define W83795_REG_FANIN_CTRL2 0x07 +#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ +#define DTS_SRC_INTEL_PECI (0 << 0) +#define DTS_SRC_AMD_SBTSI (1 << 0) + +#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ +#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ +#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ +#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ +#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ + +#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ +#define W83795_REG_DTS(n) (0x26 + (n)) +#define W83795_REG_VRLSB 0x3C + +#define W83795_TEMP_REG_TR1 0x21 +#define W83795_TEMP_REG_TR2 0x22 +#define W83795_TEMP_REG_TR3 0x23 +#define W83795_TEMP_REG_TR4 0x24 +#define W83795_TEMP_REG_TR5 0x1F +#define W83795_TEMP_REG_TR6 0x20 + +#define W83795_REG_FCMS1 0x201 +#define W83795_REG_FCMS2 0x208 +#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ +#define W83795_REG_DFSP 0x20C + +#define W83795_REG_FTSH(n) (0x240 + (n) * 2) +#define W83795_REG_FTSL(n) (0x241 + (n) * 2) +#define W83795_REG_TFTS 0x250 + +typedef enum w83795_fan_mode { + SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range + THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI + SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed + MANUAL_MODE, ///< control manually +} w83795_fan_mode_t; + +#endif diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 201df45..31b16b6 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select DRIVERS_I2C_W83795 select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 9d77a73..8ecf968 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -84,8 +84,8 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 0x01 #keyboard irq 0x72 = 0x0C #mouse end - #device pnp 2e.6 off # SPI - #end + device pnp 2e.6 off # SPI + end device pnp 2e.307 off # GPIO6 end device pnp 2e.8 off # WDTO#, PLED @@ -106,6 +106,10 @@ chip northbridge/amd/agesa/family15/root_complex device pnp 2e.c off # PECI, SST end end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 end # LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 119593e..77bf144 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -119,6 +119,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ From gerrit at coreboot.org Wed Feb 1 11:53:20 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Wed, 1 Feb 2012 11:53:20 +0100 Subject: [coreboot] Patch set updated for coreboot: c924cbe H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568 -gerrit commit c924cbee830691c4a776465c09029575d0197c90 Author: Kerry Sheh Date: Wed Feb 1 16:05:50 2012 +0800 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. For mainboard using AMD AGESA framework, lots of AGESA code will be compiled into romstage, so romstage becomes larger, especially for mainboard support 2 or more processor families. H8QGI support both f10 and f15 CPUs, 512K default xip size is not enough, so increase to 1M Bytes. Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/supermicro/h8qgi/Kconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..201df45 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -123,5 +123,19 @@ config VGA_BIOS_ID depends on VGA_BIOS default "102b,0532" +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 kinds of processor family, + Compiling 2 cpu families agesa code will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + endif # BOARD_SUPERMICRO_H8QGI From gerrit at coreboot.org Wed Feb 1 15:29:26 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 15:29:26 +0100 Subject: [coreboot] New patch to review for coreboot: 162b984 Add cache_as_ram.inc with hyper-threading CPU support References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit 162b984fbc02c230175e431135e5d50d057c9f2f Author: Ky?sti M?lkki Date: Wed Feb 1 15:55:54 2012 +0200 Add cache_as_ram.inc with hyper-threading CPU support This variant of cache_as_ram.inc starts the sibling CPU processors and clears the cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. A secondary main (named main_no_xip) built into romstage can be executed with XIP cache disabled. On my test setup (Intel e7505) ECC scrub fails if run with XIP enabled. The code was developed for model_f25 on socket_mPGA604, but probably should be placed under cpu/intel/car/ instead. Some of the cache enable-disable logic seems spurious to me. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Makefile.inc | 8 +- src/cpu/Kconfig | 4 + src/cpu/intel/model_f2x/Kconfig | 4 + src/cpu/intel/model_f2x/Makefile.inc | 3 + src/cpu/intel/model_f2x/cache_as_ram.inc | 372 ++++++++++++++++++++++++++++++ src/cpu/intel/socket_mPGA604/Kconfig | 17 ++- 6 files changed, 400 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 36f9d3a..420378b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..93b132d 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -9,6 +9,10 @@ config CACHE_AS_RAM bool default !ROMCC +config CACHE_AS_RAM_TEST + bool + default n + config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 50cac79..7eafb4a 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,3 +1,7 @@ config CPU_INTEL_MODEL_F2X bool select SMP + select UDELAY_TSC +# select UDELAY_LAPIC +# select AP_IN_SIPI_WAIT + diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index c393343..a1e5463 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1,4 @@ driver-y += model_f2x_init.c + +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/model_f2x/cache_as_ram.inc + diff --git a/src/cpu/intel/model_f2x/cache_as_ram.inc b/src/cpu/intel/model_f2x/cache_as_ram.inc new file mode 100644 index 0000000..bdd7e1a --- /dev/null +++ b/src/cpu/intel/model_f2x/cache_as_ram.inc @@ -0,0 +1,372 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Ky?sti M?lkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) + + .code32 + + /* Save the BIST result. */ + movl %eax, %ebp + + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc cache_as_ram + bswapl %ebx + cmpb $01, %bh + jbe cache_as_ram + +hyper_threading_cpu: + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~0x0F), %edx /* MAXPHYWID = 36 */ + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jnz bsp_init + +ap_init: + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* MTRR registers are shared between HT siblings. */ + movl $0x300, %ecx + rdmsr + inc %eax + wrmsr + +ap_halt: + cli +1: hlt + jnz 1b + + +bsp_init: + /* Send INIT IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Send Start IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Wait for sibling CPU to start. */ +1: movl $0x300, %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + +sipi_complete: + +cache_as_ram: + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable variable MTRRs. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + invd + + /* Clear memory for stack. */ + cld + xorl %eax, %eax + movl $(CACHE_AS_RAM_BASE), %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + rep stosl + +#if 0 + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + wbinvd + movl %eax, %cr0 + wbinvd +#endif + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + +#if 0 + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 +#endif + +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 128), %esp +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE), %esp +#endif + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23); + + call main + addl $4, %esp + + post_code(0x2f) + +#if CONFIG_MAIN_WITHOUT_XIP + /* With Intel e7505 memory controller, hardware ECC scrub + * halts and/or flushes call stack if run with XIP enabled. + */ + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Disable Flash XIP. */ + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0, %edx + movl $0x0, %eax + wrmsr + invd + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + pushl $0x0 + call main_no_xip + addl $4, %esp + movl %esp, %ebp +#endif + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + invd + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..d8ea23a 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,11 +1,15 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X select MMX select SSE - select UDELAY_TSC # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -14,3 +18,14 @@ config SSE2 bool default n depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + From gerrit at coreboot.org Wed Feb 1 15:29:26 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 15:29:26 +0100 Subject: [coreboot] Patch set updated for coreboot: 13ac7a9 Add support for RAM-less multi-processor init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 13ac7a9e4ed6cba54a049f584a87aabfa82756bc Author: Ky?sti M?lkki Date: Wed Feb 1 15:33:39 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is exported as CONFIG_AP_SIPI_VECTOR and will be used by a cache_as_ram.inc with hyper-threading support. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Makefile.inc | 9 +++++++-- src/arch/x86/init/ldscript_failover.lb | 12 ++++++++---- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cbe38dd..36f9d3a 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -338,6 +338,11 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ +$(obj)/bootblock_map.h: $(obj)/bootblock.elf + printf '#define CONFIG_AP_SIPI_VECTOR 0x' > $@ + grep ap_sipi_vector $(obj)/bootblock.map | colrm 9 >> $@ + printf '\n' >> $@ + ####################################################################### # Build the romstage $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld @@ -370,9 +375,9 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h $(obj)/bootblock_map.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -include $(obj)/bootblock_map.h -I. -I$(src) $< -o $@ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..052e0c5 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,10 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); /DISCARD/ : { *(.comment) From gerrit at coreboot.org Wed Feb 1 15:55:35 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 15:55:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 4b6a312 Via Epia-N and C3: Set ioapic delivery type in Kconfig References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/435 -gerrit commit 4b6a3125c4366bdc00f1afa0a174fa5665c410d1 Author: Ky?sti M?lkki Date: Mon Nov 21 19:12:50 2011 +0200 Via Epia-N and C3: Set ioapic delivery type in Kconfig The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. If someone can confirm this, set delivery type under cpu/via/model_c3 instead. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Ky?sti M?lkki --- src/Kconfig | 5 +++++ src/arch/x86/lib/ioapic.c | 9 --------- src/mainboard/via/epia-n/Kconfig | 5 +++++ 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 64c359e..7e91144 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -239,6 +239,11 @@ config IOAPIC bool default n +# Boards with CPU_VIA_C3 may need to override delivery type. +config IOAPIC_DELIVERY_TYPE + int + default 1 + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 7d166b9..5e17990 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -179,15 +179,6 @@ static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) } } -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. - -#if CONFIG_EPIA_VT8237R_INIT -#define CONFIG_IOAPIC_DELIVERY_TYPE 0 -#else -#define CONFIG_IOAPIC_DELIVERY_TYPE 1 -#endif - /** * Assign IOAPIC with an ID * diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 4806753..5a88f6a 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -28,4 +28,9 @@ config IRQ_SLOT_COUNT int default 7 +# IRQ delivery on APIC bus may be a Via C3 CPU requirement. +config IOAPIC_DELIVERY_TYPE + int + default 0 + endif # BOARD_VIA_EPIA_N From gerrit at coreboot.org Wed Feb 1 15:56:05 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 15:56:05 +0100 Subject: [coreboot] Patch set updated for coreboot: fbfb272 IOAPIC: Divide setup_ioapic() in two parts. References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/300 -gerrit commit fbfb2728b181dadd6d0d9ecb5b1f52d033e04cf1 Author: Ky?sti M?lkki Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Currently some southbridge codes implement the init_ioapic() part locally and do not implement the load_vectors() part at all. I suspect that load_vectors() should always be called to enable IOAPIC interrupt routes before OS. Revised init_ioapic() to log on a critical level if one tries to change an already assigned (non-zero) APIC ID, or when the APIC ID is not assigned. Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca Signed-off-by: Ky?sti M?lkki --- src/arch/x86/lib/ioapic.c | 151 +++++++++++++++++++++++++++++++++----------- 1 files changed, 113 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 81d964c..7d166b9 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -34,6 +34,11 @@ static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) write32(ioapic_base + 0x10, value); } +/** + * Clear all IOAPIC vectors. + * + * @param ioapic_base IOAPIC base address + */ void clear_ioapic(u32 ioapic_base) { u32 low, high; @@ -64,24 +69,84 @@ void clear_ioapic(u32 ioapic_base) } } -void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +/** + * Assign IOAPIC with an ID and set delivery type. + * + * @param ioapic_base IOAPIC base address + * @param new_id If non-zero (1-15), assign new apic ID. + * If zero, use previously assigned apic ID. + * @param delivery If 0x0, deliver interrupts on APIC serial bus + * If 0x1, deliver interrupts on FSB + */ +static void init_ioapic(u32 ioapic_base, u8 new_id, u8 delivery) { - u32 bsp_lapicid = lapicid(); - u32 low, high; - u32 i, ioapic_interrupts; + u8 loud = 0; + u8 active_id; + u32 reg32; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", - ioapic_base); - printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + reg32 = io_apic_read(ioapic_base, 0x00); + active_id = (reg32 >> 24) & 0xf; + + /* Changing a previously assigned ID and attempting + * to use ID=0 here are logged at a critical level. + */ + if ( ((active_id && new_id) && (active_id != new_id)) || + !(active_id || new_id)) + loud = 1; + + if (!new_id) { + printk(loud ? BIOS_CRIT : BIOS_DEBUG, + "IOAPIC: 0x%08x using old ID = %d\n", + ioapic_base, active_id); + + } else { + reg32 &= 0xf0ffffff; + reg32 |= (new_id & 0xf) << 24; + io_apic_write(ioapic_base, 0x00, reg32); + + printk(loud ? BIOS_CRIT : BIOS_DEBUG, + "IOAPIC: 0x%08x changing ID = %d->%d\n", + ioapic_base, active_id, new_id); + + reg32 = io_apic_read(ioapic_base, 0x00); + active_id = (reg32 >> 24) & 0xf; + if (active_id != new_id) + printk(BIOS_CRIT, + "IOAPIC: 0x%08x changing ID failed (%d!=%d)\n", + ioapic_base, active_id, new_id); + } - if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); - /* Set IOAPIC ID if it has been specified. */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | - (ioapic_id << 24)); + /* Assign interrupt delivery type. */ + reg32 = io_apic_read(ioapic_base, 0x03); + switch (delivery) { + case 0: + printk(BIOS_DEBUG, "IOAPIC: Delivery is on APIC serial bus\n"); + reg32 = 0x00; + break; + case 1: + printk(BIOS_DEBUG, "IOAPIC: Delivery is on FSB\n"); + reg32 = 0x01; + break; + default: + printk(BIOS_CRIT, "IOAPIC: Delivery is reverted to FSB\n"); + reg32 = 0x01; + break; } + io_apic_write(ioapic_base, 0x03, reg32); +} + +/** + * Fill IOAPIC vectors all targeting the same processor. + * Virtual Wire Mode on vector 0 is enabled, others remain disabled. + * + * + * @param ioapic_base IOAPIC base address + * @param bsp_lapicid APIC ID of a CPU to receive the interrupts + */ +static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) +{ + u32 low, high; + u32 i, ioapic_interrupts; /* Read the available number of interrupts. */ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; @@ -89,28 +154,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. -#if CONFIG_EPIA_VT8237R_INIT -#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -#else -#define IOAPIC_INTERRUPTS_ON_FSB -#endif - -#ifdef IOAPIC_INTERRUPTS_ON_FSB - /* - * For the Pentium 4 and above APICs deliver their interrupts - * on the front side bus, enable that. - */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); - io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); -#endif -#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); - io_apic_write(ioapic_base, 0x03, 0); -#endif - /* Enable Virtual Wire Mode. */ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); @@ -125,10 +168,8 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); - low = DISABLED; high = NONE; - for (i = 1; i < ioapic_interrupts; i++) { io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); @@ -137,3 +178,37 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) i, high, low); } } + +// XXX this decision should probably be made elsewhere, and +// it's the C3, not the EPIA this depends on. + +#if CONFIG_EPIA_VT8237R_INIT +#define CONFIG_IOAPIC_DELIVERY_TYPE 0 +#else +#define CONFIG_IOAPIC_DELIVERY_TYPE 1 +#endif + +/** + * Assign IOAPIC with an ID + * + * Compile-time options from mainboard Kconfig can affect the + * chosen IOAPIC operational mode. + * + * @param ioapic_base IOAPIC base address + * @param new_id If non-zero (1-15), assign new apic ID. + * If zero, use previously assigned apic ID. + */ +void setup_ioapic(u32 ioapic_base, u8 new_id) +{ + u8 bsp_lapicid = lapicid(); + u8 ioapic_dt = CONFIG_IOAPIC_DELIVERY_TYPE; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + init_ioapic(ioapic_base, new_id, ioapic_dt); + + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC ID = %d\n", + bsp_lapicid); + load_vectors(ioapic_base, bsp_lapicid); +} + From gerrit at coreboot.org Wed Feb 1 15:56:06 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 15:56:06 +0100 Subject: [coreboot] Patch set updated for coreboot: 480d5a0 Refactor and clean-up i82801 LPC codes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/302 -gerrit commit 480d5a0e605800bba8725cc37a6b251ce309288d Author: Ky?sti M?lkki Date: Tue Jan 31 16:40:31 2012 +0200 Refactor and clean-up i82801 LPC codes Rewrite IOAPIC initialisation using global setup_ioapic() or setup_ioapic_novectors(). In my opinion, the _novectors() variant that is currently used is not sufficient to route IOAPIC interrupts on boot since Virtual Wire programming and/or vectors are not programmed. That takes further study and separate patch. Select Kconfig option IOAPIC as the southbridge has one and now requires that arch/x86/lib/ioapic.c is compiled in. Unify handling of ACPI BARs. Enable device resources during dev->ops->enable() and not during dev->ops->init(). Change-Id: I8ad80fdd0913995471269f33293c4a4b8cf1de83 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/include/arch/ioapic.h | 1 + src/arch/x86/lib/ioapic.c | 11 +++ src/southbridge/intel/i82801ax/Kconfig | 1 + src/southbridge/intel/i82801ax/lpc.c | 59 ++++++++++------ src/southbridge/intel/i82801bx/Kconfig | 1 + src/southbridge/intel/i82801bx/lpc.c | 58 +++++++++------ src/southbridge/intel/i82801cx/Kconfig | 1 + src/southbridge/intel/i82801cx/lpc.c | 107 ++++++++++++++++------------- src/southbridge/intel/i82801dx/i82801dx.h | 1 + src/southbridge/intel/i82801dx/lpc.c | 68 +++++++++++-------- src/southbridge/intel/i82801ex/i82801ex.h | 9 +++ src/southbridge/intel/i82801ex/lpc.c | 82 +++++++++++++++------- src/southbridge/intel/i82801gx/i82801gx.h | 1 + src/southbridge/intel/i82801gx/lpc.c | 77 ++++++++++++--------- 14 files changed, 297 insertions(+), 180 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 623f617..3eabcdc 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -40,5 +40,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); +void setup_ioapic_novectors(u32 ioapic_base, u8 new_id); #endif diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 5e17990..1d42658 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -203,3 +203,14 @@ void setup_ioapic(u32 ioapic_base, u8 new_id) load_vectors(ioapic_base, bsp_lapicid); } +void setup_ioapic_novectors(u32 ioapic_base, u8 new_id) +{ + u8 ioapic_dt = CONFIG_IOAPIC_DELIVERY_TYPE; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + init_ioapic(ioapic_base, new_id, ioapic_dt); + + printk(BIOS_CRIT, "IOAPIC: Interrupt Vectors were not initialized\n"); +} + diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 70734a7..71ae016 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801AX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index c9404ed..c6be112 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -70,17 +70,30 @@ typedef struct southbridge_intel_i82801ax_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801ax_enable_apic(struct device *dev) -{ - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801ax_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801ax_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -88,20 +101,8 @@ static void i82801ax_enable_apic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801ax_enable_serial_irqs(struct device *dev) @@ -216,11 +217,8 @@ static void i82801ax_lpc_decode_en(device_t dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801ax_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801ax_enable_serial_irqs(dev); @@ -272,10 +270,25 @@ static void i82801ax_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801ax_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801ax_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801ax_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801ax_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801ax_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801ax_enable, diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 00cb5bf..3d725d4 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801BX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 0ff44e6..34eccf3 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -72,17 +72,29 @@ typedef struct southbridge_intel_i82801bx_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801bx_enable_apic(struct device *dev) -{ - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; - volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801bx_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801bx_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -90,20 +102,8 @@ static void i82801bx_enable_apic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801bx_enable_serial_irqs(struct device *dev) @@ -234,11 +234,8 @@ static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801bx_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801bx_enable_serial_irqs(dev); @@ -290,10 +287,25 @@ static void i82801bx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801bx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801bx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801bx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801bx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801bx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801bx_enable, diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig index a0c775d..7534cbb 100644 --- a/src/southbridge/intel/i82801cx/Kconfig +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -1,2 +1,3 @@ config SOUTHBRIDGE_INTEL_I82801CX bool + select IOAPIC diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index a1ffb8f..bacca48 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -24,34 +24,43 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801cx_enable_acpi(struct device *dev) +{ + // Set ACPI base address to 0x1100 (I/O space) + pci_write_config32(dev, PMBASE, 0x00001101); + + // Enable ACPI I/O and power management + pci_write_config8(dev, ACPI_CNTL, 0x10); + + // Set GPIO base address to 0x1180 (I/O space) + pci_write_config32(dev, GPIO_BASE, 0x00001181); + + // Enable GPIO + pci_write_config8(dev, GPIO_CNTL, 0x10); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801cx_general_cntl(struct device *dev) { - uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; - volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ - dword |= (1 <<13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - - // Must program the APIC's ID before using it - - *ioapic_index = 0; // Select APIC ID register - *ioapic_data = (2<<24); - - // Hang if the ID didn't take (chip not present?) - *ioapic_index = 0; - dword = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); - if(dword != (2<<24)) - die(""); - - *ioapic_index = 3; // Select Boot Configuration register - *ioapic_data = 1; // Use Processor System Bus to deliver interrupts + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + } // This is how interrupts are received from the Super I/O chip @@ -118,20 +127,6 @@ static void i82801cx_rtc_init(struct device *dev) static void i82801cx_1f0_misc(struct device *dev) { - // Prevent LPC disabling, enable parity errors, and SERR# (System Error) - pci_write_config16(dev, PCI_COMMAND, 0x014f); - - // Set ACPI base address to 0x1100 (I/O space) - pci_write_config32(dev, PMBASE, 0x00001101); - - // Enable ACPI I/O and power management - pci_write_config8(dev, ACPI_CNTL, 0x10); - - // Set GPIO base address to 0x1180 (I/O space) - pci_write_config32(dev, GPIO_BASE, 0x00001181); - - // Enable GPIO - pci_write_config8(dev, GPIO_CNTL, 0x10); // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); @@ -160,8 +155,9 @@ static void lpc_init(struct device *dev) int pwr_on=-1; int nmi_option; + i82801cx_general_cntl(dev); /* IO APIC initialization */ - i82801cx_enable_ioapic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801cx_enable_serial_irqs(dev); @@ -229,13 +225,28 @@ static void i82801cx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801cx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801cx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801cx_general_cntl(dev); + + /* Prevent LPC disabling, enable parity errors, and SERR# (System Error). */ + pci_write_config16(dev, PCI_COMMAND, 0x014f); +} + static struct device_operations lpc_ops = { - .read_resources = i82801cx_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = 0, + .read_resources = i82801cx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801cx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = 0, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index a38c793..2484eb1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -86,6 +86,7 @@ extern void i82801dx_enable(device_t dev); #define PMBASE_ADDR 0x0400 #define DEFAULT_PMBASE PMBASE_ADDR #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 768e700..eec984d 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -36,37 +36,37 @@ typedef struct southbridge_intel_i82801dx_config config_t; -static void i82801dx_enable_ioapic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801dx_enable_acpi(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801dx_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801dx_enable_serial_irqs(struct device *dev) @@ -264,11 +264,8 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801dx_enable_ioapic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801dx_enable_serial_irqs(dev); @@ -323,10 +320,25 @@ static void i82801dx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801dx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801dx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801dx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801dx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801dx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801dx_enable, diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..22a29f3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -12,4 +12,13 @@ extern void i82801ex_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4) + + #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..81d8aef 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,8 +12,6 @@ #include #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 #define NMI_OFF 0 #define MAINBOARD_POWER_OFF 0 @@ -23,6 +21,52 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif +typedef struct southbridge_intel_i82801ex_config config_t; + +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801ex_enable_acpi(struct device *dev) +{ + u8 gpio_cntl; +#if 0 + /* many i82801's set pmbase here */ + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); +#endif + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + /* Enable the GPIO bar */ + gpio_cntl = pci_read_config8(dev, GPIO_CNTL); + gpio_cntl |= GPIO_EN; + pci_write_config8(dev, GPIO_CNTL, gpio_cntl); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC configuration registers + */ +static void i82801ex_general_cntl(struct device *dev) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + + reg32 = pci_read_config32(dev, GEN_STS); + reg32 |= (1<<1); + pci_write_config32(dev, GEN_STS, reg32); + +} + #define SERIRQ_CNTL 0x64 static void i82801ex_enable_serial_irqs(device_t dev) { @@ -45,7 +89,6 @@ static void i82801ex_enable_lpc(device_t dev) pci_write_config8(dev, LPC_EN, 0x0d); } -typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( device_t dev, struct resource *res, config_t *config) @@ -193,7 +236,7 @@ static void i82801ex_gpio_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); + res = find_resource(dev, GPIO_BASE); if (!res) { return; } @@ -239,17 +282,10 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { uint8_t byte; - uint32_t value; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - /* IO APIC initialization */ - value = pci_read_config32(dev, 0xd0); - value |= (1 << 8)|(1<<7)|(1<<1); - pci_write_config32(dev, 0xd0, value); - value = pci_read_config32(dev, 0xd4); - value |= (1<<1); - pci_write_config32(dev, 0xd4, value); - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. + /* IO APIC initialization. */ + setup_ioapic(IO_APIC_ADDR, 0); /* No APIC ID ?? */ i82801ex_enable_serial_irqs(dev); @@ -295,10 +331,10 @@ static void i82801ex_lpc_read_resources(device_t dev) pci_dev_read_resources(dev); /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); + res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); + res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -321,20 +357,14 @@ static void i82801ex_lpc_read_resources(device_t dev) static void i82801ex_lpc_enable_resources(device_t dev) { - uint8_t acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ + /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 4); - pci_write_config8(dev, 0x44, acpi_cntl); + /* Enable ACPI and GPIO BARs. */ + i82801ex_enable_acpi(dev); - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x5c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x5c, gpio_cntl); + /* Set features (most important: IOAPIC). */ + i82801ex_general_cntl(dev); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 8fb5b92..7b93cbd 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -81,6 +81,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) /* NOTE: was 1<<4 until ICH7 */ #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c6b76d3..882fafe 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); +#if 0 + /* many i82801's set pmbase here */ + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); +#endif - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 + /* Enable ACPI I/O range decode and ACPI power management. + * Select SCI IRQ as IRQ9. */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC configuration registers + */ +static void i82801gx_general_cntl(struct device *dev) +{ + u32 reg32 = 0xABADBEEF; + + /* FIXME: Who sets OIC register @ 0x3155 ?? + */ + printk(BIOS_DEBUG, "Southbridge OIC 0x%08x.\n", reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -418,11 +419,8 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801gx_enable_serial_irqs(dev); @@ -502,6 +500,21 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void i82801gx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801gx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801gx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -509,7 +522,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801gx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable, From gerrit at coreboot.org Wed Feb 1 16:35:17 2012 From: gerrit at coreboot.org (Bernhard Urban (lewurm@gmail.com)) Date: Wed, 1 Feb 2012 16:35:17 +0100 Subject: [coreboot] New patch to review for coreboot: 6ec51f8 romcc: kill gcc warnings and .gitignore generated files References: Message-ID: Bernhard Urban (lewurm at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/605 -gerrit commit 6ec51f82110a88ffd5443c5fa6b8aa9ebad357b9 Author: Bernhard Urban Date: Wed Feb 1 16:30:30 2012 +0100 romcc: kill gcc warnings and .gitignore generated files don't remove calls to `flatten()' and `correct_coalesce_conflicts()', since they (probably) have side effects. Change-Id: I78fc4163b3f5f1f5f3c5153f9559c22e11e8344d Signed-off-by: Bernhard Urban --- .gitignore | 3 +++ util/romcc/romcc.c | 51 ++++++++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 33 deletions(-) diff --git a/.gitignore b/.gitignore index a08cb12..8e259c7 100644 --- a/.gitignore +++ b/.gitignore @@ -44,3 +44,6 @@ util/msrtool/msrtool util/nvramtool/.dependencies util/nvramtool/nvramtool util/superiotool/superiotool +util/romcc/romcc +util/romcc/tests/*.S-O2-mmmx +util/romcc/tests/fail_test*.S diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 7eced78..c7ef223 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -4080,12 +4080,10 @@ static void raw_next_token(struct compile_state *state, } /* string constants */ else if ((c == '"') || ((c == 'L') && (c1 == '"'))) { - int wchar, multiline; + int multiline; - wchar = 0; multiline = 0; if (c == 'L') { - wchar = 1; tokp = next_char(file, tokp, 1); } while((c = get_char(file, tokp)) != -1) { @@ -4113,12 +4111,10 @@ static void raw_next_token(struct compile_state *state, } /* character constants */ else if ((c == '\'') || ((c == 'L') && (c1 == '\''))) { - int wchar, multiline; + int multiline; - wchar = 0; multiline = 0; if (c == 'L') { - wchar = 1; tokp = next_char(file, tokp, 1); } while((c = get_char(file, tokp)) != -1) { @@ -4897,13 +4893,11 @@ static void raw_token(struct compile_state *state, struct token *tk) static void pp_token(struct compile_state *state, struct token *tk) { - struct file_state *file; int rescan; raw_token(state, tk); do { rescan = 0; - file = state->file; if (tk->tok == TOK_SPACE) { raw_token(state, tk); rescan = 1; @@ -7509,7 +7503,6 @@ static struct triple *write_expr( struct compile_state *state, struct triple *dest, struct triple *rval) { struct triple *def; - int op; def = 0; if (!rval) { @@ -7532,7 +7525,6 @@ static struct triple *write_expr( } /* Now figure out which assignment operator to use */ - op = -1; if (is_in_reg(state, dest)) { def = triple(state, OP_WRITE, dest->type, rval, dest); if (MISC(def, 0) != dest) { @@ -9168,8 +9160,10 @@ static struct triple *decompose_index(struct compile_state *state, static void decompose_compound_types(struct compile_state *state) { struct triple *ins, *next, *first; +#if DEBUG_DECOMPOSE_HIRES FILE *fp; fp = state->dbgout; +#endif first = state->first; ins = first; @@ -10462,7 +10456,7 @@ static void register_builtin_function(struct compile_state *state, const char *name, int op, struct type *rtype, ...) { struct type *ftype, *atype, *ctype, *crtype, *param, **next; - struct triple *def, *arg, *result, *work, *last, *first, *retvar, *ret; + struct triple *def, *result, *work, *first, *retvar, *ret; struct hash_entry *ident; struct file_state file; int parameters; @@ -10530,7 +10524,7 @@ static void register_builtin_function(struct compile_state *state, } else { atype = param; } - arg = flatten(state, first, variable(state, atype)); + flatten(state, first, variable(state, atype)); param = param->right; } work = new_triple(state, op, rtype, -1, parameters); @@ -10542,7 +10536,7 @@ static void register_builtin_function(struct compile_state *state, work = write_expr(state, deref_index(state, result, 1), work); } work = flatten(state, first, work); - last = flatten(state, first, label(state)); + flatten(state, first, label(state)); ret = flatten(state, first, ret); name_len = strlen(name); ident = lookup(state, name, name_len); @@ -13309,7 +13303,7 @@ static void resolve_branches(struct compile_state *state, struct triple *first) static struct triple *function_definition( struct compile_state *state, struct type *type) { - struct triple *def, *tmp, *first, *end, *retvar, *result, *ret; + struct triple *def, *tmp, *first, *end, *retvar, *ret; struct triple *fname; struct type *fname_type; struct hash_entry *ident; @@ -13365,7 +13359,7 @@ static struct triple *function_definition( /* Remove all type qualifiers from the return type */ new_type(TYPE_PRODUCT, ctype, clone_type(0, type->left)), 0); crtype->elements = 2; - result = flatten(state, end, variable(state, crtype)); + flatten(state, end, variable(state, crtype)); /* Allocate a variable for the return address */ retvar = flatten(state, end, variable(state, &void_ptr_type)); @@ -14326,8 +14320,7 @@ static void expand_function_call( struct triple *func, *func_first, *func_last, *retvar; struct triple *first; struct type *ptype, *rtype; - struct triple *jmp; - struct triple *ret_addr, *ret_loc, *ret_set; + struct triple *ret_addr, *ret_loc; struct triple_reg_set *enclose, *set; int closure_idx, pvals, i; @@ -14429,8 +14422,8 @@ static void expand_function_call( } ret_addr = flatten(state, ret_loc, ret_addr); - ret_set = flatten(state, ret_loc, write_expr(state, retvar, ret_addr)); - jmp = flatten(state, ret_loc, + flatten(state, ret_loc, write_expr(state, retvar, ret_addr)); + flatten(state, ret_loc, call(state, retvar, ret_addr, func_first, func_last)); /* Find the result */ @@ -14745,7 +14738,7 @@ struct triple *output_asm(struct compile_state *state) static void join_functions(struct compile_state *state) { - struct triple *jmp, *start, *end, *call, *in, *out, *func; + struct triple *start, *end, *call, *in, *out, *func; struct file_state file; struct type *pnext, *param; struct type *result_type, *args_type; @@ -14870,7 +14863,7 @@ static void join_functions(struct compile_state *state) walk_functions(state, insert_function, end); if (start->next != end) { - jmp = flatten(state, start, branch(state, end, 0)); + flatten(state, start, branch(state, end, 0)); } /* OK now the functions have been joined. */ @@ -17911,10 +17904,9 @@ static void awaken( static void eliminate_inefectual_code(struct compile_state *state) { - struct block *block; struct dead_triple *dtriple, *work_list, **work_list_tail, *dt; int triples, i; - struct triple *first, *final, *ins; + struct triple *first, *ins; if (!(state->compiler->flags & COMPILER_ELIMINATE_INEFECTUAL_CODE)) { return; @@ -17925,7 +17917,6 @@ static void eliminate_inefectual_code(struct compile_state *state) work_list_tail = &work_list; first = state->first; - final = state->first->prev; /* Count how many triples I have */ triples = count_triples(state); @@ -17935,7 +17926,6 @@ static void eliminate_inefectual_code(struct compile_state *state) ins = first; i = 1; - block = 0; do { dtriple[i].triple = ins; dtriple[i].block = block_of_triple(state, ins); @@ -18293,8 +18283,6 @@ static void print_interference_block( for(done = 0, ptr = block->first; !done; ptr = ptr->next) { struct live_range *lr; unsigned id; - int op; - op = ptr->op; done = (ptr == block->last); lr = rstate->lrd[ptr->id].lr; @@ -20085,7 +20073,6 @@ static void allocate_registers(struct compile_state *state) do { struct live_range **point, **next; - int conflicts; int tangles; int coalesced; @@ -20105,7 +20092,7 @@ static void allocate_registers(struct compile_state *state) rstate.blocks = compute_variable_lifetimes(state, &state->bb); /* Fix invalid mandatory live range coalesce conflicts */ - conflicts = correct_coalesce_conflicts(state, rstate.blocks); + correct_coalesce_conflicts(state, rstate.blocks); /* Fix two simultaneous uses of the same register. * In a few pathlogical cases a partial untangle moves @@ -23186,13 +23173,12 @@ struct reg_info arch_reg_rhs(struct compile_state *state, struct triple *ins, in static struct triple *mod_div(struct compile_state *state, struct triple *ins, int div_op, int index) { - struct triple *div, *piece0, *piece1; + struct triple *div, *piece1; /* Generate the appropriate division instruction */ div = post_triple(state, ins, div_op, ins->type, 0, 0); RHS(div, 0) = RHS(ins, 0); RHS(div, 1) = RHS(ins, 1); - piece0 = LHS(div, 0); piece1 = LHS(div, 1); div->template_id = TEMPLATE_DIV32; use_triple(RHS(div, 0), div); @@ -24393,11 +24379,10 @@ static void print_op_move(struct compile_state *state, if ((size_of(state, src->type) < size_of(state, dst->type)) && (is_signed(src->type))) { - int bits, reg_bits, shift_bits; + int reg_bits, shift_bits; int dst_reg; int dst_regcm; - bits = size_of(state, src->type); reg_bits = reg_size(state, dst); if (reg_bits > 32) { reg_bits = 32; From gerrit at coreboot.org Wed Feb 1 18:39:05 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 18:39:05 +0100 Subject: [coreboot] New patch to review for coreboot: 5025489 Copy existing cache_as_ram code References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 50254890e9ce191ac7a5820ad45cb2f2bade02e6 Author: Ky?sti M?lkki Date: Wed Feb 1 18:48:19 2012 +0200 Copy existing cache_as_ram code Use model_6ex/cache_as_ram.inc as a template for model_f2x with hyper-threading CPUs. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 265 +++++++++++++++++++++++++++++++++ 1 files changed, 265 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..18ada29 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + // movl $0x23322332, %eax + xorl %eax, %eax + rep stosl + + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif + movl %eax, %esp + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function. */ + call main + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + From gerrit at coreboot.org Wed Feb 1 18:39:06 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 18:39:06 +0100 Subject: [coreboot] New patch to review for coreboot: d26740b Apply cache-as-ram conditionally on socket mPGA604 References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607 -gerrit commit d26740b827bcd4b3621200f8a9c911a107857022 Author: Ky?sti M?lkki Date: Wed Feb 1 19:15:13 2012 +0200 Apply cache-as-ram conditionally on socket mPGA604 The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Makefile.inc | 8 +------- src/cpu/intel/socket_mPGA604/Kconfig | 16 ++++++++++++++++ src/cpu/intel/socket_mPGA604/Makefile.inc | 2 ++ 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 36f9d3a..420378b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..8f65a98 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,5 +1,10 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -14,3 +19,14 @@ config SSE2 bool default n depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..fb1cacd 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc + From gerrit at coreboot.org Wed Feb 1 18:39:06 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 1 Feb 2012 18:39:06 +0100 Subject: [coreboot] Patch set updated for coreboot: cf962a0 Add cache_as_ram_ht.inc with hyper-threading CPU support References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit cf962a0ff185cb8b1d04f4744a0bbd063d521cf5 Author: Ky?sti M?lkki Date: Wed Feb 1 19:08:23 2012 +0200 Add cache_as_ram_ht.inc with hyper-threading CPU support This variant of cache_as_ram.inc starts the sibling CPU processors and clears the cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. A secondary main (named main_no_xip) built into romstage can be executed with XIP cache disabled. On my test setup (Intel e7505) ECC scrub fails if run with XIP enabled. The code was developed for model_f25 from model_6ex. Some of the cache enable-disable logic seems spurious to me. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 192 +++++++++++++++++++++++++-------- 1 files changed, 149 insertions(+), 43 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 18ada29..3961535 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -3,6 +3,7 @@ * * Copyright (C) 2000,2007 Ronald G. Minnich * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Ky?sti M?lkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,22 +22,22 @@ #include #include #include +#include #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) -cache_as_ram: - post_code(0x20) + .code32 - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + /* Save the BIST result. */ + movl %eax, %ebp - /* Zero out all fixed range and variable range MTRRs. */ + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -55,6 +56,98 @@ clear_mtrrs: andl $(~0x00000cff), %eax wrmsr + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc cache_as_ram + bswapl %ebx + cmpb $01, %bh + jbe cache_as_ram + +hyper_threading_cpu: + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~0x0F), %edx /* MAXPHYWID = 36 */ + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jnz bsp_init + +ap_init: + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* MTRR registers are shared between HT siblings. */ + movl $0x300, %ecx + rdmsr + inc %eax + wrmsr + +ap_halt: + cli +1: hlt + jnz 1b + + +bsp_init: + /* Send INIT IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Send Start IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Wait for sibling CPU to start. */ +1: movl $0x300, %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + +sipi_complete: + +cache_as_ram: /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax @@ -67,36 +160,34 @@ clear_mtrrs: movl $0x0000000f, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $MTRRdefTypeEn, %eax wrmsr - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + /* Clear memory for stack. */ + cld xorl %eax, %eax + movl $(CACHE_AS_RAM_BASE), %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if 0 /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax + wbinvd movl %eax, %cr0 + wbinvd +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -117,32 +208,60 @@ clear_mtrrs: wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ - /* Enable cache. */ - movl %cr0, %eax +#if 0 + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif - /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax movl %esp, %ebp pushl %eax - post_code(0x23) + post_code(0x23); - /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f) +#if CONFIG_MAIN_WITHOUT_XIP + /* With Intel e7505 memory controller, hardware ECC scrub + * halts and/or flushes call stack if run with XIP enabled. + */ + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Disable Flash XIP. */ + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0, %edx + movl $0x0, %eax + wrmsr + invd + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + pushl $0x0 + call main_no_xip + addl $4, %esp + movl %esp, %ebp +#endif + post_code(0x30) /* Disable cache. */ @@ -159,20 +278,7 @@ clear_mtrrs: wrmsr post_code(0x31) - invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) From gerrit at coreboot.org Wed Feb 1 22:08:07 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Wed, 1 Feb 2012 22:08:07 +0100 Subject: [coreboot] Patch set updated for coreboot: 90c2980 Add Intel i5000 Memory Controller Hub References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491 -gerrit commit 90c2980b2e7902a4df6b0898fe64b3e3aa280735 Author: Sven Schnelle Date: Wed Feb 1 22:06:45 2012 +0100 Add Intel i5000 Memory Controller Hub Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle --- src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/i5000/Kconfig | 26 + src/northbridge/intel/i5000/Makefile.inc | 21 + src/northbridge/intel/i5000/chip.h | 23 + src/northbridge/intel/i5000/northbridge.c | 188 +++ src/northbridge/intel/i5000/raminit.c | 1771 +++++++++++++++++++++++++++++ src/northbridge/intel/i5000/raminit.h | 337 ++++++ src/northbridge/intel/i5000/udelay.c | 84 ++ 9 files changed, 2452 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 1809d11..31afe6a 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig source src/northbridge/intel/i855/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig +source src/northbridge/intel/i5000/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 0d116d0..c599dab 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig new file mode 100644 index 0000000..0595a57 --- /dev/null +++ b/src/northbridge/intel/i5000/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_I5000 + bool + select HAVE_DEBUG_RAM_SETUP + +config NORTHBRIDGE_INTEL_I5000_RAM_CHECK + bool + prompt "Run ramcheck after RAM initialization" diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc new file mode 100644 index 0000000..a5623c0 --- /dev/null +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c +romstage-y += raminit.c udelay.c diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h new file mode 100644 index 0000000..a23be90 --- /dev/null +++ b/src/northbridge/intel/i5000/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i5000_config { +}; + +extern struct chip_operations northbridge_intel_i5000_ops; diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c new file mode 100644 index 0000000..3db755c --- /dev/null +++ b/src/northbridge/intel/i5000/northbridge.c @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x25d8, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +#if CONFIG_WRITE_HIGH_TABLES +#include +#endif + +static void pci_domain_set_resources(device_t dev) +{ + struct resource *resource; + uint32_t hecbase, amsize, tolm; + uint64_t ambase, memsize; + int idx = 0; + device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + + tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16; + hecbase = pci_read_config16(dev16_0, 0x64) >> 12; + hecbase &= 0xffff; + + ambase = ((u64)pci_read_config32(dev16_0, 0x48) | + (u64)pci_read_config32(dev16_0, 0x4c) << 32); + + amsize = pci_read_config32(dev16_0, 0x50); + ambase &= 0x000000ffffff0000; + + printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase); + + /* Report the memory regions */ + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, ((tolm >> 10) - 768)); + + memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3, + pci_read_config16(dev16_1, 0x84) & ~3); + memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3); + + memsize <<= 24; + printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize); + if (memsize > 0xe0000000) { + memsize -= 0xe0000000; + printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576); + ram_resource(dev, idx++, 4096 * 1024, memsize / 1024); + } + + if (hecbase) { + printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28); + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)hecbase << 28; + resource->size = (resource_t)256 * 1024 * 1024; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)0xffe00000; + resource->size = (resource_t)0x200000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + if (ambase && amsize) { + resource = new_resource(dev, idx++); + resource->base = (resource_t)ambase; + resource->size = (resource_t)amsize; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + /* add resource for 0xfe6xxxxx range. This range is used by i5000 for + various fixed address registers (BOFL, SPAD, SPADS */ + resource = new_resource(dev, idx++); + resource->base = (resource_t)0xfe600000; + resource->size = (resource_t)0x00100000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + assign_resources(dev->link_list); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = tolm - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); +#endif +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i5000_ops = { + CHIP_NAME("Intel i5000 Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c new file mode 100644 index 0000000..2a04c7e --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.c @@ -0,0 +1,1771 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "raminit.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int i5000_for_each_channel(struct i5000_fbd_branch *branch, + int (*cb)(struct i5000_fbd_channel *)) +{ + struct i5000_fbd_channel *c; + int ret; + + for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++) + if (c->used && (ret = cb(c))) + return ret; + return 0; +} + +static int i5000_for_each_branch(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbd_branch *)) +{ + struct i5000_fbd_branch *b; + int ret; + + for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++) + if (b->used && (ret = cb(b))) + return ret; + return 0; +} + +static int i5000_for_each_dimm(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if ((ret = cb(d))) { + return ret; + } + } + return 0; +} + +static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if (d->present && (ret = cb(d))) + return ret; + } + return 0; +} + +static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) +{ + u16 status; + device_t dev = d->branch->branchdev; + + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + + while(count-- > 0) { + pci_write_config32(dev, cmdreg, 0xa8000000 | \ + (d->num & 0x03) << 24 | addr++ << 16); + + int timeout = 1000; + while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--) + udelay(10); + + if (status & I5000_SPD_SBE || !timeout) + return -1; + + if (status & I5000_SPD_RDO) { + *out = status & 0xff; + out++; + } + } + return 0; +} + +static void i5000_clear_fbd_errors(void) +{ + device_t dev16_1, dev16_2; + + dev16_1 = PCI_ADDR(0, 16, 1, 0); + dev16_2 = PCI_ADDR(0, 16, 2, 0); + + pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD, + pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD)); + + pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL)); + + pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL)); +} + +static int i5000_branch_reset(struct i5000_fbd_branch *b) +{ + device_t dev = b->branchdev; + + pci_write_config8(dev, I5000_FBDRST, 0x00); + + udelay(5000); + + pci_write_config8(dev, I5000_FBDRST, 0x05); + udelay(1); + pci_write_config8(dev, I5000_FBDRST, 0x04); + udelay(2); + pci_write_config8(dev, I5000_FBDRST, 0x05); + pci_write_config8(dev, I5000_FBDRST, 0x07); + return 0; +} + +static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del) +{ + int div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + return (del * 100) / div; +} + +static int mtb2clks(struct i5000_fbdimm *d, int del) +{ + int val, div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div); + if ((val % 10) > 0) + val += 10; + return val / 10; +} + +static int i5000_read_spd_data(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s; + u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr; + u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min; + u8 cmd2data_addr; + int t_ck_min, dimmsize; + + s = d->setup; + if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", + d->branch->num, d->channel->num, d->num); + return 0; // No FBDIMM present + } + + if (val != 0x09) + return 0; // SDRAM type not FBDIMM + + if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes)) + return 0; + + switch(d->setup->ddr_speed) { + case DDR_533MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_533; + break; + + case DDR_667MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_667; + break; + + default: + printk(BIOS_ERR, "Unsupported FBDIMM clock\n"); + return -1; + } + + if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) || + spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) || + spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) || + spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) || + spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) || + spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) || + spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) || + spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) || + spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) || + spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) || + spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) || + spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) || + spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) || + spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) || + spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) || + spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) || + spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) || + spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) || + spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) { + printk(BIOS_ERR, "failed to read data from SPD\n"); + return 0; + } + + + t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor; + if (t_ck_min <= 300) + d->speed = DDR_667MHZ; + else if (t_ck_min <= 375) + d->speed = DDR_533MHZ; + else { + printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min); + return -1; + } + + d->sdram_width = org & 0x07; + if (d->sdram_width > 1) { + printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width); + return 0; + } + + s->ddr_speed = MIN(s->ddr_speed, d->speed); + + d->banks = 4 << (addr & 0x03); + d->columns = 9 + ((addr >> 2) & 0x03); + d->rows = 12 + ((addr >> 5) & 0x03); + d->ranks = (org >> 3) & 0x03; + d->min_cas_latency = cas & 0x0f; + + d->setup->bl &= bl; + + if (!d->setup->bl) { + printk(BIOS_ERR, "no compatible burst length found\n"); + return -1; + } + + s->t_rc = MAX(s->t_rc, mtb2clks(d, + t_rc | ((t_ras_rc_h & 0xf0) << 4))); + s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd)); + s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc)); + s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd)); + s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min)); + s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr)); + s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp)); + s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp)); + s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr)); + s->t_ras = MAX(s->t_ras, mtb2clks(d, + t_ras | ((t_ras_rc_h & 0x0f) << 8))); + s->t_r2r = MAX(s->t_r2r, bb & 3); + s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3); + s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3); + + d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20; + dimmsize = d->ranksize * d->ranks; + d->branch->totalmem += dimmsize; + s->totalmem += dimmsize; + + d->channel->columns = d->columns; + d->channel->rows = d->rows; + d->channel->ranks = d->ranks; + d->channel->banks = d->banks; + d->channel->width = d->sdram_width; + + printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, " + "%d columns, %d rows, %d ranks\n", + d->branch->num, d->channel->num, d->num, dimmsize, + d->banks, d->columns, d->rows, d->ranks); + + d->present = 1; + d->branch->used |= 1; + d->channel->used |= 1; + d->channel->highest_amb = d->num; + return 0; +} + +static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16) | (byte2 << 8) | 1); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if (status & I5000_SPD_WOD && timeout) + return 0; + + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, byte2, status); + for(;;); + return -1; +} + +static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16)); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if ((status & I5000_SPD_RDO) && timeout) + *out = status & 0xff; + + if (status & I5000_SPD_SBE || !timeout) { + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, status); + for(;;); + return -1; + } + return 0; + +} + +static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u8 val) +{ + if (i5000_amb_smbus_write(d, 0x84, 00) || + i5000_amb_smbus_write(d, 0x04, fn) || + i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x04, reg & 0xff) || + i5000_amb_smbus_write(d, 0x44, val)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u16 val) +{ + if (i5000_amb_smbus_write(d, 0x88, 00) || + i5000_amb_smbus_write(d, 0x08, fn) || + i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x08, reg & 0xff) || + i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x48, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + if (i5000_amb_smbus_write(d, 0x8c, 00) || + i5000_amb_smbus_write(d, 0x0c, fn) || + i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, reg & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x4c, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 *val) +{ + u8 byte3, byte2, byte1, byte0; + + if (i5000_amb_smbus_write(d, 0x80, 00) || + i5000_amb_smbus_write(d, 0x00, fn) || + i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x40, reg & 0xff) || + i5000_amb_smbus_read(d, 0x80, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte2) || + i5000_amb_smbus_read(d, 0x00, &byte1) || + i5000_amb_smbus_read(d, 0x40, &byte0)) { + printk(BIOS_ERR, "AMB SMBUS read failed\n"); + return 1; + } + *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; + return 0; +} + +static void i5000_amb_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static u32 i5000_amb_read_config32(struct i5000_fbdimm *d, + int fn, int reg) +{ + return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)); +} + +static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command) +{ + u32 drc, status; + + printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...", + d->branch->num, d->channel->num, d->num, rank, command, addr); + + drc = i5000_amb_read_config32(d, 3, AMB_DRC); + drc &= ~((3 << 9) | (1 << 12)); + drc |= (rank << 9); + + command &= 0x0f; + command |= AMB_DCALCSR_START | (rank << 21); + + printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command); + i5000_amb_write_config32(d, 3, AMB_DRC, drc); + i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr); + i5000_amb_write_config32(d, 4, AMB_DCALCSR, command); + + udelay(1000); + while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR))) + & (1 << 31)); + + if (status & (1 << 30)) { + printk(BIOS_SPEW, "failed (status 0x%08x)\n", status); + return -1; + } + + printk(BIOS_SPEW, "done\n"); + return 0; +} + +static int i5000_ddr_calibration(struct i5000_fbdimm *d) +{ + u32 status; + + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) || + ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL)) + return -1; + return 0; +} + +static int i5000_ddr_init(struct i5000_fbdimm *d) +{ + + int rank; + u32 val; + u8 odt; + + for(rank = 0; rank < d->ranks; rank++) { + printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__, + d->branch->num, d->channel->num, d->num, rank); + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_NOP)) + return -1; + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + /* EMRS(2) */ + if (ddr_command(d, 1 << rank, + 2, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(3) */ + if (ddr_command(d, 1 << rank, + 3, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(1) */ + if (ddr_command(d, 1 << rank, + 1, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* MRS: DLL reset */ + if (ddr_command(d, 1 << rank, + 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + udelay(20); + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + if (ddr_command(d, 1 << rank, 0, + AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + /* burst length + cas latency */ + val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) | + (1 << 19) /* interleaved burst */ | + (d->setup->t_cl << 20) | + (((d->setup->t_wr - 1) & 7) << 25); + + printk(BIOS_DEBUG, "MRS: 0x%08x\n", val); + if (ddr_command(d, 1 << rank, + val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* OCD calibration default */ + if (ddr_command(d, 1 << rank, 0x03800001, + AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + + odt = d->odt; + if (rank) + odt >>= 4; + + val = (d->setup->t_al << 19) | + ((odt & 1) << 18) | + ((odt & 2) << 21) | 1; + + printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val); + + /* ODT, OCD exit, additive latency */ + if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + } + return 0; +} + +static int i5000_amb_preinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + u32 id, drc, fbdsbcfg = 0x0909; + + printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__, + d->branch->num, d->channel->num, d->num); + + i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]); + i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]); + + drc = (d->setup->t_al << 4) | (d->setup->t_cl); + printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, + d->cmd2datanxt[d->setup->ddr_speed]); + + switch(d->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651); + i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT, + d->cmd2datanxt[d->setup->ddr_speed]); + + i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc); + + if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) { + d->vendor = id & 0xffff; + d->device = id >> 16; + } + + pci_mmio_write_config8(d->branch->branchdev, + d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04); + return 0; +} + +static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) +{ + int timeout = 10000; + device_t dev = b->branchdev; + + printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state); + + pci_mmio_write_config8(dev, I5000_FBDHPC, state); + + printk(BIOS_DEBUG, "waiting for new state..."); + + while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--) + udelay(10); + + if (timeout) { + printk(BIOS_DEBUG, "done\n"); + return; + } + + printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n", + state, b->num); +} + +static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) +{ + int i = 10; + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDISTS1 : I5000_FBDISTS0); + + printk(BIOS_DEBUG, " waiting for pattern recognition..."); + while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0) + udelay(5000); + + printk(BIOS_DEBUG, i ? "done\n" : "failed\n"); + printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num, + pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f); + return !i; +} + +static const char *pattern_names[16] = { + "EI", "EI", "EI", "EI", + "EI", "EI", "EI", "EI", + "TS0", "TS1", "TS2", "TS3", + "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones", +}; + +static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait) +{ + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDICMD1 : I5000_FBDICMD0); + + printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", + c->branch->num, c->num, + pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern); + pci_mmio_write_config8(dev, 0, pattern); + + if (!wait) + return 0; + + return i5000_wait_pattern_recognized(c); +} + +static int i5000_set_ambpresent(struct i5000_fbd_channel *c) +{ + int i; + device_t branchdev = c->branch->branchdev; + u16 ambpresent = 0x8000; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + if (c->dimm[i].present) + ambpresent |= (1 << i); + } + + printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent); + pci_write_config16(branchdev, + c->num ? + I5000_AMBPRESENT1 : \ + I5000_AMBPRESENT0, ambpresent); + + return 0; +} + + +static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad) +{ + device_t branchdev = c->branch->branchdev; + int off = c->num ? 0x100 : 0; + u32 portctl; + int i, cnt = 1000; + + portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off); + portctl &= ~0x01000020; + if (mchpad) + portctl |= 0x00800000; + else + portctl &= ~0x00800000; + portctl &= ~0x01000020; + pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl); + + /* drive calibration patterns */ + if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1)) + return -1; + + while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--) + udelay(10); + + if (!cnt) { + printk(BIOS_ERR, "IBIST timeout\n"); + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + for(i = 0; i < highest_amb; i++) { + if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1))) + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1)) + return -1; + + if (i5000_set_ambpresent(c)) + return -1; + return 0; +} + +static int i5000_train_channel_idle(struct i5000_fbd_channel *c) +{ + int i; + u32 fbdsbcfg = 0x0b1b; + + switch(c->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + pci_mmio_write_config8(c->branch->branchdev, + c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05); + + for(i = 0; i < 4; i++) { + if (c->dimm[i].present) + i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg); + } + + return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1); +} + +static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 0); +} + +static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 1); +} + +static int i5000_setup_channel(struct i5000_fbd_channel *c) +{ + device_t branchdev = c->branch->branchdev; + int off = c->branch->num ? 0x100 : 0; + u32 val; + + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff); + pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff); + + pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db); + + /* unknown */ + val = pci_mmio_read_config32(branchdev, off + 0x0164); + val &= 0xfffbcffc; + val |= 0x4004; + pci_mmio_write_config32(branchdev, off + 0x164, val); + + pci_mmio_write_config32(branchdev, off + 0x15c, 0xff); + i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0); + return 0; +} + +static int i5000_link_training0(struct i5000_fbd_branch *b) +{ + device_t branchdev = b->branchdev; + + pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1); + + if (i5000_for_each_channel(b, i5000_setup_channel)) + return -1; + + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns0)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + +static int i5000_link_training1(struct i5000_fbd_branch *b) +{ + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns1)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + + +static int i5000_amb_check(struct i5000_fbdimm *d) +{ + u32 id = i5000_amb_read_config32(d, 0, 0); + + printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n", + d->branch->num, d->channel->num, d->num, + id & 0xffff, id >> 16); + + if ((id & 0xffff) != d->vendor || id >> 16 != d->device) { + printk(BIOS_ERR, "AMB mapping failed\n"); + return -1; + } + return 0; +} + +static int i5000_amb_postinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + + i5000_amb_write_config16(d, 1, 0xb6, p16[3]); + i5000_amb_write_config32(d, 1, 0xb8, p32[2]); + i5000_amb_write_config16(d, 1, 0xbc, p16[6]); + return 0; +} + +static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s; + u32 val, tref; + int refi; + + s = d->setup; + + printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n", + d->branch->num, d->channel->num, d->num); + + val = 0x44; + printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val); + i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val); + + val = (0x0c << 24) | /* CLK control */ + (1 << 18) | /* ODTZ enabled */ + (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */ + ((d->setup->t_al & 0x0f) << 4) | /* additive latency */ + (d->setup->t_cl & 0x0f); /* CAS latency */ + + if (d->ranks > 1) { + val |= (0x03 << 9); + } else { + val |= (0x01 << 9); + } + + printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRC, val); + + val = (d->sdram_width << 30) | + ((d->ranks == 2 ? 1 : 0) << 29) | + ((d->banks == 8 ? 1 : 0) << 28) | + ((d->rows - 13) << 26) | + ((d->columns - 10) << 24) | + (1 << 16) | /* Auto refresh exit */ + (0x27 << 8) | /* t_xsnr */ + (d->setup->t_rp << 4) | + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f); + + printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, val); + + tref = 15; + + switch(d->t_refi & 0x0f) { + case 0: + refi = 15625; + break; + case 1: + refi = 3900; + tref = 3; + break; + case 2: + refi = 7800; + tref = 7; + break; + case 3: + refi = 31250; + break; + case 4: + refi = 62500; + break; + case 5: + refi = 125000; + break; + default: + printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n", + d->t_refi & 0x0f); + refi = 7800; + break; + } + + s->t_ref = tref; + val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16); + + printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DAREFTC, val); + + u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) + + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor)); + u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr; + + val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) | + ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) | + ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) | + ((s->t_rtp - 2) << 27); + + switch(s->t_ras) { + case 15: + val |= (1 << 29); + break; + case 12: + val |= (2 << 29); + break; + default: + break; + } + + printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRT, val); + return 0; +} + +static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern) +{ + printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n", + d->branch->num, d->channel->num, d->num, rank, pattern); + + i5000_amb_write_config32(d, 3, AMB_DAREFTC, + i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000); + + i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678); + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8)); + return 0; +} + +static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank) +{ + int cnt = 1000; + u32 res; + + while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--) + udelay(1000); + + if (cnt && !(res & (1 << 30))) + return 0; + + printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n", + d->branch->num, d->channel->num, d->num, rank); + return -1; +} + +static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_start(d, 1, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d) +{ + + if (d->ranks < 2) + return 0; + if (i5000_do_amb_membist_start(d, 2, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_status1(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_status(d, 1)) + return -1; + return 0; +} + +static int i5000_amb_membist_status2(struct i5000_fbdimm *d) +{ + if (d->ranks < 2) + return 0; + + if (i5000_do_amb_membist_status(d, 2)) + return -1; + return 0; +} + +static int i5000_amb_membist_end(struct i5000_fbdimm *d) +{ + printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC)); + return 0; +} + +static int i5000_membist(struct i5000_fbd_setup *setup) +{ + return i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_end); +} + +static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d) +{ + u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC); + tmp &= ~(1 << 16); + printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp); + return 0; +} + +static int i5000_amb_clear_error_status(struct i5000_fbdimm *d) +{ + i5000_amb_write_config32(d, 1, AMB_FERR, 9); + i5000_amb_write_config32(d, 1, AMB_NERR, 9); + i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2); + i5000_amb_write_config8(d, 3, 0x80, 0xcf); + i5000_amb_write_config8(d, 3, 0x81, 0xd3); + i5000_amb_write_config8(d, 3, 0x82, 0xf8); + return 0; +} + +static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr) +{ + u32 val; + + if (c->dimm[0].present || c->dimm[1].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 2) | + (((c->ranks == 2) ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR0: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr, val); + } + + if (c->dimm[2].present || c->dimm[3].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 4) | + ((c->ranks ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR1: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr+2, val); + } +} + +static int get_dmir(u8 *rankmap, int *_set, int limit) +{ + int i, dmir = 0, set = 0; + + for(i = 7; set < limit && i >= 0; i--) { + if (!(*rankmap & (1 << i))) + continue; + + *rankmap &= ~(1 << i); + + switch(limit) { + case 1: + dmir |= (i | + (i << 3) | + (i << 6) | + (i << 9)); + break; + case 2: + dmir |= (i << (set * 3)) | + (i << (6 + set * 3)); + break; + case 4: + dmir |= (i << (set * 3)); + break; + + default: + break; + } + set++; + } + *_set = set; + return dmir; +} + +static int i5000_setup_dmir(struct i5000_fbd_branch *b) +{ + struct i5000_fbdimm *d; + device_t dev = b->branchdev; + u8 rankmap = 0, dmir = 0; + u32 dmirval = 0; + int i, set, rankoffset = 0, ranksize = 0, ranks = 0; + + if (!b->used) + return 0; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + rankmap >>= 2; + d = b->channel[0].dimm + i; + + if (!d->present) + continue; + + if (d->ranks == 2) { + rankmap |= 0xc0; + ranks += 2; + } else { + rankmap |= 0x40; + ranks++; + } + } + + printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap); + + dmir = I5000_DMIR0; + + ranksize = b->channel[0].dimm[0].ranksize << 8; + + if (!b->setup->single_channel) + ranksize <<= 1; + + while(ranks) { + + if (ranks >= 4) + dmirval = get_dmir(&rankmap, &set, 4); + else if (ranks >= 2) + dmirval = get_dmir(&rankmap, &set, 2); + else + dmirval = get_dmir(&rankmap, &set, 1); + + ranks -= set; + + dmirval |= rankoffset + (set * ranksize); + + rankoffset += (set * ranksize); + + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + dmir += 4; + } + + for(; dmir <= I5000_DMIR4; dmir += 4) { + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + } + return rankoffset; +} + +static void i5000_setup_interleave(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 mir0, mir1, mir2, size0, size1, minsize, tmp; + + size0 = i5000_setup_dmir(&setup->branch[1]) >> 12; + size1 = i5000_setup_dmir(&setup->branch[0]) >> 12; + + minsize = MIN(size0, size1); + + if (size0 > size1) { + tmp = size1; + size1 = size0; + size0 = tmp; + } + + if (size0 == size1) { + mir0 = (size0 << 1) | 3; + mir1 = (size0 << 1); + mir2 = (size0 << 1); + } else if (!size0) { + mir0 = size1 | 1; + mir1 = size1; + mir2 = size1; + } else { + mir0 = (size0 << 1) | 3; + mir1 = (size1 + size0) | 1; + mir2 = size1 + size0; + } + + printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + + pci_mmio_write_config16(dev16, I5000_MIR0, mir0); + pci_mmio_write_config16(dev16, I5000_MIR1, mir1); + pci_mmio_write_config16(dev16, I5000_MIR2, mir2); +} + +static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 tolm, drta, drtb, mc, mca; + int t_wrc, bl2; + + bl2 = (setup->bl & BL_BL8) ? 4 :2; + t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 + + setup->t_wr + setup->t_rp; + + drta = (setup->t_ref & 0x0f) | + ((setup->t_rrd & 0x0f) << 4) | + ((setup->t_rfc & 0xff) << 8) | + ((setup->t_rc & 0x3f) << 16) | + ((t_wrc & 0x3f) << 22) | + (setup->t_al & 0x07) << 28; + + drtb = (bl2) | + (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) | + (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) | + (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) | + (((bl2 + setup->t_w2rdr) & 0x07) << 16); + + mc = (1 << 30) | /* enable retry */ + (3 << 25) | /* bad RAM threshold */ + (1 << 21) | /* INITDONE */ + (1 << 20) | /* FSB enable */ + /* Electrical throttling: 20 clocks */ + ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) | + (1 << 8) | /* enhanced scrub mode */ + (1 << 7) | /* enable patrol scrub */ + (1 << 6) | /* enable demand scrubing */ + (1 << 5); /* enable northbound error detection */ + + printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc); + pci_mmio_write_config32(dev16, I5000_DRTA, drta); + pci_mmio_write_config32(dev16, I5000_DRTB, drtb); + pci_mmio_write_config32(dev16, I5000_MC, mc); + + mca = pci_mmio_read_config32(dev16, I5000_MCA); + + mca |= (7 << 28); + if (setup->single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca); + pci_mmio_write_config32(dev16, I5000_MCA, mca); + + pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff); + + i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1); + i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1); + + i5000_setup_interleave(setup); + + if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00) + tolm = 0xe00; + + tolm <<= 4; + printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm); + pci_mmio_write_config16(dev16, I5000_TOLM, tolm); + return 0; +} + +static void i5000_init_setup(struct i5000_fbd_setup *setup) +{ + int branch, channel, dimm, i = 0; + struct i5000_fbdimm *d; + struct i5000_fbd_channel *c; + struct i5000_fbd_branch *b; + + setup->bl = 3; + /* default to highest memory frequency. If a module doesn't + support it, it will decrease this setting in spd_read */ + setup->ddr_speed = DDR_667MHZ; + + for(branch = 0; branch < I5000_MAX_BRANCH; branch++) { + b = setup->branch + branch; + b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0); + b->setup = setup; + b->num = branch; + + for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) { + c = b->channel + channel; + c->branch = b; + c->setup = setup; + c->num = channel; + + for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) { + d = c->dimm + dimm; + setup->dimms[i++] = d; + d->channel = c; + d->branch = b; + d->setup = setup; + d->num = dimm; + d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11); + } + } + } +} + +static void i5000_reserved_register_init(struct i5000_fbd_setup *setup) +{ + /* register write captured from vendor BIOS, but undocument by Intel */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff); + + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000); + + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000); + + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007); + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f); + + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10); + + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042); + pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800); + + if (setup->branch[0].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[0].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10); + + if (setup->branch[1].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[1].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10); +} +static void i5000_dump_error_registers(void) +{ + device_t dev = PCI_ADDR(0, 16, 1, 0); + + printk(BIOS_ERR, "Dump of FBD error registers:\n" + "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" + "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n" + "EMASK_FBD: 0x%08x\n" + "ERR0_FBD: 0x%08x\n" + "ERR1_FBD: 0x%08x\n" + "ERR2_FBD: 0x%08x\n" + "MC_ERR_FBD: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_FERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_NERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_EMASK_FBD), + pci_mmio_read_config32(dev, I5000_ERR0_FBD), + pci_mmio_read_config32(dev, I5000_ERR1_FBD), + pci_mmio_read_config32(dev, I5000_ERR2_FBD), + pci_mmio_read_config32(dev, I5000_MCERR_FBD)); + + printk(BIOS_ERR, "Non recoverable error registers:\n" + "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n" + "NRECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECMEMA), + pci_mmio_read_config32(dev, I5000_NRECMEMB), + pci_mmio_read_config32(dev, I5000_NRECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "NRECFBDA: 0x%08x\n" + "NRECFBDB: 0x%08x\n" + "NRECFBDC: 0x%08x\n" + "NRECFBDD: 0x%08x\n" + "NRECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECFBDA), + pci_mmio_read_config32(dev, I5000_NRECFBDB), + pci_mmio_read_config32(dev, I5000_NRECFBDC), + pci_mmio_read_config32(dev, I5000_NRECFBDD), + pci_mmio_read_config32(dev, I5000_NRECFBDE)); + + printk(BIOS_ERR, "recoverable error registers:\n" + "RECMEMA: 0x%08x RECMEMB: 0x%08x\n" + "RECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECMEMA), + pci_mmio_read_config32(dev, I5000_RECMEMB), + pci_mmio_read_config32(dev, I5000_RECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "RECFBDA: 0x%08x\n" + "RECFBDB: 0x%08x\n" + "RECFBDC: 0x%08x\n" + "RECFBDD: 0x%08x\n" + "RECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECFBDA), + pci_mmio_read_config32(dev, I5000_RECFBDB), + pci_mmio_read_config32(dev, I5000_RECFBDC), + pci_mmio_read_config32(dev, I5000_RECFBDD), + pci_mmio_read_config32(dev, I5000_RECFBDE)); + +} + +static void i5000_try_restart(const char *msg) +{ + printk(BIOS_INFO, msg); + i5000_dump_error_registers(); +// outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); +} + +static void i5000_pam_setup(void) +{ + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33); +} + +static int i5000_setup_clocking(struct i5000_fbd_setup *setup) +{ + int fbd, fsb, ddrfrq, ddrfrqnow; + msr_t msr; + device_t dev = PCI_ADDR(0, 16, 1, 0); + + switch(setup->ddr_speed) { + case DDR_667MHZ: + fbd = 667; + break; + case DDR_533MHZ: + fbd = 533; + break; + default: + printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__); + return 1; + } + + /* mainboard specific callback */ + if (mainboard_set_fbd_clock(fbd)) { + printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__); + return 1; + } + + msr = rdmsr(0xcd); + + switch(msr.lo & 7) { + case 1: + fsb = 533; + break; + case 4: + fsb = 667; + break; + default: + printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7); + return 1; + } + + + ddrfrq = pci_mmio_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56); + ddrfrqnow = ddrfrq; + ddrfrq &= ~0x3; + + if (fsb < fbd) + ddrfrq |= 2; + else if (fsb > fbd) + ddrfrq |= 3; + + switch((ddrfrq >> 4) & 3) { + case 0: /* 1:1 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + case 2: /* 4:5 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04); + break; + case 3: + /* 5:4 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x10); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + default: + printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq); + return -1; + } + + if (ddrfrq != ddrfrqnow) { + printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n", + ddrfrqnow, ddrfrq); + pci_mmio_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); + /* FSB:FBD mapping changed, needs hard reset */ + outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); + } + return 0; +} + +void i5000_fbdimm_init(void) +{ + struct i5000_fbd_setup setup; + u32 mca, mc; + + memset(&setup, 0, sizeof(setup)); + + pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144); + + i5000_init_setup(&setup); + + pci_write_config32(PCI_DEV(0, 16, 0), 0xf0, + pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000); + + i5000_clear_fbd_errors(); + + printk(BIOS_INFO, "detecting memory modules\n"); + if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) { + printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__); + return; + } + + if (i5000_setup_clocking(&setup)) { + printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__); + return; + } + + /* posted CAS requires t_AL = t_RCD - 1 */ + setup.t_al = setup.t_rcd - 1; + + printk(BIOS_DEBUG, "global timing parameters:\n" + "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n" + "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n", + setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc, + setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r, + setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd, + setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al); + + setup.single_channel = (!(setup.branch[0].channel[1].used || + setup.branch[1].channel[0].used || + setup.branch[1].channel[1].used)); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0); + + /* enable or disable single channel mode */ + mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA); + if (setup.single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca); + + /* + * i5000 supports burst length 8 only in single channel mode + * so strip BL_BL8 if we're operating in multichannel mode + */ + + if (!setup.single_channel) + setup.bl &= ~BL_BL8; + + if (!setup.bl) + die("No supported burst length found\n"); + + mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC); + /* disable error checking for training */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20); + + printk(BIOS_INFO, "performing fbd link initialization..."); + if (i5000_for_each_branch(&setup, i5000_branch_reset) || + i5000_for_each_dimm_present(&setup, i5000_amb_preinit) || + i5000_for_each_branch(&setup, i5000_link_training0) || + i5000_for_each_dimm_present(&setup, i5000_amb_check) || + i5000_for_each_dimm_present(&setup, i5000_amb_postinit) || + i5000_for_each_branch(&setup, i5000_link_training1)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO, "done\n"); + printk(BIOS_INFO, "initializing memory..."); + + if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) || + i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) || + i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO,"done\n"); + printk(BIOS_INFO, "clearing memory..."); + + if (i5000_membist(&setup)) + i5000_try_restart("failed\n"); + else + printk(BIOS_INFO, "done\n"); + + if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh)) + i5000_try_restart("failed to enable auto refresh\n"); + + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT); + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_branch(&setup, i5000_link_training0)) + i5000_try_restart("Channel training failed\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY); + + i5000_clear_fbd_errors(); + + /* enable error checking */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20); + + i5000_dram_timing_init(&setup); + + i5000_reserved_register_init(&setup); + + i5000_pam_setup(); + + if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status)) + i5000_try_restart("failed to clear error status\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE); + +#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK + if (ram_check_nodie(0x000000, 0x0a0000) || + ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) { + i5000_try_restart("RAM verification failed"); + + } +#endif + + printk(BIOS_INFO, "Memory initialization finished\n"); +} diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h new file mode 100644 index 0000000..d3fa16a --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.h @@ -0,0 +1,337 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_I5000_RAMINIT_H +#define NORTHBRIDGE_I5000_RAMINIT_H + +#include +#include +#include + +#define I5000_MAX_BRANCH 2 +#define I5000_MAX_CHANNEL 2 +#define I5000_MAX_DIMM_PER_CHANNEL 4 +#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL) + +#define I5000_FBDRST 0x53 + +#define I5000_SPD_BUSY (1 << 12) +#define I5000_SPD_SBE (1 << 13) +#define I5000_SPD_WOD (1 << 14) +#define I5000_SPD_RDO (1 << 15) + +#define I5000_SPD0 0x74 +#define I5000_SPD1 0x76 + +#define I5000_SPDCMD0 0x78 +#define I5000_SPDCMD1 0x7c + +#define I5000_FBDHPC 0x4f +#define I5000_FBDST 0x4b + +#define I5000_FBDHPC_STATE_RESET 0x00 +#define I5000_FBDHPC_STATE_INIT 0x10 +#define I5000_FBDHPC_STATE_READY 0x20 +#define I5000_FBDHPC_STATE_ACTIVE 0x30 + +#define I5000_FBDISTS0 0x58 +#define I5000_FBDISTS1 0x5a + +#define I5000_FBDLVL0 0x44 +#define I5000_FBDLVL1 0x45 + +#define I5000_FBDICMD0 0x46 +#define I5000_FBDICMD1 0x47 + +#define I5000_FBDICMD_IDLE 0x00 +#define I5000_FBDICMD_TS0 0x80 +#define I5000_FBDICMD_TS1 0x90 +#define I5000_FBDICMD_TS2 0xa0 +#define I5000_FBDICMD_TS3 0xb0 +#define I5000_FBDICMD_TS2_MERGE 0xd0 +#define I5000_FBDICMD_TS2_NOMERGE 0xe0 +#define I5000_FBDICMD_ALL_ONES 0xf0 + +#define I5000_AMBPRESENT0 0x64 +#define I5000_AMBPRESENT1 0x66 + +#define I5000_FBDSBTXCFG0 0xc0 +#define I5000_FBDSBTXCFG1 0xc1 + +#define I5000_PROCENABLE 0xf0 +#define I5000_FBD0IBPORTCTL 0x180 +#define I5000_FBD0IBTXPAT2EN 0x1a8 +#define I5000_FBD0IBRXPAT2EN 0x1ac + +#define I5000_FBD0IBTXMSK 0x18c +#define I5000_FBD0IBRXMSK 0x190 + +#define I5000_FBDPLLCTRL 0x1c0 + +/* dev 16, function 1 registers */ +#define I5000_MC 0x40 +#define I5000_DRTA 0x48 +#define I5000_DRTB 0x4c +#define I5000_ERRPERR 0x50 +#define I5000_MCA 0x58 +#define I5000_TOLM 0x6c +#define I5000_MIR0 0x80 +#define I5000_MIR1 0x84 +#define I5000_MIR2 0x88 +#define I5000_AMIR0 0x8c +#define I5000_AMIR1 0x90 +#define I5000_AMIR2 0x94 + +#define I5000_FERR_FAT_FBD 0x98 +#define I5000_NERR_FAT_FBD 0x9c +#define I5000_FERR_NF_FBD 0xa0 +#define I5000_NERR_NF_FBD 0xa4 +#define I5000_EMASK_FBD 0xa8 +#define I5000_ERR0_FBD 0xac +#define I5000_ERR1_FBD 0xb0 +#define I5000_ERR2_FBD 0xb4 +#define I5000_MCERR_FBD 0xb8 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECMEMB 0xc0 +#define I5000_NRECFGLOG 0xc4 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECFBDA 0xc8 +#define I5000_NRECFBDB 0xcc +#define I5000_NRECFBDC 0xd0 +#define I5000_NRECFBDD 0xd4 +#define I5000_NRECFBDE 0xd8 + +#define I5000_REDMEMB 0x7c +#define I5000_RECMEMA 0xe2 +#define I5000_RECMEMB 0xe4 +#define I5000_RECFGLOG 0xe8 +#define I5000_RECFBDA 0xec +#define I5000_RECFBDB 0xf0 +#define I5000_RECFBDC 0xf4 +#define I5000_RECFBDD 0xf8 +#define I5000_RECFBDE 0xfc + +#define I5000_FBDTOHOSTGRCFG0 0x160 +#define I5000_FBDTOHOSTGRCFG1 0x164 +#define I5000_HOSTTOFBDGRCFG 0x168 +#define I5000_GRFBDLVLDCFG 0x16c +#define I5000_GRHOSTFULLCFG 0x16d +#define I5000_GRBUBBLECFG 0x16e +#define I5000_GRFBDTOHOSTDBLCFG 0x16f + +/* dev 16, function 2 registers */ +#define I5000_FERR_GLOBAL 0x40 +#define I5000_NERR_GLOBAL 0x44 + +/* dev 21, function 0 registers */ +#define I5000_MTR0 0x80 +#define I5000_MTR1 0x84 +#define I5000_MTR2 0x88 +#define I5000_MTR3 0x8c +#define I5000_DMIR0 0x90 +#define I5000_DMIR1 0x94 +#define I5000_DMIR2 0x98 +#define I5000_DMIR3 0x9c +#define I5000_DMIR4 0xa0 + +#define DEFAULT_AMBASE 0xfe000000 + +/* AMB function 1 registers */ +#define AMB_FBDSBCFGNXT 0x54 +#define AMB_FBDLOCKTO 0x68 +#define AMB_EMASK 0x8c +#define AMB_FERR 0x90 +#define AMB_NERR 0x94 +#define AMB_CMD2DATANXT 0xe8 + +/* AMB function 3 registers */ +#define AMB_DAREFTC 0x70 +#define AMB_DSREFTC 0x74 +#define AMB_DRT 0x78 +#define AMB_DRC 0x7c + +#define AMB_MBCSR 0x40 +#define AMB_MBADDR 0x44 +#define AMB_MBLFSRSED 0xa4 + +/* AMB function 4 registers */ +#define AMB_DCALCSR 0x40 +#define AMB_DCALADDR 0x44 +#define AMB_DCALCSR_START (1 << 31) + +#define AMB_DCALCSR_OPCODE_NOP 0x00 +#define AMB_DCALCSR_OPCODE_REFRESH 0x01 +#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 +#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 +#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05 +#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c +#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d + +#define AMB_DDR2ODTC 0xfc + +#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04 +#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07 +#define FBDIMM_SPD_FTB 0x08 +#define FBDIMM_SPD_MTB_DIVIDEND 0x09 +#define FBDIMM_SPD_MTB_DIVISOR 0x0a +#define FBDIMM_SPD_MIN_TCK 0x0b +#define FBDIMM_SPD_CAS_LATENCIES 0x0d +#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e +#define FBDIMM_SPD_T_WR 0x10 +#define FBDIMM_SPD_T_RCD 0x13 +#define FBDIMM_SPD_T_RRD 0x14 +#define FBDIMM_SPD_T_RP 0x15 +#define FBDIMM_SPD_T_RAS_RC_MSB 0x16 +#define FBDIMM_SPD_T_RAS 0x17 +#define FBDIMM_SPD_T_RC 0x18 +#define FBDIMM_SPD_T_RFC 0x19 +#define FBDIMM_SPD_T_WTR 0x1b +#define FBDIMM_SPD_T_RTP 0x1c +#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d +#define FBDIMM_SPD_ODT 0x4f +#define FBDIMM_SPD_T_REFI 0x20 +#define FBDIMM_SPD_T_BB 0x83 +#define FBDIMM_SPD_CMD2DATA_800 0x54 +#define FBDIMM_SPD_CMD2DATA_667 0x55 +#define FBDIMM_SPD_CMD2DATA_533 0x56 + +void i5000_fbdimm_init(void); + +#define I5000_BURST4 0x01 +#define I5000_BURST8 0x02 +#define I5000_BURST_CHOP 0x80 + +#define I5000_ODT_50 4 +#define I5000_ODT_75 2 +#define I5000_ODT_150 1 + +enum ddr_speeds { + DDR_533MHZ, + DDR_667MHZ, + DDR_MAX, +}; + +struct i5000_fbdimm { + struct i5000_fbd_branch *branch; + struct i5000_fbd_channel *channel; + struct i5000_fbd_setup *setup; + enum ddr_speeds speed; + int num; + int present:1; + u32 ambase; + + /* SPD data */ + u8 amb_personality_bytes[14]; + u8 banks; + u8 rows; + u8 columns; + u8 ranks; + u8 odt; + u8 sdram_width; + u8 mtb_divisor; + u8 mtb_dividend; + u8 t_ck_min; + u8 min_cas_latency; + u8 t_rrd; + u16 t_rfc; + u8 t_wtr; + u8 t_refi; + u8 cmd2datanxt[DDR_MAX]; + + u16 vendor; + u16 device; + + /* memory rank size in MB */ + int ranksize; +}; + +struct i5000_fbd_channel { + struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL]; + struct i5000_fbd_branch *branch; + struct i5000_fbd_setup *setup; + int num; + int used; + int highest_amb; + int columns; + int rows; + int ranks; + int banks; + int width; + /* memory size in MB on this channel */ + int totalmem; +}; + +struct i5000_fbd_branch { + struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; + struct i5000_fbd_setup *setup; + device_t branchdev; + int num; + int used; + /* memory size in MB on this branch */ + int totalmem; +}; + +enum odt { + ODT_150OHM=1, + ODT_50OHM=4, + ODT_75OHM=2, +}; + +enum bl { + BL_BL4=1, + BL_BL8=2, +}; + +struct i5000_fbd_setup { + struct i5000_fbd_branch branch[I5000_MAX_BRANCH]; + struct i5000_fbdimm *dimms[I5000_MAX_DIMMS]; + enum bl bl; + enum ddr_speeds ddr_speed; + + int single_channel:1; + u32 tolm; + + /* global SDRAM timing parameters */ + u8 t_al; + u8 t_cl; + u8 t_ras; + u8 t_wrc; + u8 t_rc; + u8 t_rfc; + u8 t_rrd; + u8 t_ref; + u8 t_w2rdr; + u8 t_r2w; + u8 t_w2r; + u8 t_r2r; + u8 t_w2w; + u8 t_wtr; + u8 t_rcd; + u8 t_rp; + u8 t_wr; + u8 t_rtp; + /* memory size in MB */ + int totalmem; +}; + +int mainboard_set_fbd_clock(int); +#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) +#endif diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c new file mode 100644 index 0000000..6462fe0 --- /dev/null +++ b/src/northbridge/intel/i5000/udelay.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ + + msr = rdmsr(0xcd); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + tsc = rdtsc(); + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +} From gerrit at coreboot.org Thu Feb 2 13:17:53 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Thu, 2 Feb 2012 13:17:53 +0100 Subject: [coreboot] Patch set updated for coreboot: 7832515 Add Intel i5000 Memory Controller Hub References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491 -gerrit commit 783251547346ae2e61749e8750a95f52cd81eec9 Author: Sven Schnelle Date: Wed Feb 1 22:06:45 2012 +0100 Add Intel i5000 Memory Controller Hub Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle --- src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/i5000/Kconfig | 26 + src/northbridge/intel/i5000/Makefile.inc | 21 + src/northbridge/intel/i5000/chip.h | 23 + src/northbridge/intel/i5000/northbridge.c | 188 +++ src/northbridge/intel/i5000/raminit.c | 1770 +++++++++++++++++++++++++++++ src/northbridge/intel/i5000/raminit.h | 337 ++++++ src/northbridge/intel/i5000/udelay.c | 84 ++ 9 files changed, 2451 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 1809d11..31afe6a 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig source src/northbridge/intel/i855/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig +source src/northbridge/intel/i5000/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 0d116d0..c599dab 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig new file mode 100644 index 0000000..0595a57 --- /dev/null +++ b/src/northbridge/intel/i5000/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_I5000 + bool + select HAVE_DEBUG_RAM_SETUP + +config NORTHBRIDGE_INTEL_I5000_RAM_CHECK + bool + prompt "Run ramcheck after RAM initialization" diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc new file mode 100644 index 0000000..a5623c0 --- /dev/null +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c +romstage-y += raminit.c udelay.c diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h new file mode 100644 index 0000000..a23be90 --- /dev/null +++ b/src/northbridge/intel/i5000/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i5000_config { +}; + +extern struct chip_operations northbridge_intel_i5000_ops; diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c new file mode 100644 index 0000000..3db755c --- /dev/null +++ b/src/northbridge/intel/i5000/northbridge.c @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x25d8, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +#if CONFIG_WRITE_HIGH_TABLES +#include +#endif + +static void pci_domain_set_resources(device_t dev) +{ + struct resource *resource; + uint32_t hecbase, amsize, tolm; + uint64_t ambase, memsize; + int idx = 0; + device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + + tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16; + hecbase = pci_read_config16(dev16_0, 0x64) >> 12; + hecbase &= 0xffff; + + ambase = ((u64)pci_read_config32(dev16_0, 0x48) | + (u64)pci_read_config32(dev16_0, 0x4c) << 32); + + amsize = pci_read_config32(dev16_0, 0x50); + ambase &= 0x000000ffffff0000; + + printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase); + + /* Report the memory regions */ + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, ((tolm >> 10) - 768)); + + memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3, + pci_read_config16(dev16_1, 0x84) & ~3); + memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3); + + memsize <<= 24; + printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize); + if (memsize > 0xe0000000) { + memsize -= 0xe0000000; + printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576); + ram_resource(dev, idx++, 4096 * 1024, memsize / 1024); + } + + if (hecbase) { + printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28); + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)hecbase << 28; + resource->size = (resource_t)256 * 1024 * 1024; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)0xffe00000; + resource->size = (resource_t)0x200000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + if (ambase && amsize) { + resource = new_resource(dev, idx++); + resource->base = (resource_t)ambase; + resource->size = (resource_t)amsize; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + /* add resource for 0xfe6xxxxx range. This range is used by i5000 for + various fixed address registers (BOFL, SPAD, SPADS */ + resource = new_resource(dev, idx++); + resource->base = (resource_t)0xfe600000; + resource->size = (resource_t)0x00100000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + assign_resources(dev->link_list); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = tolm - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); +#endif +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i5000_ops = { + CHIP_NAME("Intel i5000 Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c new file mode 100644 index 0000000..95610ce --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.c @@ -0,0 +1,1770 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "raminit.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int i5000_for_each_channel(struct i5000_fbd_branch *branch, + int (*cb)(struct i5000_fbd_channel *)) +{ + struct i5000_fbd_channel *c; + int ret; + + for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++) + if (c->used && (ret = cb(c))) + return ret; + return 0; +} + +static int i5000_for_each_branch(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbd_branch *)) +{ + struct i5000_fbd_branch *b; + int ret; + + for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++) + if (b->used && (ret = cb(b))) + return ret; + return 0; +} + +static int i5000_for_each_dimm(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if ((ret = cb(d))) { + return ret; + } + } + return 0; +} + +static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if (d->present && (ret = cb(d))) + return ret; + } + return 0; +} + +static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) +{ + u16 status; + device_t dev = d->branch->branchdev; + + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + + while(count-- > 0) { + pci_write_config32(dev, cmdreg, 0xa8000000 | \ + (d->num & 0x03) << 24 | addr++ << 16); + + int timeout = 1000; + while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--) + udelay(10); + + if (status & I5000_SPD_SBE || !timeout) + return -1; + + if (status & I5000_SPD_RDO) { + *out = status & 0xff; + out++; + } + } + return 0; +} + +static void i5000_clear_fbd_errors(void) +{ + device_t dev16_1, dev16_2; + + dev16_1 = PCI_ADDR(0, 16, 1, 0); + dev16_2 = PCI_ADDR(0, 16, 2, 0); + + pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD, + pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD)); + + pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL)); + + pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL)); +} + +static int i5000_branch_reset(struct i5000_fbd_branch *b) +{ + device_t dev = b->branchdev; + + pci_write_config8(dev, I5000_FBDRST, 0x00); + + udelay(5000); + + pci_write_config8(dev, I5000_FBDRST, 0x05); + udelay(1); + pci_write_config8(dev, I5000_FBDRST, 0x04); + udelay(2); + pci_write_config8(dev, I5000_FBDRST, 0x05); + pci_write_config8(dev, I5000_FBDRST, 0x07); + return 0; +} + +static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del) +{ + int div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + return (del * 100) / div; +} + +static int mtb2clks(struct i5000_fbdimm *d, int del) +{ + int val, div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div); + if ((val % 10) > 0) + val += 10; + return val / 10; +} + +static int i5000_read_spd_data(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s = d->setup; + u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr; + u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min; + u8 cmd2data_addr; + int t_ck_min, dimmsize; + + if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", + d->branch->num, d->channel->num, d->num); + return 0; // No FBDIMM present + } + + if (val != 0x09) + return -1; // SDRAM type not FBDIMM + + if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes)) + return -1; + + switch(s->ddr_speed) { + case DDR_533MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_533; + break; + + case DDR_667MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_667; + break; + + default: + printk(BIOS_ERR, "Unsupported FBDIMM clock\n"); + return -1; + } + + if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) || + spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) || + spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) || + spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) || + spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) || + spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) || + spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) || + spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) || + spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) || + spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) || + spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) || + spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) || + spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) || + spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) || + spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) || + spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) || + spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) || + spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) || + spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) { + printk(BIOS_ERR, "failed to read data from SPD\n"); + return 0; + } + + + t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor; + if (t_ck_min <= 300) + d->speed = DDR_667MHZ; + else if (t_ck_min <= 375) + d->speed = DDR_533MHZ; + else { + printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min); + return -1; + } + + d->sdram_width = org & 0x07; + if (d->sdram_width > 1) { + printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width); + return -1; + } + + if (s->ddr_speed == DDR_667MHZ && d->speed == DDR_533MHZ) + s->ddr_speed = DDR_533MHZ; + + d->banks = 4 << (addr & 0x03); + d->columns = 9 + ((addr >> 2) & 0x03); + d->rows = 12 + ((addr >> 5) & 0x03); + d->ranks = (org >> 3) & 0x03; + d->min_cas_latency = cas & 0x0f; + + s->bl &= bl; + + if (!s->bl) { + printk(BIOS_ERR, "no compatible burst length found\n"); + return -1; + } + + s->t_rc = MAX(s->t_rc, mtb2clks(d, + t_rc | ((t_ras_rc_h & 0xf0) << 4))); + s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd)); + s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc)); + s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd)); + s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min)); + s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr)); + s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp)); + s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp)); + s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr)); + s->t_ras = MAX(s->t_ras, mtb2clks(d, + t_ras | ((t_ras_rc_h & 0x0f) << 8))); + s->t_r2r = MAX(s->t_r2r, bb & 3); + s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3); + s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3); + + d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20; + dimmsize = d->ranksize * d->ranks; + d->branch->totalmem += dimmsize; + s->totalmem += dimmsize; + + d->channel->columns = d->columns; + d->channel->rows = d->rows; + d->channel->ranks = d->ranks; + d->channel->banks = d->banks; + d->channel->width = d->sdram_width; + + printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, " + "%d columns, %d rows, %d ranks\n", + d->branch->num, d->channel->num, d->num, dimmsize, + d->banks, d->columns, d->rows, d->ranks); + + d->present = 1; + d->branch->used |= 1; + d->channel->used |= 1; + d->channel->highest_amb = d->num; + return 0; +} + +static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16) | (byte2 << 8) | 1); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if (status & I5000_SPD_WOD && timeout) + return 0; + + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, byte2, status); + for(;;); + return -1; +} + +static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16)); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if ((status & I5000_SPD_RDO) && timeout) + *out = status & 0xff; + + if (status & I5000_SPD_SBE || !timeout) { + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, status); + return -1; + } + return 0; + +} + +static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u8 val) +{ + if (i5000_amb_smbus_write(d, 0x84, 00) || + i5000_amb_smbus_write(d, 0x04, fn) || + i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x04, reg & 0xff) || + i5000_amb_smbus_write(d, 0x44, val)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u16 val) +{ + if (i5000_amb_smbus_write(d, 0x88, 00) || + i5000_amb_smbus_write(d, 0x08, fn) || + i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x08, reg & 0xff) || + i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x48, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + if (i5000_amb_smbus_write(d, 0x8c, 00) || + i5000_amb_smbus_write(d, 0x0c, fn) || + i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, reg & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x4c, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 *val) +{ + u8 byte3, byte2, byte1, byte0; + + if (i5000_amb_smbus_write(d, 0x80, 00) || + i5000_amb_smbus_write(d, 0x00, fn) || + i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x40, reg & 0xff) || + i5000_amb_smbus_read(d, 0x80, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte2) || + i5000_amb_smbus_read(d, 0x00, &byte1) || + i5000_amb_smbus_read(d, 0x40, &byte0)) { + printk(BIOS_ERR, "AMB SMBUS read failed\n"); + return 1; + } + *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; + return 0; +} + +static void i5000_amb_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static u32 i5000_amb_read_config32(struct i5000_fbdimm *d, + int fn, int reg) +{ + return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)); +} + +static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command) +{ + u32 drc, status; + + printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...", + d->branch->num, d->channel->num, d->num, rank, command, addr); + + drc = i5000_amb_read_config32(d, 3, AMB_DRC); + drc &= ~((3 << 9) | (1 << 12)); + drc |= (rank << 9); + + command &= 0x0f; + command |= AMB_DCALCSR_START | (rank << 21); + + printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command); + i5000_amb_write_config32(d, 3, AMB_DRC, drc); + i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr); + i5000_amb_write_config32(d, 4, AMB_DCALCSR, command); + + udelay(1000); + while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR))) + & (1 << 31)); + + if (status & (1 << 30)) { + printk(BIOS_SPEW, "failed (status 0x%08x)\n", status); + return -1; + } + + printk(BIOS_SPEW, "done\n"); + return 0; +} + +static int i5000_ddr_calibration(struct i5000_fbdimm *d) +{ + u32 status; + + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) || + ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL)) + return -1; + return 0; +} + +static int i5000_ddr_init(struct i5000_fbdimm *d) +{ + + int rank; + u32 val; + u8 odt; + + for(rank = 0; rank < d->ranks; rank++) { + printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__, + d->branch->num, d->channel->num, d->num, rank); + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_NOP)) + return -1; + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + /* EMRS(2) */ + if (ddr_command(d, 1 << rank, + 2, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(3) */ + if (ddr_command(d, 1 << rank, + 3, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(1) */ + if (ddr_command(d, 1 << rank, + 1, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* MRS: DLL reset */ + if (ddr_command(d, 1 << rank, + 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + udelay(20); + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + if (ddr_command(d, 1 << rank, 0, + AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + /* burst length + cas latency */ + val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) | + (1 << 19) /* interleaved burst */ | + (d->setup->t_cl << 20) | + (((d->setup->t_wr - 1) & 7) << 25); + + printk(BIOS_DEBUG, "MRS: 0x%08x\n", val); + if (ddr_command(d, 1 << rank, + val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* OCD calibration default */ + if (ddr_command(d, 1 << rank, 0x03800001, + AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + + odt = d->odt; + if (rank) + odt >>= 4; + + val = (d->setup->t_al << 19) | + ((odt & 1) << 18) | + ((odt & 2) << 21) | 1; + + printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val); + + /* ODT, OCD exit, additive latency */ + if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + } + return 0; +} + +static int i5000_amb_preinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + u32 id, drc, fbdsbcfg = 0x0909; + + printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__, + d->branch->num, d->channel->num, d->num); + + i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]); + i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]); + + drc = (d->setup->t_al << 4) | (d->setup->t_cl); + printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, + d->cmd2datanxt[d->setup->ddr_speed]); + + switch(d->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651); + i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT, + d->cmd2datanxt[d->setup->ddr_speed]); + + i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc); + + if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) { + d->vendor = id & 0xffff; + d->device = id >> 16; + } + + pci_mmio_write_config8(d->branch->branchdev, + d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04); + return 0; +} + +static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) +{ + int timeout = 10000; + device_t dev = b->branchdev; + + printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state); + + pci_mmio_write_config8(dev, I5000_FBDHPC, state); + + printk(BIOS_DEBUG, "waiting for new state..."); + + while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--) + udelay(10); + + if (timeout) { + printk(BIOS_DEBUG, "done\n"); + return; + } + + printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n", + state, b->num); +} + +static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) +{ + int i = 10; + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDISTS1 : I5000_FBDISTS0); + + printk(BIOS_DEBUG, " waiting for pattern recognition..."); + while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0) + udelay(5000); + + printk(BIOS_DEBUG, i ? "done\n" : "failed\n"); + printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num, + pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f); + return !i; +} + +static const char *pattern_names[16] = { + "EI", "EI", "EI", "EI", + "EI", "EI", "EI", "EI", + "TS0", "TS1", "TS2", "TS3", + "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones", +}; + +static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait) +{ + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDICMD1 : I5000_FBDICMD0); + + printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", + c->branch->num, c->num, + pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern); + pci_mmio_write_config8(dev, 0, pattern); + + if (!wait) + return 0; + + return i5000_wait_pattern_recognized(c); +} + +static int i5000_set_ambpresent(struct i5000_fbd_channel *c) +{ + int i; + device_t branchdev = c->branch->branchdev; + u16 ambpresent = 0x8000; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + if (c->dimm[i].present) + ambpresent |= (1 << i); + } + + printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent); + pci_write_config16(branchdev, + c->num ? + I5000_AMBPRESENT1 : \ + I5000_AMBPRESENT0, ambpresent); + + return 0; +} + + +static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad) +{ + device_t branchdev = c->branch->branchdev; + int off = c->num ? 0x100 : 0; + u32 portctl; + int i, cnt = 1000; + + portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off); + portctl &= ~0x01000020; + if (mchpad) + portctl |= 0x00800000; + else + portctl &= ~0x00800000; + portctl &= ~0x01000020; + pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl); + + /* drive calibration patterns */ + if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1)) + return -1; + + while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--) + udelay(10); + + if (!cnt) { + printk(BIOS_ERR, "IBIST timeout\n"); + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + for(i = 0; i < highest_amb; i++) { + if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1))) + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1)) + return -1; + + if (i5000_set_ambpresent(c)) + return -1; + return 0; +} + +static int i5000_train_channel_idle(struct i5000_fbd_channel *c) +{ + int i; + u32 fbdsbcfg = 0x0b1b; + + switch(c->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + pci_mmio_write_config8(c->branch->branchdev, + c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05); + + for(i = 0; i < 4; i++) { + if (c->dimm[i].present) + i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg); + } + + return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1); +} + +static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 0); +} + +static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 1); +} + +static int i5000_setup_channel(struct i5000_fbd_channel *c) +{ + device_t branchdev = c->branch->branchdev; + int off = c->branch->num ? 0x100 : 0; + u32 val; + + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff); + pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff); + + pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db); + + /* unknown */ + val = pci_mmio_read_config32(branchdev, off + 0x0164); + val &= 0xfffbcffc; + val |= 0x4004; + pci_mmio_write_config32(branchdev, off + 0x164, val); + + pci_mmio_write_config32(branchdev, off + 0x15c, 0xff); + i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0); + return 0; +} + +static int i5000_link_training0(struct i5000_fbd_branch *b) +{ + device_t branchdev = b->branchdev; + + pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1); + + if (i5000_for_each_channel(b, i5000_setup_channel)) + return -1; + + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns0)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + +static int i5000_link_training1(struct i5000_fbd_branch *b) +{ + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns1)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + + +static int i5000_amb_check(struct i5000_fbdimm *d) +{ + u32 id = i5000_amb_read_config32(d, 0, 0); + + printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n", + d->branch->num, d->channel->num, d->num, + id & 0xffff, id >> 16); + + if ((id & 0xffff) != d->vendor || id >> 16 != d->device) { + printk(BIOS_ERR, "AMB mapping failed\n"); + return -1; + } + return 0; +} + +static int i5000_amb_postinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + + i5000_amb_write_config16(d, 1, 0xb6, p16[3]); + i5000_amb_write_config32(d, 1, 0xb8, p32[2]); + i5000_amb_write_config16(d, 1, 0xbc, p16[6]); + return 0; +} + +static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s; + u32 val, tref; + int refi; + + s = d->setup; + + printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n", + d->branch->num, d->channel->num, d->num); + + val = 0x44; + printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val); + i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val); + + val = (0x0c << 24) | /* CLK control */ + (1 << 18) | /* ODTZ enabled */ + (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */ + ((d->setup->t_al & 0x0f) << 4) | /* additive latency */ + (d->setup->t_cl & 0x0f); /* CAS latency */ + + if (d->ranks > 1) { + val |= (0x03 << 9); + } else { + val |= (0x01 << 9); + } + + printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRC, val); + + val = (d->sdram_width << 30) | + ((d->ranks == 2 ? 1 : 0) << 29) | + ((d->banks == 8 ? 1 : 0) << 28) | + ((d->rows - 13) << 26) | + ((d->columns - 10) << 24) | + (1 << 16) | /* Auto refresh exit */ + (0x27 << 8) | /* t_xsnr */ + (d->setup->t_rp << 4) | + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f); + + printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, val); + + tref = 15; + + switch(d->t_refi & 0x0f) { + case 0: + refi = 15625; + break; + case 1: + refi = 3900; + tref = 3; + break; + case 2: + refi = 7800; + tref = 7; + break; + case 3: + refi = 31250; + break; + case 4: + refi = 62500; + break; + case 5: + refi = 125000; + break; + default: + printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n", + d->t_refi & 0x0f); + refi = 7800; + break; + } + + s->t_ref = tref; + val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16); + + printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DAREFTC, val); + + u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) + + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor)); + u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr; + + val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) | + ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) | + ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) | + ((s->t_rtp - 2) << 27); + + switch(s->t_ras) { + case 15: + val |= (1 << 29); + break; + case 12: + val |= (2 << 29); + break; + default: + break; + } + + printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRT, val); + return 0; +} + +static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern) +{ + printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n", + d->branch->num, d->channel->num, d->num, rank, pattern); + + i5000_amb_write_config32(d, 3, AMB_DAREFTC, + i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000); + + i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678); + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8)); + return 0; +} + +static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank) +{ + int cnt = 1000; + u32 res; + + while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--) + udelay(1000); + + if (cnt && !(res & (1 << 30))) + return 0; + + printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n", + d->branch->num, d->channel->num, d->num, rank); + return -1; +} + +static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_start(d, 1, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d) +{ + + if (d->ranks < 2) + return 0; + if (i5000_do_amb_membist_start(d, 2, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_status1(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_status(d, 1)) + return -1; + return 0; +} + +static int i5000_amb_membist_status2(struct i5000_fbdimm *d) +{ + if (d->ranks < 2) + return 0; + + if (i5000_do_amb_membist_status(d, 2)) + return -1; + return 0; +} + +static int i5000_amb_membist_end(struct i5000_fbdimm *d) +{ + printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC)); + return 0; +} + +static int i5000_membist(struct i5000_fbd_setup *setup) +{ + return i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_end); +} + +static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d) +{ + u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC); + tmp &= ~(1 << 16); + printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp); + return 0; +} + +static int i5000_amb_clear_error_status(struct i5000_fbdimm *d) +{ + i5000_amb_write_config32(d, 1, AMB_FERR, 9); + i5000_amb_write_config32(d, 1, AMB_NERR, 9); + i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2); + i5000_amb_write_config8(d, 3, 0x80, 0xcf); + i5000_amb_write_config8(d, 3, 0x81, 0xd3); + i5000_amb_write_config8(d, 3, 0x82, 0xf8); + return 0; +} + +static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr) +{ + u32 val; + + if (c->dimm[0].present || c->dimm[1].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 2) | + (((c->ranks == 2) ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR0: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr, val); + } + + if (c->dimm[2].present || c->dimm[3].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 4) | + ((c->ranks ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR1: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr+2, val); + } +} + +static int get_dmir(u8 *rankmap, int *_set, int limit) +{ + int i, dmir = 0, set = 0; + + for(i = 7; set < limit && i >= 0; i--) { + if (!(*rankmap & (1 << i))) + continue; + + *rankmap &= ~(1 << i); + + switch(limit) { + case 1: + dmir |= (i | + (i << 3) | + (i << 6) | + (i << 9)); + break; + case 2: + dmir |= (i << (set * 3)) | + (i << (6 + set * 3)); + break; + case 4: + dmir |= (i << (set * 3)); + break; + + default: + break; + } + set++; + } + *_set = set; + return dmir; +} + +static int i5000_setup_dmir(struct i5000_fbd_branch *b) +{ + struct i5000_fbdimm *d; + device_t dev = b->branchdev; + u8 rankmap = 0, dmir = 0; + u32 dmirval = 0; + int i, set, rankoffset = 0, ranksize = 0, ranks = 0; + + if (!b->used) + return 0; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + rankmap >>= 2; + d = b->channel[0].dimm + i; + + if (!d->present) + continue; + + if (d->ranks == 2) { + rankmap |= 0xc0; + ranks += 2; + } else { + rankmap |= 0x40; + ranks++; + } + } + + printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap); + + dmir = I5000_DMIR0; + + ranksize = b->channel[0].dimm[0].ranksize << 8; + + if (!b->setup->single_channel) + ranksize <<= 1; + + while(ranks) { + + if (ranks >= 4) + dmirval = get_dmir(&rankmap, &set, 4); + else if (ranks >= 2) + dmirval = get_dmir(&rankmap, &set, 2); + else + dmirval = get_dmir(&rankmap, &set, 1); + + ranks -= set; + + dmirval |= rankoffset + (set * ranksize); + + rankoffset += (set * ranksize); + + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + dmir += 4; + } + + for(; dmir <= I5000_DMIR4; dmir += 4) { + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + } + return rankoffset; +} + +static void i5000_setup_interleave(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 mir0, mir1, mir2, size0, size1, minsize, tmp; + + size0 = i5000_setup_dmir(&setup->branch[1]) >> 12; + size1 = i5000_setup_dmir(&setup->branch[0]) >> 12; + + minsize = MIN(size0, size1); + + if (size0 > size1) { + tmp = size1; + size1 = size0; + size0 = tmp; + } + + if (size0 == size1) { + mir0 = (size0 << 1) | 3; + mir1 = (size0 << 1); + mir2 = (size0 << 1); + } else if (!size0) { + mir0 = size1 | 1; + mir1 = size1; + mir2 = size1; + } else { + mir0 = (size0 << 1) | 3; + mir1 = (size1 + size0) | 1; + mir2 = size1 + size0; + } + + printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + + pci_mmio_write_config16(dev16, I5000_MIR0, mir0); + pci_mmio_write_config16(dev16, I5000_MIR1, mir1); + pci_mmio_write_config16(dev16, I5000_MIR2, mir2); +} + +static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 tolm, drta, drtb, mc, mca; + int t_wrc, bl2; + + bl2 = (setup->bl & BL_BL8) ? 4 :2; + t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 + + setup->t_wr + setup->t_rp; + + drta = (setup->t_ref & 0x0f) | + ((setup->t_rrd & 0x0f) << 4) | + ((setup->t_rfc & 0xff) << 8) | + ((setup->t_rc & 0x3f) << 16) | + ((t_wrc & 0x3f) << 22) | + (setup->t_al & 0x07) << 28; + + drtb = (bl2) | + (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) | + (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) | + (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) | + (((bl2 + setup->t_w2rdr) & 0x07) << 16); + + mc = (1 << 30) | /* enable retry */ + (3 << 25) | /* bad RAM threshold */ + (1 << 21) | /* INITDONE */ + (1 << 20) | /* FSB enable */ + /* Electrical throttling: 20 clocks */ + ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) | + (1 << 8) | /* enhanced scrub mode */ + (1 << 7) | /* enable patrol scrub */ + (1 << 6) | /* enable demand scrubing */ + (1 << 5); /* enable northbound error detection */ + + printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc); + pci_mmio_write_config32(dev16, I5000_DRTA, drta); + pci_mmio_write_config32(dev16, I5000_DRTB, drtb); + pci_mmio_write_config32(dev16, I5000_MC, mc); + + mca = pci_mmio_read_config32(dev16, I5000_MCA); + + mca |= (7 << 28); + if (setup->single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca); + pci_mmio_write_config32(dev16, I5000_MCA, mca); + + pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff); + + i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1); + i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1); + + i5000_setup_interleave(setup); + + if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00) + tolm = 0xe00; + + tolm <<= 4; + printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm); + pci_mmio_write_config16(dev16, I5000_TOLM, tolm); + return 0; +} + +static void i5000_init_setup(struct i5000_fbd_setup *setup) +{ + int branch, channel, dimm, i = 0; + struct i5000_fbdimm *d; + struct i5000_fbd_channel *c; + struct i5000_fbd_branch *b; + + setup->bl = 3; + /* default to highest memory frequency. If a module doesn't + support it, it will decrease this setting in spd_read */ + setup->ddr_speed = DDR_667MHZ; + + for(branch = 0; branch < I5000_MAX_BRANCH; branch++) { + b = setup->branch + branch; + b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0); + b->setup = setup; + b->num = branch; + + for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) { + c = b->channel + channel; + c->branch = b; + c->setup = setup; + c->num = channel; + + for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) { + d = c->dimm + dimm; + setup->dimms[i++] = d; + d->channel = c; + d->branch = b; + d->setup = setup; + d->num = dimm; + d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11); + } + } + } +} + +static void i5000_reserved_register_init(struct i5000_fbd_setup *setup) +{ + /* register write captured from vendor BIOS, but undocument by Intel */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff); + + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000); + + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000); + + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007); + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f); + + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10); + + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042); + pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800); + + if (setup->branch[0].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[0].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10); + + if (setup->branch[1].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[1].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10); +} +static void i5000_dump_error_registers(void) +{ + device_t dev = PCI_ADDR(0, 16, 1, 0); + + printk(BIOS_ERR, "Dump of FBD error registers:\n" + "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" + "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n" + "EMASK_FBD: 0x%08x\n" + "ERR0_FBD: 0x%08x\n" + "ERR1_FBD: 0x%08x\n" + "ERR2_FBD: 0x%08x\n" + "MC_ERR_FBD: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_FERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_NERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_EMASK_FBD), + pci_mmio_read_config32(dev, I5000_ERR0_FBD), + pci_mmio_read_config32(dev, I5000_ERR1_FBD), + pci_mmio_read_config32(dev, I5000_ERR2_FBD), + pci_mmio_read_config32(dev, I5000_MCERR_FBD)); + + printk(BIOS_ERR, "Non recoverable error registers:\n" + "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n" + "NRECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECMEMA), + pci_mmio_read_config32(dev, I5000_NRECMEMB), + pci_mmio_read_config32(dev, I5000_NRECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "NRECFBDA: 0x%08x\n" + "NRECFBDB: 0x%08x\n" + "NRECFBDC: 0x%08x\n" + "NRECFBDD: 0x%08x\n" + "NRECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECFBDA), + pci_mmio_read_config32(dev, I5000_NRECFBDB), + pci_mmio_read_config32(dev, I5000_NRECFBDC), + pci_mmio_read_config32(dev, I5000_NRECFBDD), + pci_mmio_read_config32(dev, I5000_NRECFBDE)); + + printk(BIOS_ERR, "recoverable error registers:\n" + "RECMEMA: 0x%08x RECMEMB: 0x%08x\n" + "RECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECMEMA), + pci_mmio_read_config32(dev, I5000_RECMEMB), + pci_mmio_read_config32(dev, I5000_RECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "RECFBDA: 0x%08x\n" + "RECFBDB: 0x%08x\n" + "RECFBDC: 0x%08x\n" + "RECFBDD: 0x%08x\n" + "RECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECFBDA), + pci_mmio_read_config32(dev, I5000_RECFBDB), + pci_mmio_read_config32(dev, I5000_RECFBDC), + pci_mmio_read_config32(dev, I5000_RECFBDD), + pci_mmio_read_config32(dev, I5000_RECFBDE)); + +} + +static void i5000_try_restart(const char *msg) +{ + printk(BIOS_INFO, msg); + i5000_dump_error_registers(); +// outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); +} + +static void i5000_pam_setup(void) +{ + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33); +} + +static int i5000_setup_clocking(struct i5000_fbd_setup *setup) +{ + int fbd, fsb, ddrfrq, ddrfrqnow; + msr_t msr; + device_t dev = PCI_ADDR(0, 16, 1, 0); + + switch(setup->ddr_speed) { + case DDR_667MHZ: + fbd = 667; + break; + case DDR_533MHZ: + fbd = 533; + break; + default: + printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__); + return 1; + } + + /* mainboard specific callback */ + if (mainboard_set_fbd_clock(fbd)) { + printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__); + return 1; + } + + msr = rdmsr(0xcd); + + switch(msr.lo & 7) { + case 1: + fsb = 533; + break; + case 4: + fsb = 667; + break; + default: + printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7); + return 1; + } + + + ddrfrq = pci_mmio_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56); + ddrfrqnow = ddrfrq; + ddrfrq &= ~0x3; + + if (fsb < fbd) + ddrfrq |= 2; + else if (fsb > fbd) + ddrfrq |= 3; + + switch((ddrfrq >> 4) & 3) { + case 0: /* 1:1 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + case 2: /* 4:5 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04); + break; + case 3: + /* 5:4 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x10); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + default: + printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq); + return -1; + } + + if (ddrfrq != ddrfrqnow) { + printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n", + ddrfrqnow, ddrfrq); + pci_mmio_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); + /* FSB:FBD mapping changed, needs hard reset */ + outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); + } + return 0; +} + +void i5000_fbdimm_init(void) +{ + struct i5000_fbd_setup setup; + u32 mca, mc; + + memset(&setup, 0, sizeof(setup)); + + pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144); + + i5000_init_setup(&setup); + + pci_write_config32(PCI_DEV(0, 16, 0), 0xf0, + pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000); + + i5000_clear_fbd_errors(); + + printk(BIOS_INFO, "detecting memory modules\n"); + if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) { + printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__); + return; + } + + if (i5000_setup_clocking(&setup)) { + printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__); + return; + } + + /* posted CAS requires t_AL = t_RCD - 1 */ + setup.t_al = setup.t_rcd - 1; + + printk(BIOS_DEBUG, "global timing parameters:\n" + "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n" + "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n", + setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc, + setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r, + setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd, + setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al); + + setup.single_channel = (!(setup.branch[0].channel[1].used || + setup.branch[1].channel[0].used || + setup.branch[1].channel[1].used)); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0); + + /* enable or disable single channel mode */ + mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA); + if (setup.single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca); + + /* + * i5000 supports burst length 8 only in single channel mode + * so strip BL_BL8 if we're operating in multichannel mode + */ + + if (!setup.single_channel) + setup.bl &= ~BL_BL8; + + if (!setup.bl) + die("No supported burst length found\n"); + + mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC); + /* disable error checking for training */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20); + + printk(BIOS_INFO, "performing fbd link initialization..."); + if (i5000_for_each_branch(&setup, i5000_branch_reset) || + i5000_for_each_dimm_present(&setup, i5000_amb_preinit) || + i5000_for_each_branch(&setup, i5000_link_training0) || + i5000_for_each_dimm_present(&setup, i5000_amb_check) || + i5000_for_each_dimm_present(&setup, i5000_amb_postinit) || + i5000_for_each_branch(&setup, i5000_link_training1)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO, "done\n"); + printk(BIOS_INFO, "initializing memory..."); + + if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) || + i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) || + i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO,"done\n"); + printk(BIOS_INFO, "clearing memory..."); + + if (i5000_membist(&setup)) + i5000_try_restart("failed\n"); + else + printk(BIOS_INFO, "done\n"); + + if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh)) + i5000_try_restart("failed to enable auto refresh\n"); + + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT); + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_branch(&setup, i5000_link_training0)) + i5000_try_restart("Channel training failed\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY); + + i5000_clear_fbd_errors(); + + /* enable error checking */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20); + + i5000_dram_timing_init(&setup); + + i5000_reserved_register_init(&setup); + + i5000_pam_setup(); + + if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status)) + i5000_try_restart("failed to clear error status\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE); + +#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK + if (ram_check_nodie(0x000000, 0x0a0000) || + ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) { + i5000_try_restart("RAM verification failed"); + + } +#endif + + printk(BIOS_INFO, "Memory initialization finished\n"); +} diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h new file mode 100644 index 0000000..d3fa16a --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.h @@ -0,0 +1,337 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_I5000_RAMINIT_H +#define NORTHBRIDGE_I5000_RAMINIT_H + +#include +#include +#include + +#define I5000_MAX_BRANCH 2 +#define I5000_MAX_CHANNEL 2 +#define I5000_MAX_DIMM_PER_CHANNEL 4 +#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL) + +#define I5000_FBDRST 0x53 + +#define I5000_SPD_BUSY (1 << 12) +#define I5000_SPD_SBE (1 << 13) +#define I5000_SPD_WOD (1 << 14) +#define I5000_SPD_RDO (1 << 15) + +#define I5000_SPD0 0x74 +#define I5000_SPD1 0x76 + +#define I5000_SPDCMD0 0x78 +#define I5000_SPDCMD1 0x7c + +#define I5000_FBDHPC 0x4f +#define I5000_FBDST 0x4b + +#define I5000_FBDHPC_STATE_RESET 0x00 +#define I5000_FBDHPC_STATE_INIT 0x10 +#define I5000_FBDHPC_STATE_READY 0x20 +#define I5000_FBDHPC_STATE_ACTIVE 0x30 + +#define I5000_FBDISTS0 0x58 +#define I5000_FBDISTS1 0x5a + +#define I5000_FBDLVL0 0x44 +#define I5000_FBDLVL1 0x45 + +#define I5000_FBDICMD0 0x46 +#define I5000_FBDICMD1 0x47 + +#define I5000_FBDICMD_IDLE 0x00 +#define I5000_FBDICMD_TS0 0x80 +#define I5000_FBDICMD_TS1 0x90 +#define I5000_FBDICMD_TS2 0xa0 +#define I5000_FBDICMD_TS3 0xb0 +#define I5000_FBDICMD_TS2_MERGE 0xd0 +#define I5000_FBDICMD_TS2_NOMERGE 0xe0 +#define I5000_FBDICMD_ALL_ONES 0xf0 + +#define I5000_AMBPRESENT0 0x64 +#define I5000_AMBPRESENT1 0x66 + +#define I5000_FBDSBTXCFG0 0xc0 +#define I5000_FBDSBTXCFG1 0xc1 + +#define I5000_PROCENABLE 0xf0 +#define I5000_FBD0IBPORTCTL 0x180 +#define I5000_FBD0IBTXPAT2EN 0x1a8 +#define I5000_FBD0IBRXPAT2EN 0x1ac + +#define I5000_FBD0IBTXMSK 0x18c +#define I5000_FBD0IBRXMSK 0x190 + +#define I5000_FBDPLLCTRL 0x1c0 + +/* dev 16, function 1 registers */ +#define I5000_MC 0x40 +#define I5000_DRTA 0x48 +#define I5000_DRTB 0x4c +#define I5000_ERRPERR 0x50 +#define I5000_MCA 0x58 +#define I5000_TOLM 0x6c +#define I5000_MIR0 0x80 +#define I5000_MIR1 0x84 +#define I5000_MIR2 0x88 +#define I5000_AMIR0 0x8c +#define I5000_AMIR1 0x90 +#define I5000_AMIR2 0x94 + +#define I5000_FERR_FAT_FBD 0x98 +#define I5000_NERR_FAT_FBD 0x9c +#define I5000_FERR_NF_FBD 0xa0 +#define I5000_NERR_NF_FBD 0xa4 +#define I5000_EMASK_FBD 0xa8 +#define I5000_ERR0_FBD 0xac +#define I5000_ERR1_FBD 0xb0 +#define I5000_ERR2_FBD 0xb4 +#define I5000_MCERR_FBD 0xb8 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECMEMB 0xc0 +#define I5000_NRECFGLOG 0xc4 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECFBDA 0xc8 +#define I5000_NRECFBDB 0xcc +#define I5000_NRECFBDC 0xd0 +#define I5000_NRECFBDD 0xd4 +#define I5000_NRECFBDE 0xd8 + +#define I5000_REDMEMB 0x7c +#define I5000_RECMEMA 0xe2 +#define I5000_RECMEMB 0xe4 +#define I5000_RECFGLOG 0xe8 +#define I5000_RECFBDA 0xec +#define I5000_RECFBDB 0xf0 +#define I5000_RECFBDC 0xf4 +#define I5000_RECFBDD 0xf8 +#define I5000_RECFBDE 0xfc + +#define I5000_FBDTOHOSTGRCFG0 0x160 +#define I5000_FBDTOHOSTGRCFG1 0x164 +#define I5000_HOSTTOFBDGRCFG 0x168 +#define I5000_GRFBDLVLDCFG 0x16c +#define I5000_GRHOSTFULLCFG 0x16d +#define I5000_GRBUBBLECFG 0x16e +#define I5000_GRFBDTOHOSTDBLCFG 0x16f + +/* dev 16, function 2 registers */ +#define I5000_FERR_GLOBAL 0x40 +#define I5000_NERR_GLOBAL 0x44 + +/* dev 21, function 0 registers */ +#define I5000_MTR0 0x80 +#define I5000_MTR1 0x84 +#define I5000_MTR2 0x88 +#define I5000_MTR3 0x8c +#define I5000_DMIR0 0x90 +#define I5000_DMIR1 0x94 +#define I5000_DMIR2 0x98 +#define I5000_DMIR3 0x9c +#define I5000_DMIR4 0xa0 + +#define DEFAULT_AMBASE 0xfe000000 + +/* AMB function 1 registers */ +#define AMB_FBDSBCFGNXT 0x54 +#define AMB_FBDLOCKTO 0x68 +#define AMB_EMASK 0x8c +#define AMB_FERR 0x90 +#define AMB_NERR 0x94 +#define AMB_CMD2DATANXT 0xe8 + +/* AMB function 3 registers */ +#define AMB_DAREFTC 0x70 +#define AMB_DSREFTC 0x74 +#define AMB_DRT 0x78 +#define AMB_DRC 0x7c + +#define AMB_MBCSR 0x40 +#define AMB_MBADDR 0x44 +#define AMB_MBLFSRSED 0xa4 + +/* AMB function 4 registers */ +#define AMB_DCALCSR 0x40 +#define AMB_DCALADDR 0x44 +#define AMB_DCALCSR_START (1 << 31) + +#define AMB_DCALCSR_OPCODE_NOP 0x00 +#define AMB_DCALCSR_OPCODE_REFRESH 0x01 +#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 +#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 +#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05 +#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c +#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d + +#define AMB_DDR2ODTC 0xfc + +#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04 +#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07 +#define FBDIMM_SPD_FTB 0x08 +#define FBDIMM_SPD_MTB_DIVIDEND 0x09 +#define FBDIMM_SPD_MTB_DIVISOR 0x0a +#define FBDIMM_SPD_MIN_TCK 0x0b +#define FBDIMM_SPD_CAS_LATENCIES 0x0d +#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e +#define FBDIMM_SPD_T_WR 0x10 +#define FBDIMM_SPD_T_RCD 0x13 +#define FBDIMM_SPD_T_RRD 0x14 +#define FBDIMM_SPD_T_RP 0x15 +#define FBDIMM_SPD_T_RAS_RC_MSB 0x16 +#define FBDIMM_SPD_T_RAS 0x17 +#define FBDIMM_SPD_T_RC 0x18 +#define FBDIMM_SPD_T_RFC 0x19 +#define FBDIMM_SPD_T_WTR 0x1b +#define FBDIMM_SPD_T_RTP 0x1c +#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d +#define FBDIMM_SPD_ODT 0x4f +#define FBDIMM_SPD_T_REFI 0x20 +#define FBDIMM_SPD_T_BB 0x83 +#define FBDIMM_SPD_CMD2DATA_800 0x54 +#define FBDIMM_SPD_CMD2DATA_667 0x55 +#define FBDIMM_SPD_CMD2DATA_533 0x56 + +void i5000_fbdimm_init(void); + +#define I5000_BURST4 0x01 +#define I5000_BURST8 0x02 +#define I5000_BURST_CHOP 0x80 + +#define I5000_ODT_50 4 +#define I5000_ODT_75 2 +#define I5000_ODT_150 1 + +enum ddr_speeds { + DDR_533MHZ, + DDR_667MHZ, + DDR_MAX, +}; + +struct i5000_fbdimm { + struct i5000_fbd_branch *branch; + struct i5000_fbd_channel *channel; + struct i5000_fbd_setup *setup; + enum ddr_speeds speed; + int num; + int present:1; + u32 ambase; + + /* SPD data */ + u8 amb_personality_bytes[14]; + u8 banks; + u8 rows; + u8 columns; + u8 ranks; + u8 odt; + u8 sdram_width; + u8 mtb_divisor; + u8 mtb_dividend; + u8 t_ck_min; + u8 min_cas_latency; + u8 t_rrd; + u16 t_rfc; + u8 t_wtr; + u8 t_refi; + u8 cmd2datanxt[DDR_MAX]; + + u16 vendor; + u16 device; + + /* memory rank size in MB */ + int ranksize; +}; + +struct i5000_fbd_channel { + struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL]; + struct i5000_fbd_branch *branch; + struct i5000_fbd_setup *setup; + int num; + int used; + int highest_amb; + int columns; + int rows; + int ranks; + int banks; + int width; + /* memory size in MB on this channel */ + int totalmem; +}; + +struct i5000_fbd_branch { + struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; + struct i5000_fbd_setup *setup; + device_t branchdev; + int num; + int used; + /* memory size in MB on this branch */ + int totalmem; +}; + +enum odt { + ODT_150OHM=1, + ODT_50OHM=4, + ODT_75OHM=2, +}; + +enum bl { + BL_BL4=1, + BL_BL8=2, +}; + +struct i5000_fbd_setup { + struct i5000_fbd_branch branch[I5000_MAX_BRANCH]; + struct i5000_fbdimm *dimms[I5000_MAX_DIMMS]; + enum bl bl; + enum ddr_speeds ddr_speed; + + int single_channel:1; + u32 tolm; + + /* global SDRAM timing parameters */ + u8 t_al; + u8 t_cl; + u8 t_ras; + u8 t_wrc; + u8 t_rc; + u8 t_rfc; + u8 t_rrd; + u8 t_ref; + u8 t_w2rdr; + u8 t_r2w; + u8 t_w2r; + u8 t_r2r; + u8 t_w2w; + u8 t_wtr; + u8 t_rcd; + u8 t_rp; + u8 t_wr; + u8 t_rtp; + /* memory size in MB */ + int totalmem; +}; + +int mainboard_set_fbd_clock(int); +#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) +#endif diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c new file mode 100644 index 0000000..6462fe0 --- /dev/null +++ b/src/northbridge/intel/i5000/udelay.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ + + msr = rdmsr(0xcd); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + tsc = rdtsc(); + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +} From gerrit at coreboot.org Thu Feb 2 13:49:34 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 13:49:34 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7832515 Add Intel i5000 Memory Controller Hub References: Message-ID: the following patch was just integrated into master: commit 783251547346ae2e61749e8750a95f52cd81eec9 Author: Sven Schnelle Date: Wed Feb 1 22:06:45 2012 +0100 Add Intel i5000 Memory Controller Hub Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle Build-Tested: build bot (Jenkins) at Thu Feb 2 13:28:40 2012, giving +1 Reviewed-By: Sven Schnelle at Thu Feb 2 13:49:32 2012, giving +2 See http://review.coreboot.org/491 for details. -gerrit From gerrit at coreboot.org Thu Feb 2 13:54:39 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 13:54:39 +0100 Subject: [coreboot] Patch merged into coreboot/master: ac36286 RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code References: Message-ID: the following patch was just integrated into master: commit ac362862a3a19006e6d75471f1655f4aabc54dc9 Author: Kerry Sheh Date: Tue Jan 31 20:39:37 2012 +0800 RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code Change-Id: If9908ffeb5b707a660db38dc44f5118347cbcc06 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Reviewed-By: Patrick Georgi at Thu Feb 2 13:53:44 2012, giving +2 See http://review.coreboot.org/557 for details. -gerrit From gerrit at coreboot.org Thu Feb 2 15:05:37 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 15:05:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: 33b60dd SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code References: Message-ID: the following patch was just integrated into master: commit 33b60ddb3d34150cd8d5a962758b02dcfd0e2127 Author: Kerry Sheh Date: Wed Feb 1 13:55:13 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code Support AMD SB700 and SP5100 chipsets. Change-Id: I0955abf7f48a79483f624b46a61b22711315f888 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Reviewed-By: Patrick Georgi at Thu Feb 2 15:05:35 2012, giving +2 See http://review.coreboot.org/560 for details. -gerrit From gerrit at coreboot.org Thu Feb 2 15:10:08 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 15:10:08 +0100 Subject: [coreboot] Patch merged into coreboot/master: 425158e CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir References: Message-ID: the following patch was just integrated into master: commit 425158e483eb7ea8a5faf742742b42396ecd8fd4 Author: Kerry Sheh Date: Wed Feb 1 14:07:38 2012 +0800 CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir AGESA and CIMX build changed from commit 2a830d0b, sb800 and sb900 CIMX dir already traversed in vendorcode Makefile. Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Reviewed-By: Patrick Georgi at Thu Feb 2 15:10:05 2012, giving +2 See http://review.coreboot.org/602 for details. -gerrit From gerrit at coreboot.org Thu Feb 2 15:48:29 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 15:48:29 +0100 Subject: [coreboot] Patch merged into coreboot/master: 0d44787 libpayload: Refactor highlevel CMOS access References: Message-ID: the following patch was just integrated into master: commit 0d4478753226d92213f295b2cc72c2b098a5c279 Author: Patrick Georgi Date: Mon Jan 16 10:14:24 2012 +0100 libpayload: Refactor highlevel CMOS access This will allow using libpayload functions to access CMOS data in template files in RAM or CBFS. Change-Id: I323ed625e657cbdc1fae8c279a82ee578e83ad00 Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Thu Feb 2 15:48:27 2012, giving +2 See http://review.coreboot.org/583 for details. -gerrit From gerrit at coreboot.org Thu Feb 2 15:55:05 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Thu, 2 Feb 2012 15:55:05 +0100 Subject: [coreboot] Patch set updated for coreboot: 3ff1453 libpayload: Add access to CMOS images in memory space References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/584 -gerrit commit 3ff14530ac906ebc89f7300feb94694c49ccf34a Author: Patrick Georgi Date: Thu Feb 2 15:51:29 2012 +0100 libpayload: Add access to CMOS images in memory space Provide access to CMOS images in RAM or CBFS, such as cmos.defaults Change-Id: Ifa70dea6206d94c0c271caf9ae1152fc76b5d51a Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/options.c | 17 +++++++++++++++++ payloads/libpayload/include/libpayload.h | 3 ++- 2 files changed, 19 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 61e6cc5..36d8a9b 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -30,11 +30,28 @@ #include #include +u8 *mem_accessor_base; + +static u8 mem_read(u8 reg) +{ + return mem_accessor_base[reg]; +} + +static void mem_write(u8 val, u8 reg) +{ + mem_accessor_base[reg] = val; +} + struct nvram_accessor *use_nvram = &(struct nvram_accessor) { nvram_read, nvram_write }; +struct nvram_accessor *use_mem = &(struct nvram_accessor) { + mem_read, + mem_write +}; + struct cb_cmos_option_table *get_system_option_table(void) { return phys_to_virt(lib_sysinfo.option_table); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 91156e5..308d95c 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -199,7 +199,8 @@ struct nvram_accessor { void (*write)(u8 val, u8 reg); }; -extern struct nvram_accessor *use_nvram; +extern u8 *mem_accessor_base; +extern struct nvram_accessor *use_nvram, *use_mem; struct cb_cmos_option_table *get_system_option_table(void); void fix_options_checksum_with(const struct nvram_accessor *nvram); From gerrit at coreboot.org Thu Feb 2 16:01:49 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 16:01:49 +0100 Subject: [coreboot] Patch merged into coreboot/master: f81d7bd i3100: configure pci irqs References: Message-ID: the following patch was just integrated into master: commit f81d7bd250944c585a0cdcdf614f4ba4878b22db Author: Sven Schnelle Date: Wed Feb 1 11:47:29 2012 +0100 i3100: configure pci irqs without it, you can't boot from PCI devices like scsi controllers which require an interrupt set. So preconfigure all pci devices. Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194 Signed-off-by: Sven Schnelle Build-Tested: build bot (Jenkins) at Wed Feb 1 12:06:48 2012, giving +1 Reviewed-By: Sven Schnelle at Thu Feb 2 16:01:47 2012, giving +2 See http://review.coreboot.org/603 for details. -gerrit From paulepanter at users.sourceforge.net Thu Feb 2 16:06:14 2012 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Thu, 02 Feb 2012 16:06:14 +0100 Subject: [coreboot] Suggestion for (FOSDEM) talk to attract new contributors Message-ID: <1328195174.3941.29.camel@mattotaupa> Dear Carl-Daniel and coreboot folks, to attract new developers from my (inexperienced) point of view possible contributors hesitate because they think doing coreboot development will be searching for and reading a lot of data sheets, do reverse engineering, bricking boards, etc.. So to attract contributors one could point out that there are more or less hardware unrelated tasks to do and that interested people also can do (easy) hardware related stuff and learn things by looking at the infrastructure projects Patrick listed at [1]. Additionally more ?conventional? (software) programming is needed to get more payloads (configuration payload to for example set up RAM timing), create images that fit in a flash chip (for recovery maybe) and (graphical) configuration tools for example for `nvramtool`. But not knowing for sure the reasons people stay away from coreboot development this is of course just a suggestion and a guess. Thanks, Paul [1] http://www.coreboot.org/Infrastructure_Projects -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From peter at stuge.se Thu Feb 2 16:17:05 2012 From: peter at stuge.se (Peter Stuge) Date: Thu, 2 Feb 2012 16:17:05 +0100 Subject: [coreboot] Suggestion for (FOSDEM) talk to attract new contributors In-Reply-To: <1328195174.3941.29.camel@mattotaupa> References: <1328195174.3941.29.camel@mattotaupa> Message-ID: <20120202151705.30871.qmail@stuge.se> Paul Menzel wrote: > But not knowing for sure the reasons people stay away from coreboot > development this is of course just a suggestion and a guess. I for one think they are good ideas, and I hope that they will be mentioned during the talk! //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 190 bytes Desc: not available URL: From gerrit at coreboot.org Thu Feb 2 17:48:06 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 2 Feb 2012 17:48:06 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3ff1453 libpayload: Add access to CMOS images in memory space References: Message-ID: the following patch was just integrated into master: commit 3ff14530ac906ebc89f7300feb94694c49ccf34a Author: Patrick Georgi Date: Thu Feb 2 15:51:29 2012 +0100 libpayload: Add access to CMOS images in memory space Provide access to CMOS images in RAM or CBFS, such as cmos.defaults Change-Id: Ifa70dea6206d94c0c271caf9ae1152fc76b5d51a Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Thu Feb 2 17:48:05 2012, giving +2 See http://review.coreboot.org/584 for details. -gerrit From gerrit at coreboot.org Fri Feb 3 04:28:35 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 3 Feb 2012 04:28:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 44e8b03 SIO: Add smsc/sch4037 superio support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit 44e8b03e634c0b236dc7f252104c2399757c6145 Author: Kerry Sheh Date: Fri Feb 3 12:23:58 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 ++++ src/superio/smsc/sch4037/chip.h | 34 +++++++ src/superio/smsc/sch4037/sch4037.h | 34 +++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++++++++++++++ 7 files changed, 287 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..8dff3b8 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..392f229 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /*Auto power management*/ + pnp_write_config (dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config (dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config (dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV (port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..af4040f --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} From paulepanter at users.sourceforge.net Fri Feb 3 10:20:48 2012 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Fri, 03 Feb 2012 10:20:48 +0100 Subject: [coreboot] Patch set updated for coreboot: 44e8b03 SIO: Add smsc/sch4037 superio support In-Reply-To: References: Message-ID: <1328260848.3782.4.camel@mattotaupa> Dear Kerry, thank you for updating the patch. Am Freitag, den 03.02.2012, 04:28 +0100 schrieb Kerry Sheh: > Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 > > -gerrit > > commit 44e8b03e634c0b236dc7f252104c2399757c6145 > Author: Kerry Sheh > Date: Fri Feb 3 12:23:58 2012 +0800 > > SIO: Add smsc/sch4037 superio support > > Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 > Signed-off-by: Kerry Sheh > Signed-off-by: Kerry Sheh > --- > src/superio/smsc/Kconfig | 3 + > src/superio/smsc/Makefile.inc | 2 + > src/superio/smsc/sch4037/Makefile.inc | 20 ++++ > src/superio/smsc/sch4037/chip.h | 34 +++++++ > src/superio/smsc/sch4037/sch4037.h | 34 +++++++ > src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++++++++ > src/superio/smsc/sch4037/superio.c | 123 +++++++++++++++++++++++++ > 7 files changed, 287 insertions(+), 0 deletions(-) [?] > diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c > new file mode 100644 > index 0000000..392f229 > --- /dev/null > +++ b/src/superio/smsc/sch4037/sch4037_early_init.c > @@ -0,0 +1,71 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2012 Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ Is that comment still valid? I think the model number needs to be updated. > + > +#include > +#include "sch4037.h" > + > +static inline void pnp_enter_conf_state(device_t dev) > +{ > + unsigned port = dev>>8; > + outb(0x55, port); > +} > + > +static void pnp_exit_conf_state(device_t dev) > +{ > + unsigned port = dev>>8; > + outb(0xaa, port); > +} > + > +static inline void sch4037_early_init(unsigned port) > +{ > + device_t dev; > + > + dev = PNP_DEV (port, SMSCSUPERIO_SP1); > + pnp_enter_conf_state(dev); > + > + /*Auto power management*/ For consistency spaces are missing at the borders. > + pnp_write_config (dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ > + pnp_write_config (dev, 0x23, 0 ); > + > + /* Enable SMSC UART 0 */ > + dev = PNP_DEV (port, SMSCSUPERIO_SP1); > + pnp_set_logical_device(dev); > + pnp_set_enable(dev, 0); > + > + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); > + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); > + > + /* Enabled High speed, disabled MIDI support. */ > + pnp_write_config (dev, 0xF0, 0x02); > + pnp_set_enable(dev, 1); > + > + /* Enable keyboard */ > + dev = PNP_DEV (port, SCH4037_KBC); > + pnp_set_logical_device(dev); > + pnp_set_enable(dev, 0); > + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ > + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ > + pnp_set_enable(dev, 1); > + > + pnp_exit_conf_state(dev); > + > +} > + > diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c > new file mode 100644 > index 0000000..af4040f > --- /dev/null > +++ b/src/superio/smsc/sch4037/superio.c > @@ -0,0 +1,123 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2012 Advanced Micro Devices, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +/* RAM driver for the SMSC KBC1100 Super I/O chip */ Dito. [?] Thanks, Paul -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From prakash at punnoor.de Fri Feb 3 10:17:34 2012 From: prakash at punnoor.de (Prakash Punnoor) Date: Fri, 03 Feb 2012 10:17:34 +0100 Subject: [coreboot] Trying to port abit A-S78H In-Reply-To: <20120129183847.19436.qmail@stuge.se> References: <1977757.UymRIiIbzV@graviton> <4F258930.90905@punnoor.de> <20120129183847.19436.qmail@stuge.se> Message-ID: <3290074.2kehqaUnQA@graviton> On Sunday 29 January 2012 19:38:47 Peter Stuge wrote: > Prakash Punnoor wrote: > > >> - seabios payload: no gfx output, but postcode is F8 > > > > > > Focus on this. What is the serial output from coreboot and SeaBIOS? > > > > That's the thing: I don't have a serial port on this mainboard, that's > > why I had to do painful post code debugging... > > Maybe you can use some of the other methods for debug output. USB > Debug device or RTL8029? Thx for the hints. I knew about the USB debug device, but it seems too costly and also there is no guarantee it will work. But I have an ancient RTL8029AS which I tried. I didn't get any output, though. I configured it properly in menuconfig. (I didn't change the default ioport. Linux chooses 0xbf00, but 0xe00 seems to be free, as well...) Do I have to call some function in the code to enable console output via ethernet? I checked the connection in Linux and it worked. (I use a cross-over cable, btw.) > For serial output from SeaBIOS or later coreboot stages a PCI based > serial port would also work. Ok, this would be my second option if above doesn't work. Thanks, Prakash From gerrit at coreboot.org Fri Feb 3 11:18:17 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 3 Feb 2012 11:18:17 +0100 Subject: [coreboot] Patch set updated for coreboot: bdc19e0 SIO: Add smsc/sch4037 superio support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit bdc19e069ea81915c87a8b584f70fcfb409c076b Author: Kerry Sheh Date: Fri Feb 3 19:12:43 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 ++++ src/superio/smsc/sch4037/chip.h | 34 +++++++ src/superio/smsc/sch4037/sch4037.h | 34 +++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 69 ++++++++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++++++++++++++ 7 files changed, 285 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..8dff3b8 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..9c74062 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config(dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..af4040f --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} From gerrit at coreboot.org Fri Feb 3 11:18:17 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 3 Feb 2012 11:18:17 +0100 Subject: [coreboot] Patch set updated for coreboot: 29dad49 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/561 -gerrit commit 29dad490271f35bd0125159c4d5d1786022ae2d4 Author: Kerry Sheh Date: Fri Feb 3 12:35:23 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/southbridge/amd/Makefile.inc | 1 + src/southbridge/amd/cimx/Kconfig | 3 +- src/southbridge/amd/cimx/Makefile.inc | 3 +- src/southbridge/amd/cimx/sb700/Amd.h | 363 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/AmdSbLib.h | 181 +++++++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 63 +++++ src/southbridge/amd/cimx/sb700/Makefile.inc | 31 +++ src/southbridge/amd/cimx/sb700/Platform.h | 87 +++++++ src/southbridge/amd/cimx/sb700/bootblock.c | 97 +++++++ src/southbridge/amd/cimx/sb700/cbtypes.h | 53 ++++ src/southbridge/amd/cimx/sb700/chip.h | 42 +++ src/southbridge/amd/cimx/sb700/chip_name.c | 25 ++ src/southbridge/amd/cimx/sb700/early.c | 75 ++++++ src/southbridge/amd/cimx/sb700/late.c | 329 ++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.c | 195 ++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.h | 30 +++ src/southbridge/amd/cimx/sb700/sb_cimx.h | 49 ++++ src/southbridge/amd/cimx/sb700/smbus.c | 270 ++++++++++++++++++++ src/southbridge/amd/cimx/sb700/smbus.h | 82 ++++++ 19 files changed, 1977 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 406a0b3..54245f2 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -12,6 +12,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 8f12b90..f61b75a 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -21,5 +21,6 @@ config AMD_SB_CIMX bool default n +source src/southbridge/amd/cimx/sb700/Kconfig source src/southbridge/amd/cimx/sb800/Kconfig source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 421a11c..80c6378 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h new file mode 100644 index 0000000..fbd5531 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Amd.h @@ -0,0 +1,363 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +// AGESA Types and Definitions +#ifndef NULL +#define NULL 0 +#endif + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT + +#ifndef Int16FromChar +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#endif +#ifndef Int32FromChar +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +#endif + +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') + +typedef unsigned int AGESA_STATUS; + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h new file mode 100644 index 0000000..2812605 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef signed char *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + unsigned int AMDLogo; + unsigned long long CreatorID; + unsigned int Version1; + unsigned int Version2; + unsigned int Version3; + unsigned int ModuleInfoOffset; + unsigned int EntryPoint; + unsigned int ImageBase; + unsigned int RelocTableOffset; + unsigned int ImageSize; + unsigned short CheckSum; + unsigned char ImageType; + unsigned char Reserved2; +} CIMFILEHEADER; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS AmdSbDispatcher (IN void *pConfig); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig new file mode 100644 index 0000000..27338fc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_CIMX_SB700 + bool + select IOAPIC + select AMD_SB_CIMX + +if SOUTHBRIDGE_AMD_CIMX_SB700 +config SATA_CONTROLLER_MODE + hex + default 0x0 + help + 0x0 = Native IDE mode. + 0x1 = RAID mode. + 0x2 = AHCI mode. + 0x3 = Legacy IDE mode. + 0x4 = IDE->AHCI mode. + 0x5 = AHCI mode as 7804 ID (AMD driver). + 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). + +config PCIB_ENABLE + bool + default n + help + n = Disable PCI Bridge Device 14 Function 4. + y = Enable PCI Bridge Device 14 Function 4. + +config ACPI_SCI_IRQ + hex + default 0x9 + help + Set SCI IRQ to 9. +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/cimx/sb700/bootblock.c" + +config REDIRECT_SBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Southbridge CIMX Trace to serial console" + default n + help + This Option allows you to redirect the AMD Southbridge CIMX Trace + debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. +endif #SOUTHBRIDGE_AMD_CIMX_SB700 + diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..7929cf7 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# SB700 Platform Files + +romstage-y += early.c +romstage-y += smbus.c + +ramstage-y += late.c + +driver-y += smbus.c +driver-y += lpc.c + + diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h new file mode 100644 index 0000000..15e5b07 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_PLATFORM_H_ +#define _AMD_SB_CIMx_PLATFORM_H_ + +#pragma pack(push,1) + +#include "cbtypes.h" +#include +#include +#ifdef NULL +#undef NULL +#endif +#define NULL 0 + +typedef struct _EXT_PCI_ADDR{ + UINT32 Reg :16; + UINT32 Func:3; + UINT32 Dev :5; + UINT32 Bus :8; +}EXT_PCI_ADDR; + + +typedef union _PCI_ADDR{ + UINT32 ADDR; + EXT_PCI_ADDR Addr; +}PCI_ADDR; + + +#ifdef CIM_DEBUG + +#if CIM_DEBUG & 2 +void TraceDebug( UINT32 Level, CHAR8 *Format, ...); +#define TRACE(Arguments) TraceDebug Arguments +#else +#define TRACE(Arguments) +#endif + +#if CIM_DEBUG & 1 +void TraceCode ( UINT32 Level, UINT32 Code); +#define TRACECODE(Arguments) TraceCode Arguments +#else +#define TRACECODE(Arguments) +#endif +#else + #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL + #define TRACE(Arguments) printk Arguments + #else + #define TRACE(Arguments) do {} while(0) + #endif + #define TRACECODE(Arguments) +#endif + +#define FIXUP_PTR(ptr) ptr + +#pragma pack(pop) + +#include "OEM.h" +#include "Amd.h" +#include "ACPILIB.h" +#include "SBTYPE.h" +#include "sbAMDLIB.h" +#include "SBCMNLIB.h" +#include "SB700.h" +#include "SBDEF.h" + +#define DMSG_SB_TRACE 0x02 + +#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_ + diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c new file mode 100644 index 0000000..401c039 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include + + +#if CONFIG_CONSOLE_POST == 1 + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif // CONFIG_TTYS0_DIV + +#define UART_LCS CONFIG_TTYS0_LCS + +#endif // CONFIG_CONSOLE_POST == 1 + + +static void sb700_enable_rom(void) +{ + u32 word; + u32 dword; + device_t dev; + + dev = PCI_DEV(0, 0x14, 0x03); + /* SB700 LPC Bridge 0:20:3:44h. + * BIT6: Port Enable for serial port 0x3f8-0x3ff + * BIT29: Port Enable for KBC port 0x60 and 0x64 + * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 + */ + dword = pci_io_read_config32(dev, 0x44); + //dword |= (1<<6) | (1<<29) | (1<<30) ; + /*Turn on all of LPC IO Port decode enable */ + dword = 0xffffffff; + pci_io_write_config32(dev, 0x44, dword); + + /* SB700 LPC Bridge 0:20:3:48h. + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) + * BIT6: Port Enable for RTC IO 0x70-0x73 + * BIT21: Port Enable for Port 0x80 + */ + dword = pci_io_read_config32(dev, 0x48); + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + pci_io_write_config32(dev, 0x48, dword); + + /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Set the 4MB enable bits */ + word = pci_io_read_config16(dev, 0x6c); + word = 0xFFC0; + pci_io_write_config16(dev, 0x6c, word); +} + +static void bootblock_southbridge_init(void) +{ + /* Setup the rom access for 2M */ + sb700_enable_rom(); +} diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h new file mode 100644 index 0000000..d37e1e3 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/cbtypes.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include + +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN; +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +#endif diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h new file mode 100644 index 0000000..ef294f4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CIMX_SB700_CHIP_H_ +#define _CIMX_SB700_CHIP_H_ + +extern struct chip_operations southbridge_amd_cimx_sb700_ops; + +/* + * configuration set in mainboard/devicetree.cb + * boot_switch_sata_ide: + * 0 -set SATA as primary, PATA(IDE) as secondary. + * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, + * gpp_configuration - The configuration of General Purpose Port A/B/C/D + * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] + * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] + * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ +struct southbridge_amd_cimx_sb700_config +{ + u32 boot_switch_sata_ide : 1; + u8 gpp_configuration; +}; + +#endif /* _CIMX_SB700_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c new file mode 100644 index 0000000..13d2276 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("AMD South Bridge SB700") +}; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c new file mode 100644 index 0000000..bc3d944 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +//#include +#include +#include +#include /* inl, outl */ +#include /* device_t */ +#include "Platform.h" +#include "sb_cimx.h" +#include "sb700_cfg.h" /*sb700_cimx_config*/ +#include +#include +#include "smbus.h" + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus) +{ + device_t dev; + + printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - Start.\n"); + //dev = PCI_DEV(bus, 0x14, 0); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), + bus); + + printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - End.\n"); + return (dev >> 15) & 0x1f; +} +#endif + +/** + * @brief Enable A-Link Express Configuration DMA Access. + */ + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of sbPowerOnInit entry point. + */ +void sb_Poweron_Init(void) +{ + AMDSBCFG sb_early_cfg; + + printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() Start:\n", __func__); + /* Enable A-Link Base Address */ + //sb_enable_alink (); + + sb700_cimx_config(&sb_early_cfg); + sbPowerOnInit(&sb_early_cfg); + printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() End\n", __func__); +} + diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c new file mode 100644 index 0000000..8d13cd8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include /* device_t */ +#include /* device_operations */ +#include +#include +#include /* smbus_bus_operations */ +#include /* printk */ +#include "lpc.h" /* lpc_read_resources */ +#include "Platform.h" /* Platfrom Specific Definitions */ +#include "sb_cimx.h" +#include "sb700_cfg.h" /* sb700 Cimx configuration */ +#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ + + +/*implement in mainboard.c*/ +void set_pcie_reset(void); +void set_pcie_dereset(void); + +static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config +static AMDSBCFG *sb_config = &sb_late_cfg; + + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_config Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* config) +{ + u32 ret = 0; + + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n"); + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n"); + return ret; +} + + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static void lpc_enable_resources(device_t dev) +{ + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - Start.\n"); + pci_dev_enable_resources(dev); + lpc_enable_childrens_resources(dev); + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - End.\n"); +} + +static struct device_operations lpc_ops = { + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_LPC, +}; + + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390 +}; + +#if CONFIG_USBDEBUG +static void usb_set_resources(struct device *dev) +{ + struct resource *res; + u32 base; + u32 old_debug; + + printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - Start.\n"); + old_debug = get_ehci_debug(); + set_ehci_debug(0); + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x10); + set_ehci_debug(old_debug); + if (!res) + return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); + printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - End.\n"); +} +#endif + + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, +#if CONFIG_USBDEBUG + .set_resources = usb_set_resources, +#else + .set_resources = pci_dev_set_resources, +#endif + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +/* + * The pci id of usb ctrl 0 and 1 are the same. + */ +static const struct pci_driver usb_ohci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci3_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1, +}; + +static const struct pci_driver usb_ehci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci4_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */ +}; + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver azalia_driver __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_HDA, +}; + +#ifdef UNUSED_CODE +static struct device_operations gec_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; +#endif + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_PCI, +}; + + +static void sb700_enable(device_t dev) +{ + struct southbridge_amd_cimx_sb700_config *sb_chip = + (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info); + + printk(BIOS_DEBUG, "sb700_enable() "); + switch (dev->path.pci.devfn) { + case (0x11 << 3) | 0: /* 0:11.0 SATA */ + sb700_cimx_config(sb_config); + if (dev->enabled) { + sb_config->SataController = CIMX_OPTION_ENABLED; + if (1 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. + else if (0 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. + } else { + sb_config->SataController = CIMX_OPTION_DISABLED; + } + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + break; + + case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { +#if 1 + u32 ioapic_base; + printk(BIOS_DEBUG, "sm_init().\n"); + ioapic_base = IO_APIC_ADDR; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ +#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); +#elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); +#else +#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" +#endif +#endif + } + break; + + case (0x14 << 3) | 1: /* 0:14:1 IDE */ + break; + + case (0x14 << 3) | 2: /* 0:14:2 HDA */ + if (dev->enabled) { + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; + } + printk(BIOS_DEBUG, "hda enabled\n"); + } else { + sb_config->AzaliaController = AZALIA_DISABLE; + printk(BIOS_DEBUG, "hda disabled\n"); + } + break; + + + case (0x14 << 3) | 3: /* 0:14:3 LPC */ + break; + + case (0x14 << 3) | 4: /* 0:14:4 PCI */ + break; + + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + /* call CIMX entry after last device enable */ + sb_Before_Pci_Init(); + break; + + default: + break; + } +} + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("ATI SB700") + .enable_dev = sb700_enable, +}; + +/** + * @brief SB Cimx entry point sbBeforePciInit wrapper + */ +void sb_Before_Pci_Init(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbBeforePciInit(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} + +void sb_After_Pci_Init(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbAfterPciInit(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} + +void sb_Late_Post(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_LATE_POST_INIT; + //AmdSbDispatcher(sb_config); + sbLatePost(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c new file mode 100644 index 0000000..5d551cc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc.h" +#include +#include +#include /* printk */ +#include + +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xfc, i; + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} + +void lpc_read_resources(device_t dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - Start.\n"); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + + pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + compact_resources(dev); + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - End.\n"); +} + +void lpc_set_resources(struct device *dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - Start.\n"); + pci_dev_set_resources(dev); + + /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS); + pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - End.\n"); +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whos children's resources are to be enabled + * + */ +void lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); +/* + printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); +*/ + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + reg |= (1 << 29); + break; + case 0x3f8: /* COM1 */ + reg |= (1 << 6); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 7); + break; + case 0x378: /* Parallal 1 */ + reg |= (1 << 0); + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 26); + break; + case 0x220: /* Aduio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 18); + break; + case 0x400: + reg_x |= (1 << 16); + break; + case 0x480: + reg_x |= (1 << 17); + break; + case 0x500: + reg_x |= (1 << 18); + break; + case 0x580: + reg_x |= (1 << 19); + break; + case 0x4700: + reg_x |= (1 << 22); + break; + case 0xfd60: + reg_x |= (1 << 23); + break; + default: + if (var_num >= 3) + continue; /* only 3 var ; compact them ? */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + break; + case 1: + reg_x |= (1 << 24); + break; + case 2: + reg_x |= (1 << 25); + break; + } + reg_var[var_num++] = + base & 0xffff; + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 2: + pci_write_config16(dev, 0x90, reg_var[2]); + case 1: + pci_write_config16(dev, 0x66, reg_var[1]); + case 0: + //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata + break; + } + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - End.\n"); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h new file mode 100644 index 0000000..edb13f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_LPC_H_ +#define _SB700_LPC_H_ + + +#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ + +void lpc_read_resources(device_t dev); +void lpc_set_resources(device_t dev); +void lpc_enable_childrens_resources(device_t dev); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h new file mode 100644 index 0000000..84fe4d0 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_H_ +#define _CIMX_H_ + +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +#define REV_SB700_A11 0x11 +#define REV_SB700_A12 0x12 + + +/** + * AMD South Bridge CIMx entry point wrapper + */ +void sb_Poweron_Init(void); +void sb_Before_Pci_Init(void); +void sb_After_Pci_Init(void); +void sb_Mid_Post_Init(void); +void sb_Late_Post(void); + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c new file mode 100644 index 0000000..58dd012 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.c @@ -0,0 +1,270 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "smbus.h" +#include /* printk */ + +static inline void smbus_delay(void) +{ + outb(inb(0x80), 0x80); +} + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { /* ready now */ + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; /* mask off reserved bits */ + if (val & 0x1c) { + return -5; /* error */ + } + if (val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + return 0; + } + } while (--loops); + + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n"); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n"); + return byte; +} + +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n"); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n"); + return 0; +} + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n"); + return byte; +} + +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n"); + return 0; +} + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); +} + +/* space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n"); + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n"); +} + diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h new file mode 100644 index 0000000..10e0874 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_SMBUS_H_ +#define _SB700_SMBUS_H_ + +//#include +#include /* SMBUS0_BASE_ADDRESS */ +#ifndef SMBUS0_BASE_ADDRESS +#error SMBUS0_BASE_ADDRESS not define +#endif +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif //_SB700_SMBUS_H_ From gerrit at coreboot.org Fri Feb 3 11:18:18 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 3 Feb 2012 11:18:18 +0100 Subject: [coreboot] Patch set updated for coreboot: 5d7ce65 RD890: AMD RD890/SR56X0 CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit 5d7ce65c8410c67dcbb5496714cdb36378e203b9 Author: Kerry Sheh Date: Fri Feb 3 12:35:23 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 269 +++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1171 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..5eaefd1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include + +#include "amd.h" //cimx typedef +#include +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; /// + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..62a842a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rx780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RX780_HT, +}; + +static const struct pci_driver ht_driver_rd780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD780_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ + From gerrit at coreboot.org Fri Feb 3 11:18:19 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 3 Feb 2012 11:18:19 +0100 Subject: [coreboot] Patch set updated for coreboot: 222876b AGESA F15: AGESA family15 model 00-0fh northbridge wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/556 -gerrit commit 222876b2886e5a897320837aebb68ec81ba57006 Author: Kerry Sheh Date: Fri Feb 3 12:35:23 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/agesa/Kconfig | 3 +- src/northbridge/amd/agesa/Makefile.inc | 3 +- src/northbridge/amd/agesa/family15/Kconfig | 49 + src/northbridge/amd/agesa/family15/Makefile.inc | 20 + src/northbridge/amd/agesa/family15/bootblock.c | 25 + src/northbridge/amd/agesa/family15/chip.h | 24 + src/northbridge/amd/agesa/family15/northbridge.c | 1174 ++++++++++++++++++++ src/northbridge/amd/agesa/family15/northbridge.h | 26 + .../amd/agesa/family15/root_complex/Kconfig | 2 + .../amd/agesa/family15/root_complex/chip.h | 24 + 10 files changed, 1348 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 3bcb0bb..2ed9fd5 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,4 +24,5 @@ config CONSOLE_VGA_MULTI source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig +source src/northbridge/amd/agesa/family15/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1da8f60..eef1cd3 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,3 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..52f7a1e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY15 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY15 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 +config MMCONF_BUS_NUMBER + int + default 64 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family15/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 + +source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..255fe10 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c new file mode 100644 index 0000000..fc62c3e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..cec1fc4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_ops; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c new file mode 100644 index 0000000..c16c8d3 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -0,0 +1,1174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "root_complex/chip.h" +#include "northbridge.h" +#include "chip.h" +#if CONFIG_AMD_SB_CIMX +#include "sb_cimx.h" +#endif + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; ilink[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; ienabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure not exist, usable + * @retval 0 resource exist, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + +#if CONFIG_AMD_SB_CIMX + //sb_Before_Pci_Init(); +#endif + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } +} + + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " ", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + device_t io_hub = NULL; + u32 next_unitid = 0x18; + nodeid = amdfam15_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ + if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1600, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1200, +}; + +struct chip_operations northbridge_amd_agesa_family15_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); + + +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} +#endif + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_TABLES_SIZE, high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 6) {//f15 + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ +#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ +#define CFG_PLAT_NUM_IO_APICS 3 +#endif + if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { + lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, cpu_path.apic.apic_id); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " "); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + + +struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") + .enable_dev = root_complex_enable_dev, +}; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h new file mode 100644 index 0000000..7606b32 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15_H +#define NORTHBRIDGE_AMD_AGESA_FAM15_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig new file mode 100644 index 0000000..032b836 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h new file mode 100644 index 0000000..06b3510 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops; From gerrit at coreboot.org Fri Feb 3 11:18:20 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 3 Feb 2012 11:18:20 +0100 Subject: [coreboot] Patch set updated for coreboot: fc27601 AGESA F15: AGESA family15 model 00-0fh cpu wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/555 -gerrit commit fc27601469f29e7dfc7d40ad5345ba6f3f8a9f9f Author: Kerry Sheh Date: Fri Feb 3 12:35:22 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/cpu/amd/agesa/Kconfig | 7 +- src/cpu/amd/agesa/Makefile.inc | 3 +- src/cpu/amd/agesa/family15/Kconfig | 82 +++++++++++++++ src/cpu/amd/agesa/family15/Makefile.inc | 30 ++++++ src/cpu/amd/agesa/family15/chip.h | 23 +++++ src/cpu/amd/agesa/family15/chip_name.c | 25 +++++ src/cpu/amd/agesa/family15/model_15_init.c | 147 ++++++++++++++++++++++++++++ src/include/cpu/amd/amdfam15.h | 41 ++++++++ 8 files changed, 356 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 60bb74b..8eaa11d 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,11 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_AGESA + bool + default n + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig +source src/cpu/amd/agesa/family15/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..fb536dd 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..0f2f920 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -0,0 +1,82 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15 + bool + select PCI_IO_CFG_EXT + select AMD_AGESA + +if CPU_AMD_AGESA_FAMILY15 + +config CPU_AMD_SOCKET_G34 + bool + default n + help + AMD G34 Socket + +config CPU_AMD_SOCKET_C32 + bool + default n + help + AMD C32 Socket + +config CPU_AMD_SOCKET_AM3R2 + bool + default n + help + AMD AM3r2 Socket + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY15 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..936d3c8 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -0,0 +1,30 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + +ramstage-y += chip_name.c +driver-y += model_15_init.c + diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h new file mode 100644 index 0000000..0171e7f --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family15_ops; + +struct cpu_amd_agesa_family15_config { +}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c new file mode 100644 index 0000000..963a423 --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family15_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c new file mode 100644 index 0000000..d100338 --- /dev/null +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr.lo = 0x04040404; msr.hi = 0x04040404; + wrmsr(0x259, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache (); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h new file mode 100644 index 0000000..3d300de --- /dev/null +++ b/src/include/cpu/amd/amdfam15.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM15_H +#define CPU_AMD_FAM15_H + +#include + +#define MCI_STATUS 0x00000401 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f + +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define CU_CFG_MSR 0xC0011023 +#define CU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +static msr_t rdmsr_amd(u32 index); +static void wrmsr_amd(u32 index, msr_t msr); + +#endif /* CPU_AMD_FAM15_H */ From gerrit at coreboot.org Fri Feb 3 11:57:36 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 3 Feb 2012 11:57:36 +0100 Subject: [coreboot] Patch set updated for coreboot: 69470aa libpayload: Add iterators for CMOS variables References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/587 -gerrit commit 69470aacda54a628fb7d6437198fc2eddb314009 Author: Patrick Georgi Date: Mon Jan 16 15:39:57 2012 +0100 libpayload: Add iterators for CMOS variables Provide functions that pick the first CMOS variable defined in the cmos layout, and from there, the next one. Change-Id: Ie98146de7f6273089fc6fc0b232a4b94337cf8a3 Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/options.c | 14 ++++++++++++++ payloads/libpayload/include/libpayload.h | 2 ++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 1b98cda..10d165e 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -171,6 +171,20 @@ static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *op return NULL; } +struct cb_cmos_entries *first_cmos_entry(struct cb_cmos_option_table *option_table) +{ + return lookup_cmos_entry(option_table, ""); +} + +struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cmos_entry) +{ + struct cb_cmos_entries *next = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); + if (next->tag == CB_TAG_OPTION) + return next; + else + return NULL; +} + /* Either value or text must be NULL. Returns the field that matches "the other" for a given config_id */ static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *option_table, int config_id, u8 *value, char *text) { diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 488ad48..53d6672 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -206,6 +206,8 @@ struct cb_cmos_option_table *get_system_option_table(void); int options_checksum_valid(const struct nvram_accessor *nvram); void fix_options_checksum_with(const struct nvram_accessor *nvram); void fix_options_checksum(void); +struct cb_cmos_entries *first_cmos_entry(struct cb_cmos_option_table *option_table); +struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cur); int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option(void *dest, char *name); From gerrit at coreboot.org Fri Feb 3 11:57:00 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 3 Feb 2012 11:57:00 +0100 Subject: [coreboot] Patch set updated for coreboot: 788f600 libpayload: Expose options_checksum_valid References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/586 -gerrit commit 788f60034be9fa535f5c384d5513d2817c3920ad Author: Patrick Georgi Date: Mon Jan 16 15:03:11 2012 +0100 libpayload: Expose options_checksum_valid options_checksum_valid can be used as a fast test to identify invalid CMOS data by checking the checksum. Change-Id: I44635d4c5d389579ad82435907ba8658e1bd44bb Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/options.c | 2 +- payloads/libpayload/include/libpayload.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 33c0659..1b98cda 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -57,7 +57,7 @@ struct cb_cmos_option_table *get_system_option_table(void) return phys_to_virt(lib_sysinfo.option_table); } -static int options_checksum_valid(const struct nvram_accessor *nvram) +int options_checksum_valid(const struct nvram_accessor *nvram) { int i; int range_start = lib_sysinfo.cmos_range_start / 8; diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index dd98404..488ad48 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -203,6 +203,7 @@ extern u8 *mem_accessor_base; extern struct nvram_accessor *use_nvram, *use_mem; struct cb_cmos_option_table *get_system_option_table(void); +int options_checksum_valid(const struct nvram_accessor *nvram); void fix_options_checksum_with(const struct nvram_accessor *nvram); void fix_options_checksum(void); int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name); From gerrit at coreboot.org Fri Feb 3 11:54:55 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 3 Feb 2012 11:54:55 +0100 Subject: [coreboot] Patch set updated for coreboot: 75ff6ad libpayload: Provide interpretation of CMOS data structures References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/585 -gerrit commit 75ff6addfcd674cc2b3803f9b4216e1b9e338af7 Author: Patrick Georgi Date: Mon Jan 16 13:47:33 2012 +0100 libpayload: Provide interpretation of CMOS data structures Add new functions that allow using string based key/value access to CMOS, including support for enums. Change-Id: Ibe238eff4c5230e5f61004c88221cd34393873aa Signed-off-by: Patrick Georgi --- payloads/libpayload/drivers/options.c | 103 ++++++++++++++++++++++++++++++ payloads/libpayload/include/libpayload.h | 2 + 2 files changed, 105 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 36d8a9b..33c0659 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -171,6 +171,42 @@ static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *op return NULL; } +/* Either value or text must be NULL. Returns the field that matches "the other" for a given config_id */ +static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *option_table, int config_id, u8 *value, char *text) +{ + struct cb_cmos_entries *cmos_entry; + int len = strnlen(text, CMOS_MAX_TEXT_LENGTH); + + /* cmos entries are located right after the option table. Skip them */ + cmos_entry = (struct cb_cmos_entries*)((unsigned char *)option_table + option_table->header_length); + while (cmos_entry->tag == CB_TAG_OPTION) + cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size); + + /* cmos enums are located after cmos entries. */ + struct cb_cmos_enums *cmos_enum; + for ( cmos_enum = (struct cb_cmos_enums*)cmos_entry; + cmos_enum->tag == CB_TAG_OPTION_ENUM; + cmos_enum = (struct cb_cmos_enums*)((unsigned char *)cmos_enum + cmos_enum->size)) { + if ((cmos_enum->config_id == config_id) + && ((value == NULL) || (cmos_enum->value == *value)) + && ((text == NULL) || (memcmp((const char*)cmos_enum->text, text, len)))) { + return cmos_enum; + } + } + + return NULL; +} + +static struct cb_cmos_enums *lookup_cmos_enum_by_value(struct cb_cmos_option_table *option_table, int config_id, u8 *value) +{ + return lookup_cmos_enum_core(option_table, config_id, value, NULL); +} + +static struct cb_cmos_enums *lookup_cmos_enum_by_label(struct cb_cmos_option_table *option_table, int config_id, char *label) +{ + return lookup_cmos_enum_core(option_table, config_id, NULL, label); +} + int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name) { struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); @@ -211,3 +247,70 @@ int set_option(void *value, char *name) { return set_option_with(use_nvram, get_system_option_table(), value, name); } + +int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, char *name) +{ + void *raw; + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + if (!cmos_entry) + return 1; + int cmos_length = (cmos_entry->length+7)/8; + + /* extra byte to ensure 0-terminated strings */ + raw = malloc(cmos_length+1); + memset(raw, 0, cmos_length+1); + + int ret = get_option_with(nvram, option_table, raw, name); + + struct cb_cmos_enums *cmos_enum; + switch (cmos_entry->config) { + case 'h': + /* only works on little endian. + 26 bytes is enough for a 64bit value in decimal */ + *dest = malloc(26); + sprintf(*dest, "%ull", *(u64*)raw); + break; + case 's': + *dest = strdup(raw); + break; + case 'e': + cmos_enum = lookup_cmos_enum_by_value(option_table, cmos_entry->config_id, (u8*)raw); + *dest = strdup((const char*)cmos_enum->text); + break; + default: /* fail */ + return 1; + } + free(raw); + return ret; +} + +int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char *value, char *name) +{ + void *raw; + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + if (!cmos_entry) + return 1; + + struct cb_cmos_enums *cmos_enum; + switch (cmos_entry->config) { + case 'h': + /* only works on little endian */ + raw = malloc(8); + *(u64*)raw = strtoull(value, NULL, 0); + break; + case 's': + raw = strdup(value); + break; + case 'e': + cmos_enum = lookup_cmos_enum_by_label(option_table, cmos_entry->config_id, value); + raw = malloc(sizeof(u32)); + *(u32*)raw = cmos_enum->value; + break; + default: /* fail */ + return 1; + } + + int ret = set_option_with(nvram, option_table, raw, name); + free(raw); + return ret; +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 308d95c..dd98404 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -210,6 +210,8 @@ int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char int get_option(void *dest, char *name); int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name); int set_option(void *value, char *name); +int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, char *name); +int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char *value, char *name); /** * @defgroup console Console functions From Kerry.She at amd.com Fri Feb 3 11:17:53 2012 From: Kerry.She at amd.com (She, Kerry) Date: Fri, 3 Feb 2012 18:17:53 +0800 Subject: [coreboot] Patch set updated for coreboot: 44e8b03 SIO: Add smsc/sch4037 superio support In-Reply-To: <1328260848.3782.4.camel@mattotaupa> References: <1328260848.3782.4.camel@mattotaupa> Message-ID: Dear Paul, Thanks for your careful review, I have fix these problem, and upload a new patch set. Thanks --Kerry > -----Original Message----- > From: Paul Menzel [mailto:paulepanter at users.sourceforge.net] > Sent: Friday, February 03, 2012 5:21 PM > To: coreboot at coreboot.org > Cc: She, Kerry; Kerry Sheh > Subject: Re: [coreboot] Patch set updated for coreboot: 44e8b03 SIO: Add > smsc/sch4037 superio support > > Dear Kerry, > > > thank you for updating the patch. > > > Am Freitag, den 03.02.2012, 04:28 +0100 schrieb Kerry Sheh: > > Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to > > gerrit, which you can find at http://review.coreboot.org/562 > > > > -gerrit > > > > commit 44e8b03e634c0b236dc7f252104c2399757c6145 > > Author: Kerry Sheh > > Date: Fri Feb 3 12:23:58 2012 +0800 > > > > SIO: Add smsc/sch4037 superio support > > > > Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 > > Signed-off-by: Kerry Sheh > > Signed-off-by: Kerry Sheh > > --- > > src/superio/smsc/Kconfig | 3 + > > src/superio/smsc/Makefile.inc | 2 + > > src/superio/smsc/sch4037/Makefile.inc | 20 ++++ > > src/superio/smsc/sch4037/chip.h | 34 +++++++ > > src/superio/smsc/sch4037/sch4037.h | 34 +++++++ > > src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++++++++ > > src/superio/smsc/sch4037/superio.c | 123 > +++++++++++++++++++++++++ > > 7 files changed, 287 insertions(+), 0 deletions(-) > > [?] > > > diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c > > b/src/superio/smsc/sch4037/sch4037_early_init.c > > new file mode 100644 > > index 0000000..392f229 > > --- /dev/null > > +++ b/src/superio/smsc/sch4037/sch4037_early_init.c > > @@ -0,0 +1,71 @@ > > +/* > > + * This file is part of the coreboot project. > > + * > > + * Copyright (C) 2012 Advanced Micro Devices, Inc. > > + * > > + * This program is free software; you can redistribute it and/or > > +modify > > + * it under the terms of the GNU General Public License as published > > +by > > + * the Free Software Foundation; version 2 of the License. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA > > +02110-1301 USA */ > > + > > +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ > > Is that comment still valid? I think the model number needs to be updated. > > > + > > +#include > > +#include "sch4037.h" > > + > > +static inline void pnp_enter_conf_state(device_t dev) { > > + unsigned port = dev>>8; > > + outb(0x55, port); > > +} > > + > > +static void pnp_exit_conf_state(device_t dev) { > > + unsigned port = dev>>8; > > + outb(0xaa, port); > > +} > > + > > +static inline void sch4037_early_init(unsigned port) { > > + device_t dev; > > + > > + dev = PNP_DEV (port, SMSCSUPERIO_SP1); > > + pnp_enter_conf_state(dev); > > + > > + /*Auto power management*/ > > For consistency spaces are missing at the borders. > > > + pnp_write_config (dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ > > + pnp_write_config (dev, 0x23, 0 ); > > + > > + /* Enable SMSC UART 0 */ > > + dev = PNP_DEV (port, SMSCSUPERIO_SP1); > > + pnp_set_logical_device(dev); > > + pnp_set_enable(dev, 0); > > + > > + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); > > + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); > > + > > + /* Enabled High speed, disabled MIDI support. */ > > + pnp_write_config (dev, 0xF0, 0x02); > > + pnp_set_enable(dev, 1); > > + > > + /* Enable keyboard */ > > + dev = PNP_DEV (port, SCH4037_KBC); > > + pnp_set_logical_device(dev); > > + pnp_set_enable(dev, 0); > > + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ > > + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ > > + pnp_set_enable(dev, 1); > > + > > + pnp_exit_conf_state(dev); > > + > > +} > > + > > diff --git a/src/superio/smsc/sch4037/superio.c > > b/src/superio/smsc/sch4037/superio.c > > new file mode 100644 > > index 0000000..af4040f > > --- /dev/null > > +++ b/src/superio/smsc/sch4037/superio.c > > @@ -0,0 +1,123 @@ > > +/* > > + * This file is part of the coreboot project. > > + * > > + * Copyright (C) 2012 Advanced Micro Devices, Inc. > > + * > > + * This program is free software; you can redistribute it and/or > > +modify > > + * it under the terms of the GNU General Public License as published > > +by > > + * the Free Software Foundation; version 2 of the License. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA > > +02110-1301 USA */ > > + > > +/* RAM driver for the SMSC KBC1100 Super I/O chip */ > > Dito. > > [?] > > > Thanks, > > Paul From gerrit at coreboot.org Fri Feb 3 13:21:59 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 3 Feb 2012 13:21:59 +0100 Subject: [coreboot] Patch merged into coreboot/master: 75ff6ad libpayload: Provide interpretation of CMOS data structures References: Message-ID: the following patch was just integrated into master: commit 75ff6addfcd674cc2b3803f9b4216e1b9e338af7 Author: Patrick Georgi Date: Mon Jan 16 13:47:33 2012 +0100 libpayload: Provide interpretation of CMOS data structures Add new functions that allow using string based key/value access to CMOS, including support for enums. Change-Id: Ibe238eff4c5230e5f61004c88221cd34393873aa Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Fri Feb 3 13:21:57 2012, giving +2 See http://review.coreboot.org/585 for details. -gerrit From gerrit at coreboot.org Fri Feb 3 13:22:22 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 3 Feb 2012 13:22:22 +0100 Subject: [coreboot] Patch merged into coreboot/master: 788f600 libpayload: Expose options_checksum_valid References: Message-ID: the following patch was just integrated into master: commit 788f60034be9fa535f5c384d5513d2817c3920ad Author: Patrick Georgi Date: Mon Jan 16 15:03:11 2012 +0100 libpayload: Expose options_checksum_valid options_checksum_valid can be used as a fast test to identify invalid CMOS data by checking the checksum. Change-Id: I44635d4c5d389579ad82435907ba8658e1bd44bb Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Fri Feb 3 13:22:20 2012, giving +2 See http://review.coreboot.org/586 for details. -gerrit From gerrit at coreboot.org Fri Feb 3 13:22:51 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 3 Feb 2012 13:22:51 +0100 Subject: [coreboot] Patch merged into coreboot/master: 69470aa libpayload: Add iterators for CMOS variables References: Message-ID: the following patch was just integrated into master: commit 69470aacda54a628fb7d6437198fc2eddb314009 Author: Patrick Georgi Date: Mon Jan 16 15:39:57 2012 +0100 libpayload: Add iterators for CMOS variables Provide functions that pick the first CMOS variable defined in the cmos layout, and from there, the next one. Change-Id: Ie98146de7f6273089fc6fc0b232a4b94337cf8a3 Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Fri Feb 3 13:22:47 2012, giving +2 See http://review.coreboot.org/587 for details. -gerrit From hercares at gmail.com Fri Feb 3 19:13:42 2012 From: hercares at gmail.com (Julian Shulika) Date: Fri, 3 Feb 2012 20:13:42 +0200 Subject: [coreboot] Asus m2n-e mcp55 won't boot In-Reply-To: References: Message-ID: I tried,there are some changes if I use 3th and 4th memory slots, last POST code is 66 and turns off coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 mcp55_num:01 ht reset - coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef20 Unbuffered 333MHz 333MHz Interleaving disabled RAM end at 0x00080000 kB Ram3 Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=0e done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9f0 TrainDQSPos: MutualCSPassW[48] :000ce8c8 TrainDQSPos: MutualCSPassW[48] :000ce8c8 TrainDQSPos: MutualCSPassW[48] :000ce8c8 TrainDQSPos: MutualCSPassW[48] :000ce8d8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=57 done Total DQS Training : tsc [00]=000000001287da11 Total DQS Training : tsc [01]=000000001302b830 Total DQS Training : tsc [02]=00000000188e7b94 Total DQS Training : tsc [03]=00000000195ea260 Ram4 v_esp=000cef68 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (245760 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [10de/0369] ops PCI: 00:00.0 [10de/0369] enabled Capability: type 0x08 @ 0x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 0010 PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0360] bus ops PCI: 00:01.0 [10de/0360] enabled PCI: 00:01.1 [10de/0368] bus ops PCI: 00:01.1 [10de/0368] enabled PCI: 00:01.2 [10de/036a] enabled PCI: 00:01.3 [10de/036b] enabled PCI: 00:02.0 [10de/036c] ops PCI: 00:02.0 [10de/036c] enabled PCI: 00:02.1 [10de/036d] ops PCI: 00:02.1 [10de/036d] enabled PCI: 00:04.0 [10de/036e] ops PCI: 00:04.0 [10de/036e] enabled PCI: 00:05.0 [10de/037f] ops PCI: 00:05.0 [10de/037f] enabled PCI: 00:05.1 [10de/037f] ops PCI: 00:05.1 [10de/037f] enabled PCI: 00:05.2 [10de/037f] ops PCI: 00:05.2 [10de/037f] enabled PCI: 00:06.0 [10de/0370] bus ops PCI: 00:06.0 [10de/0370] enabled PCI: 00:06.1 [10de/0371] ops PCI: 00:06.1 [10de/0371] enabled PCI: 00:08.0 [10de/0373] ops PCI: 00:08.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0376] bus ops PCI: 00:0a.0 [10de/0376] enabled PCI: 00:0c.0 [10de/0374] bus ops PCI: 00:0c.0 [10de/0374] enabled PCI: 00:0d.0 [10de/0378] bus ops PCI: 00:0d.0 [10de/0378] enabled PCI: 00:0f.0 [10de/0377] bus ops PCI: 00:0f.0 [10de/0377] enabled scan_static_bus for PCI: 00:01.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.1 smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled scan_static_bus for PCI: 00:01.1 done do_pci_scan_bridge for PCI: 00:06.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:0f.0 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:01.1 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:01.1 read_resources bus 1 link: 0 done PCI: 00:06.0 read_resources bus 1 link: 0 PCI: 00:06.0 read_resources bus 1 link: 0 done PCI: 00:0a.0 read_resources bus 2 link: 0 PCI: 00:0a.0 read_resources bus 2 link: 0 done PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0f.0 read_resources bus 5 link: 0 PCI: 00:0f.0 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3000 flags 1 index0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 801 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flag0 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 i4 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.2 PNP: 002e.2 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 inde0 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 0 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.3 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i2 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 i4 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit 7ff flags c00001002 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c00 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c02 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.6 PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.7 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i0 PNP: 002e.7 resource base 800 size 8 align 3 gran 3 limit 7ff flags c000012 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags c00001004 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 inde0 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 0 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 1000 PNP: 002e.a PCI: 00:01.1 child on link 0 I2C: 01:50 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in0 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in0 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in4 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i0 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i4 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i8 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PCI: 00:01.2 PCI: 00:01.3 PCI: 00:01.3 resource base 0 size 40000 align 18 gran 18 limit ffffffff fla0 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag0 PCI: 00:02.1 PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 20 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.0 PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0 PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4 PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8 PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc PCI: 00:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:05.1 PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0 PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4 PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8 PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc PCI: 00:05.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:05.2 PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0 PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4 PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8 PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc PCI: 00:05.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:06.0 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102c PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 84 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:06.1 PCI: 00:06.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flag0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag0 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind4 PCI: 00:08.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 28 PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 20c PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:0e.0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff fl4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:01.1 60 * [0x0 - 0xff] io PCI: 00:01.1 64 * [0x400 - 0x4ff] io PCI: 00:01.1 68 * [0x800 - 0x8ff] io PCI: 00:01.1 10 * [0xc00 - 0xc3f] io PCI: 00:01.1 20 * [0xc40 - 0xc7f] io PCI: 00:01.1 24 * [0xc80 - 0xcbf] io PCI: 00:04.0 20 * [0xcc0 - 0xccf] io PCI: 00:05.0 20 * [0xcd0 - 0xcdf] io PCI: 00:05.1 20 * [0xce0 - 0xcef] io PCI: 00:05.2 20 * [0xcf0 - 0xcff] io PCI: 00:05.0 10 * [0x1000 - 0x1007] io PCI: 00:05.0 18 * [0x1008 - 0x100f] io PCI: 00:05.1 10 * [0x1010 - 0x1017] io PCI: 00:05.1 18 * [0x1018 - 0x101f] io PCI: 00:05.2 10 * [0x1020 - 0x1027] io PCI: 00:05.2 18 * [0x1028 - 0x102f] io PCI: 00:08.0 14 * [0x1030 - 0x1037] io PCI: 00:05.0 14 * [0x1038 - 0x103b] io PCI: 00:05.0 1c * [0x103c - 0x103f] io PCI: 00:05.1 14 * [0x1040 - 0x1043] io PCI: 00:05.1 1c * [0x1044 - 0x1047] io PCI: 00:05.2 14 * [0x1048 - 0x104b] io PCI: 00:05.2 1c * [0x104c - 0x104f] io PCI: 00:18.0 compute_resources_io: base: 1050 size: 2000 align: 12 gran: 12 lime PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 e PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:01.3 10 * [0x0 - 0x3ffff] mem PCI: 00:06.1 10 * [0x40000 - 0x43fff] mem PCI: 00:01.0 14 * [0x44000 - 0x44fff] mem PCI: 00:02.0 10 * [0x45000 - 0x45fff] mem PCI: 00:05.0 24 * [0x46000 - 0x46fff] mem PCI: 00:05.1 24 * [0x47000 - 0x47fff] mem PCI: 00:05.2 24 * [0x48000 - 0x48fff] mem PCI: 00:08.0 10 * [0x49000 - 0x49fff] mem PCI: 00:02.1 10 * [0x4a000 - 0x4a0ff] mem PCI: 00:08.0 18 * [0x4a100 - 0x4a1ff] mem PCI: 00:08.0 1c * [0x4a200 - 0x4a20f] mem PCI: 00:18.0 compute_resources_mem: base: 4a210 size: 100000 align: 20 gran: 20e PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 01 * [0x4000000 - 0x40fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 4100000 size: 4100000 align: 26 ge avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 skipping PNP: 002e.3 at 62 fixed resource, size=0! constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.5 constrain_resources: PNP: 002e.6 constrain_resources: PCI: 00:01.1 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PCI: 00:01.2 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:05.0 constrain_resources: PCI: 00:05.1 constrain_resources: PCI: 00:05.2 constrain_resources: PCI: 00:06.0 constrain_resources: PCI: 00:06.1 constrain_resources: PCI: 00:08.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limf Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gre PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:f Assigned: PCI: 00:01.1 60 * [0x1000 - 0x10ff] io Assigned: PCI: 00:01.1 64 * [0x1400 - 0x14ff] io Assigned: PCI: 00:01.1 68 * [0x1800 - 0x18ff] io Assigned: PCI: 00:01.1 10 * [0x1c00 - 0x1c3f] io Assigned: PCI: 00:01.1 20 * [0x1c40 - 0x1c7f] io Assigned: PCI: 00:01.1 24 * [0x1c80 - 0x1cbf] io Assigned: PCI: 00:04.0 20 * [0x1cc0 - 0x1ccf] io Assigned: PCI: 00:05.0 20 * [0x1cd0 - 0x1cdf] io Assigned: PCI: 00:05.1 20 * [0x1ce0 - 0x1cef] io Assigned: PCI: 00:05.2 20 * [0x1cf0 - 0x1cff] io Assigned: PCI: 00:05.0 10 * [0x2000 - 0x2007] io Assigned: PCI: 00:05.0 18 * [0x2008 - 0x200f] io Assigned: PCI: 00:05.1 10 * [0x2010 - 0x2017] io Assigned: PCI: 00:05.1 18 * [0x2018 - 0x201f] io Assigned: PCI: 00:05.2 10 * [0x2020 - 0x2027] io Assigned: PCI: 00:05.2 18 * [0x2028 - 0x202f] io Assigned: PCI: 00:08.0 14 * [0x2030 - 0x2037] io Assigned: PCI: 00:05.0 14 * [0x2038 - 0x203b] io Assigned: PCI: 00:05.0 1c * [0x203c - 0x203f] io Assigned: PCI: 00:05.1 14 * [0x2040 - 0x2043] io Assigned: PCI: 00:05.1 1c * [0x2044 - 0x2047] io Assigned: PCI: 00:05.2 14 * [0x2048 - 0x204b] io Assigned: PCI: 00:05.2 1c * [0x204c - 0x204f] io PCI: 00:18.0 allocate_resources_io: next_base: 2050 size: 2000 align: 12 gran: e PCI: 00:06.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:06.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0d.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0d.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0f.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0f.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:4100000 align:26 grf Assigned: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem Assigned: PCI: 00:18.0 01 * [0xfc000000 - 0xfc0fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc100000 size: 4100000 alige PCI: 00:18.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:18.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:06.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:06.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0f.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20f Assigned: PCI: 00:01.3 10 * [0xfc000000 - 0xfc03ffff] mem Assigned: PCI: 00:06.1 10 * [0xfc040000 - 0xfc043fff] mem Assigned: PCI: 00:01.0 14 * [0xfc044000 - 0xfc044fff] mem Assigned: PCI: 00:02.0 10 * [0xfc045000 - 0xfc045fff] mem Assigned: PCI: 00:05.0 24 * [0xfc046000 - 0xfc046fff] mem Assigned: PCI: 00:05.1 24 * [0xfc047000 - 0xfc047fff] mem Assigned: PCI: 00:05.2 24 * [0xfc048000 - 0xfc048fff] mem Assigned: PCI: 00:08.0 10 * [0xfc049000 - 0xfc049fff] mem Assigned: PCI: 00:02.1 10 * [0xfc04a000 - 0xfc04a0ff] mem Assigned: PCI: 00:08.0 18 * [0xfc04a100 - 0xfc04a1ff] mem Assigned: PCI: 00:08.0 1c * [0xfc04a200 - 0xfc04a20f] mem PCI: 00:18.0 allocate_resources_mem: next_base: fc04a210 size: 100000 align: 20e PCI: 00:06.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:06.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0f.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0f.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003e0000, basek=00000300, limitk=00080000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io > PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 mem> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:01.0 14 <- [0x00fc044000 - 0x00fc044fff] size 0x00001000 gran 0x0c mem PCI: 00:01.0 assign_resources, bus 0 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 62 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00o PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PCI: 00:01.0 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io PCI: 00:01.1 20 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000001c80 - 0x0000001cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 60 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 64 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 68 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.3 10 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.0 10 <- [0x00fc045000 - 0x00fc045fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00fc04a000 - 0x00fc04a0ff] size 0x00000100 gran 0x08 mem PCI: 00:04.0 20 <- [0x0000001cc0 - 0x0000001ccf] size 0x00000010 gran 0x04 io PCI: 00:05.0 10 <- [0x0000002000 - 0x0000002007] size 0x00000008 gran 0x03 io PCI: 00:05.0 14 <- [0x0000002038 - 0x000000203b] size 0x00000004 gran 0x02 io PCI: 00:05.0 18 <- [0x0000002008 - 0x000000200f] size 0x00000008 gran 0x03 io PCI: 00:05.0 1c <- [0x000000203c - 0x000000203f] size 0x00000004 gran 0x02 io PCI: 00:05.0 20 <- [0x0000001cd0 - 0x0000001cdf] size 0x00000010 gran 0x04 io PCI: 00:05.0 24 <- [0x00fc046000 - 0x00fc046fff] size 0x00001000 gran 0x0c mem PCI: 00:05.1 10 <- [0x0000002010 - 0x0000002017] size 0x00000008 gran 0x03 io PCI: 00:05.1 14 <- [0x0000002040 - 0x0000002043] size 0x00000004 gran 0x02 io PCI: 00:05.1 18 <- [0x0000002018 - 0x000000201f] size 0x00000008 gran 0x03 io PCI: 00:05.1 1c <- [0x0000002044 - 0x0000002047] size 0x00000004 gran 0x02 io PCI: 00:05.1 20 <- [0x0000001ce0 - 0x0000001cef] size 0x00000010 gran 0x04 io PCI: 00:05.1 24 <- [0x00fc047000 - 0x00fc047fff] size 0x00001000 gran 0x0c mem PCI: 00:05.2 10 <- [0x0000002020 - 0x0000002027] size 0x00000008 gran 0x03 io PCI: 00:05.2 14 <- [0x0000002048 - 0x000000204b] size 0x00000004 gran 0x02 io PCI: 00:05.2 18 <- [0x0000002028 - 0x000000202f] size 0x00000008 gran 0x03 io PCI: 00:05.2 1c <- [0x000000204c - 0x000000204f] size 0x00000004 gran 0x02 io PCI: 00:05.2 20 <- [0x0000001cf0 - 0x0000001cff] size 0x00000010 gran 0x04 io PCI: 00:05.2 24 <- [0x00fc048000 - 0x00fc048fff] size 0x00001000 gran 0x0c mem PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:06.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:06.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:06.1 10 <- [0x00fc040000 - 0x00fc043fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00fc049000 - 0x00fc049fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x0000002030 - 0x0000002037] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00fc04a100 - 0x00fc04a1ff] size 0x00000100 gran 0x08 mem PCI: 00:08.0 1c <- [0x00fc04a200 - 0x00fc04a20f] size 0x00000010 gran 0x04 mem PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0d.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0d.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0f.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0f.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0f.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flag0 PCI_DOMAIN: 0000 resource base f8000000 size 4100000 align 26 gran 0 limit fe0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0000 PCI_DOMAIN: 0000 resource base 2012/1/30 Julian Shulika > Hi. I compiled coreboot image for Asus m2n-e (mcp55,ite 8716f). This board > turns off after few seconds > The log from serial > > Welcome to minicom 2.5 > > OPTIONS: > > Compiled on Dec 4 2011, > 11:23:38. > Port > /dev/ttyS0 > > > Press CTRL-A Z for help on special > keys > > > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > started ap apicid: > SBLink=00 > NC node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x807f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x0, freq=0x6, > needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, > needs_reset=0x1 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x1 > after optimize_link_read_pointers_chain, > reset_needed=0x1 > mcp55_num:01 > > ht reset > - > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e40bef > Total DQS Training : tsc > [01]=000000001358f446 > Total DQS Training : tsc > [02]=0000000018d60c82 > Total DQS Training : tsc > [03]=0000000019771d46 > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > > Issuing > SOFT_RESET... > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e3eacf > Total DQS Training : tsc > [01]=000000001358d326 > Total DQS Training : tsc > [02]=0000000018d97cfa > Total DQS Training : tsc > [03]=00000000197a8c56 > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > D > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > > Issuing > SOFT_RESET... > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e3ed63 > Total DQS Training : tsc > [01]=000000001358f68a > Total DQS Training : tsc > [02]=0000000018d73a6a > Total DQS Training : tsc > [03]=0000000019784e5a > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > m > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > > Issuing > SOFT_RESET... > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e4504b > Total DQS Training : tsc > [01]=0000000013593c4a > Total DQS Training : tsc > [02]=0000000018d6d4b2 > Total DQS Training : tsc > [03]=000000001977e9ce > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From hagigatali at gmail.com Sun Feb 5 13:50:32 2012 From: hagigatali at gmail.com (ali hagigat) Date: Sun, 5 Feb 2012 16:20:32 +0330 Subject: [coreboot] How to port core boot Message-ID: My motherboard is Pentium III, Intel 82815 and ICH2. I want to port the Coreboot to this motherboard and I already have an assembly routine which initializes the RAM modules. Considering that what files i should alter exactly to get it done? I know that ASUS, MEW-AM is close to my board and it can be used as a start... From hagigatali at gmail.com Sun Feb 5 15:55:09 2012 From: hagigatali at gmail.com (ali hagigat) Date: Sun, 5 Feb 2012 18:25:09 +0330 Subject: [coreboot] coreboot is being stopped!! help Message-ID: My motherboard is: Pentium III, 82815, ICH2. I configured coreboot for Intel, d810e2cb motherboard. The coreboot stops printing the following lines on the serial port: coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... SMBus controller enabled No DIMM found in slot 0 No DIMM found in slot 1 DRP calculated to 0x00 BUFF_SC calculated to 0x0000 Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. Where is the problem. I just replaced sdram_enable() with a routine which I am sure that it initializes RAM correctly. The rest is the pure Coreboot code. From gerrit at coreboot.org Sun Feb 5 17:45:10 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Sun, 5 Feb 2012 17:45:10 +0100 Subject: [coreboot] Patch merged into coreboot/master: 22d10e9 SIO: condition compile Nuvoton WPCM450 early_init.c References: Message-ID: the following patch was just integrated into master: commit 22d10e91dec3aefb162cba777f32815bd745a295 Author: Kerry Sheh Date: Wed Feb 1 13:59:00 2012 +0800 SIO: condition compile Nuvoton WPCM450 early_init.c Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450 Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Reviewed-By: Patrick Georgi at Sun Feb 5 17:45:08 2012, giving +2 See http://review.coreboot.org/566 for details. -gerrit From kyosti.malkki at gmail.com Sun Feb 5 23:10:32 2012 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Mon, 06 Feb 2012 00:10:32 +0200 Subject: [coreboot] coreboot is being stopped!! help In-Reply-To: References: Message-ID: <1328479832.5785.41.camel@obelix> On Sun, 2012-02-05 at 18:25 +0330, ali hagigat wrote: > My motherboard is: Pentium III, 82815, ICH2. > > I configured coreboot for Intel, d810e2cb motherboard. The coreboot > stops printing the following lines on the serial port: > > coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... > SMBus controller enabled > No DIMM found in slot 0 > No DIMM found in slot 1 > DRP calculated to 0x00 > BUFF_SC calculated to 0x0000 > Loading image. > Searching for fallback/coreboot_ram > Check fallback/romstage > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 > Stage: done loading. > Jumping to image. > > Where is the problem. I just replaced sdram_enable() with a routine > which I am sure that it initializes RAM correctly. The rest is the > pure Coreboot code. > Hi Enable most verbose logging (8 ?) and post new logs. Also readers on the list have currently no clue how You obtained and modified your local copy of Coreboot. Your posted serial log appears exactly as from the coreboot sources. Double-check you have really changed the call to sdram_enable(), recompiled, flashed correctly etc. If you are running closed-source assembly code copy-pasted and mixed within coreboot, don't expect much assistance until you have convinced us that at the minimum ram_check() passes without errors after sdram_enable() :) The following patch contains a replacement ram_check() that I consider more reliable or thorough: http://review.coreboot.org/294 Thanks, KM From hillmands at gmail.com Mon Feb 6 05:37:02 2012 From: hillmands at gmail.com (David Hillman) Date: Sun, 05 Feb 2012 23:37:02 -0500 Subject: [coreboot] Asus M2V-MX problems In-Reply-To: <4F285EF6.4010604@assembler.cz> References: <4F285EF6.4010604@assembler.cz> Message-ID: <4F2F58EE.1030408@gmail.com> I have finally gotten another programmed BIOS chip. It turns out the old chip was damaged somehow. Here is the error that I got from Flashrom: ...Erasing flash chip...ERASE FAILED at 0x00000000! Expected =0xff, Read=0x4c, failed byte count from 0x00000000-0x00000fff: 0xfb3... I also got that error while trying to program the latest factory BIOS file using flashrom; flashrom was able to erase and program the new chip with no problems. My original problem of creating a proper image for this board still remains. Superiotool found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e. Any help would be appreciated. On 1/31/2012 4:36 PM, Rudolf Marek wrote: > Hi, > >> I was hoping to use the board above to experiment with Coreboot. The >> board has >> the same northbridge as the Asus M2V-MX SE (VIA K8M890) and the same >> southbridge >> as the Asus M2V (VIA 8237A). Both of those chipsets are fully >> supported. >> Thinking that maybe I can at least get the board to boot ASAP, I >> built Coreboot >> for the Asus M2V board to get the southbridge functionality. I also >> didn't use >> the M2V-MX SE profile because it has the SPI chip, while the M2V-MX >> board has a >> PLCC-32 chip. > > OK > > >> The board booted fine, except I have no video, serial port or ability >> to write >> to the BIOS chip. > > No video -> you need to include the extracted VGA bios from original > BIOS. No serial port looks like wrong superio setup. No ability to > write to the chip sounds interesting ? What do you mean by that. > Flashrom cannot no-long overwrite the chip content? Maybe just some > GPIO needs to be raised. Do you have more PLCC chips or other boards > so you can hotswap them? > >> I know the board booted fine because I was able to SSH into >> the box using a PCI network card. Considering that both the M2V and >> M2V-MX have >> the same southbridge chip, I don't understand why there was not >> serial port or >> write access to the BIOS chip. Can someone shed some light on that >> for me, please. > > Yep see above. I would suggest to run the superiotool (see utils dir) > and check what kind of superio is really there. Or even better provide > ./superiotool -d dump best with original bios running if possible. > > Then you just need to change few lines and you should get serial back. > I can even help with that but we need to know not only the chip there > but also how the chip is configured. > > For the VGA you need to use bios_extract and extract the VGA bios from > orig bios image and tell coreboot via menu to include that (you need > just pci ID lspci -n will tell) > >> My other problem is I would like to create a build profile for the >> M2V-MX using >> the code from the M2V for the southbridge and the code from the >> M2V-MX SE for >> the northbridge. Is that a good idea or would I have to do some >> other things? >> I learned C programming in 1993 and used it only until 1998; I am a >> little >> rusty. > > Well C is simple you will got it back soon. > >> My ability to make sense of low-level chipset stuff is also very >> narrow. > > If you ask good questions you will get answers. > >> However, I am a fast learner and I am desperate to get something >> accomplished for a homebrew thin client project that I have spent way >> too much >> time working on. >> >> My goal is to extend the life of boards that people send in for >> recycling by >> turning them into more reliable diskless information terminals. > > A nice coreboot use! > > Thanks > Rudolf From gerrit at coreboot.org Mon Feb 6 12:10:30 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 6 Feb 2012 12:10:30 +0100 Subject: [coreboot] New patch to review for coreboot: 81d14b7 Auto-generate directory layouts within Kconfig files References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/608 -gerrit commit 81d14b7fe2ed4c7d0557c2dbd58618509f44f102 Author: Ky?sti M?lkki Date: Mon Feb 6 11:49:52 2012 +0200 Auto-generate directory layouts within Kconfig files Goal of this patch is to remove some redundancy in the way compile directories are defined between Kconfig files and the devicetree.cb file. The script util/config-rules/autogen-kconfig.sh examines and operates recursively on selected subdirectories of src/ and creates temporary files under build/. For mainboard vendor and board directories the necessary choice entries are created with texts extracted from Kconfig files placed under the child directories. For results see: build/mainboard/Kconfig.autogen build/mainboard/vendor/Kconfig.autogen For the mainboard/vendor/board directory, devicetree.cb is parsed to generate select directives to include sources for all chip components. Few select directives will need to be renamed if this is taken into real use. For results see: build/mainboard/vendor/board/Kconfig.autogen Change-Id: Iaeededc70c771d478883d5f8f9a438ddfccc1df8 Signed-off-by: Ky?sti M?lkki --- util/config-rules/autogen-kconfig.sh | 159 ++++++++++++++++++++++++++++++++++ util/config-rules/extract_choice | 15 +++ 2 files changed, 174 insertions(+), 0 deletions(-) diff --git a/util/config-rules/autogen-kconfig.sh b/util/config-rules/autogen-kconfig.sh new file mode 100755 index 0000000..a0068f8 --- /dev/null +++ b/util/config-rules/autogen-kconfig.sh @@ -0,0 +1,159 @@ +#! /bin/sh +# +# Auto-generates Kconfig sections for coreboot directory layout +# +# For mainboard vendor and board directories the necessary choice +# entries are created with texts extracted from Kconfig files +# placed under the child directories. +# +# For the mainboard/vendor/board directory, devicetree.cb is parsed to +# generate select directives to include sources for all chip components. + +sedpath=`dirname $0` +choice_field=$sedpath/extract_choice + +autogen_sub() +{ + kconfig_in=$1/$2/Kconfig + + if test -s $kconfig_in ; then + echo 'source "'${kconfig_in}'"' >> $sub_source + fi + + if test "$spath" = "mainboard" -o "$spath" = "mainboard_vendor" ; then + sed -f $choice_field $kconfig_in >> $sub_choice + fi +} + +autogen_cfg() +{ +# bootblock generation triggered from Makefile +# bcfg="bootblock_autogen.h" +# build/util/sconfig/sconfig $2/$3 $1 -b $bcfg + + kcfg="Kconfig.sdep" + build/util/sconfig/sconfig $2/$3 $1 -k $kcfg + cat $1/$kcfg >> $this_sconfig + rm -f $1/$kcfg + +} + + +output_sub_choice() +{ + if test ! -s $sub_choice ; then return ; fi + + if test "$spath" = "mainboard" ; then + echo '\nchoice\n\tprompt "Mainboard vendor"\n\tdefault VENDOR_EMULATION\n' >> $Kconfig_out + cat $sub_choice >> $Kconfig_out + echo 'endchoice\n' >> $Kconfig_out + elif test "$spath" = "mainboard_vendor" ; then + echo 'choice\n\tprompt "Mainboard model"\n' >> $Kconfig_out + cat $sub_choice >> $Kconfig_out + echo 'endchoice\n' >> $Kconfig_out + else + cat $sub_choice >> $Kconfig_out + echo >> $Kconfig_out + fi +} + +output_sub_source() +{ + if test ! -s $sub_source ; then return ; fi + + cat $sub_source >> $Kconfig_out + echo >> $Kconfig_out +} + +output_this_sconfig() +{ + if test ! -s $this_sconfig ; then return ; fi + + cat $this_sconfig >> $Kconfig_out + echo >> $Kconfig_out +} + + +# splits $root to $spath/$vendor/$part +# sets $subirs to list of $root subdirectories +split_parent_directory() +{ + sdir=$(echo $parent | tr "/" " ") + lvl=-1 + spath=none + + for i in $sdir ; do + if test $lvl -eq -1 -a $i = src ; then + lvl=0 + subdirs="cpu mainboard northbridge southbridge superio" + elif test $lvl -eq 0 ; then + spath=${i} + lvl=1 + elif test $lvl -eq 1 ; then + spath=${spath}_vendor + vendor=${i} + lvl=2 + else + spath=${spath}_part + part=${i} + fi + done + if test $lvl -gt 0 ; then + subdirs=`find $parent -mindepth 1 -maxdepth 1 -type d -printf "%f\n" | sort` + fi +} + +output_parent() +{ + Kconfig_out=$objd/Kconfig.autogen + sub_source=`mktemp -p $objd` + sub_choice=`mktemp -p $objd` + this_sconfig=`mktemp -p $objd` + + # sets spath, vendor, part, subdirs + split_parent_directory + + # generate sub-directory includes + for subd in $subdirs ; do + echo $parent/$subd >> nextdirs.tmp + autogen_sub $parent $subd + done + + # generate mainboard devicetree.cb configs + if test "$spath" = "mainboard_vendor_part" ; then + autogen_cfg $objd $vendor $part + fi + + if test -s $sub_source -o -s $sub_choice -o -s $this_sconfig ; then + echo '## begin Kconfig.autogen\n' > $Kconfig_out + output_this_sconfig + output_sub_choice + output_sub_source + echo '## end Kconfig.autogen' >> $Kconfig_out + fi + rm -f $sub_source $sub_choice $this_sconfig +} + +# main + +find ./build -name Kconfig.autogen -delete +find ./build -name bootblock_autogen.h -delete + +roots=src +while test -n "$roots" ; do + rm -f nextdirs.tmp + + for parent in $roots ; do + objd=`echo $parent | sed -e "s/^src/build/g"` + mkdir -p $objd + output_parent + done + + if test -s nextdirs.tmp ; then + roots=`cat nextdirs.tmp` + else + roots= + fi + +done + diff --git a/util/config-rules/extract_choice b/util/config-rules/extract_choice new file mode 100644 index 0000000..7582778 --- /dev/null +++ b/util/config-rules/extract_choice @@ -0,0 +1,15 @@ +/if VENDOR_/ b choice +/if BOARD_/ b choice +/config MAINBOARD_VENDOR/,+3b name +/config MAINBOARD_PART_NUMBER/,+3b name +/^/ D +: choice +{ +s/if/config/ p +/^/ D +} +: name +{ +s/default/bool/ p +/^/ D +} From hagigatali at gmail.com Mon Feb 6 12:18:02 2012 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 6 Feb 2012 14:48:02 +0330 Subject: [coreboot] coreboot is being stopped!! help In-Reply-To: <1328479832.5785.41.camel@obelix> References: <1328479832.5785.41.camel@obelix> Message-ID: Thank you for the reply. My log level is 8 and I repeated my test and I added the following lines to src/mainboard/intel/d810e2cb/romstage.c: void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); //enable_smbus(); //dump_spd_registers(); //sdram_set_registers(); //sdram_set_spd_registers(); sdram_enable(); ram_check(0x02000000, 0x10000000); } Please look at the result by the serial port: coreboot-4.0-1959-g950f20a-dirty Mon Feb 6 14:33:44 IRST 2012 starting... Testing DRAM : 02000000 - 10000000 DRAM fill: 0x02000000-0x10000000 10000000 DRAM filled DRAM verify: 0x02000000-0x10000000 10000000 DRAM range verified. Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. It shows that RAM is OK between 32M and 256M bytes. I have not changed the Coreboot code much. I just replaced sdram_enable() with my routine and i am pretty sure that RAM is OK. and besides I have commented some lines inside the main function as i have copied. I got Coreboot by the Coreboot site and by git. Where is the problem you think? RAM check seems OK. Regards # # Automatically generated make config: don't edit # coreboot version: 4.0-1959-g950f20a-dirty # Mon Feb 6 14:33:41 2012 # # # General setup # # CONFIG_EXPERT is not set CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_SCANBUILD_ENABLE is not set # CONFIG_CCACHE is not set # CONFIG_USE_OPTION_TABLE is not set # CONFIG_COMPRESS_RAMSTAGE is not set # CONFIG_INCLUDE_CONFIG_FILE is not set # # Mainboard # # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTEC_GROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_DIGITAL_LOGIC is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PC_ENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/d810e2cb" CONFIG_MAINBOARD_PART_NUMBER="D810E2CB" CONFIG_IRQ_SLOT_COUNT=7 CONFIG_MAINBOARD_VENDOR="Intel" CONFIG_MAX_CPUS=1 CONFIG_MAX_PHYSICAL_CPUS=1 CONFIG_RAMTOP=0x200000 CONFIG_HEAP_SIZE=0x4000 CONFIG_RAMBASE=0x100000 CONFIG_VGA_BIOS_ID="8086,7121" CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0 CONFIG_SERIAL_CPU_INIT=y CONFIG_ACPI_SSDTX_NUM=0 # CONFIG_VGA_BIOS is not set CONFIG_STACK_SIZE=0x8000 # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_CONSOLE_POST is not set # CONFIG_PCI_64BIT_PREF_MEM is not set # CONFIG_MMCONF_SUPPORT_DEFAULT is not set CONFIG_BOARD_INTEL_D810E2CB=y # CONFIG_BOARD_INTEL_D945GCLF is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_JARRELL is not set # CONFIG_BOARD_INTEL_MTARVON is not set # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_XE7501DEVKIT is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_IOAPIC is not set CONFIG_SMP=y CONFIG_TTYS0_BAUD=9600 CONFIG_TTYS0_BASE=0x3f8 CONFIG_TTYS0_LCS=3 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 CONFIG_CONSOLE_SERIAL8250=y # CONFIG_PCI_ROM_RUN is not set # CONFIG_USBDEBUG is not set CONFIG_VAR_MTRR_HOLE=y # CONFIG_LIFT_BSP_APIC_ID is not set # CONFIG_WAIT_BEFORE_CPUS_INIT is not set # CONFIG_K8_REV_F_SUPPORT is not set CONFIG_BOARD_ROMSIZE_KB_512=y # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set CONFIG_COREBOOT_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set CONFIG_COREBOOT_ROMSIZE_KB=256 CONFIG_ROM_SIZE=0x40000 CONFIG_ARCH_X86=y # # Architecture (x86) # # CONFIG_AP_IN_SIPI_WAIT is not set CONFIG_ROMBASE=0xffff0000 CONFIG_MAX_REBOOT_CNT=3 # CONFIG_X86_BOOTBLOCK_SIMPLE is not set CONFIG_X86_BOOTBLOCK_NORMAL=y CONFIG_BOOTBLOCK_SOURCE="bootblock_normal.c" # CONFIG_UPDATE_IMAGE is not set # CONFIG_ROMCC is not set CONFIG_PC80_SYSTEM=y # CONFIG_HAVE_CMOS_DEFAULT is not set # CONFIG_BIG_ENDIAN is not set CONFIG_LITTLE_ENDIAN=y # # Chipset # # # CPU # CONFIG_CPU_ADDR_BITS=36 CONFIG_XIP_ROM_SIZE=0x10000 CONFIG_DIMM_SUPPORT=0x0004 # CONFIG_UDELAY_IO is not set CONFIG_HAVE_INIT_TIMER=y CONFIG_CPU_INTEL_MODEL_68X=y CONFIG_CPU_INTEL_SOCKET_FC_PGA370=y # CONFIG_SSE2 is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_CALIBRATE_WITH_IO is not set CONFIG_CACHE_AS_RAM=y CONFIG_MMX=y CONFIG_SSE=y # # Northbridge # CONFIG_VIDEO_MB=0 # CONFIG_CONSOLE_VGA_MULTI is not set CONFIG_NORTHBRIDGE_INTEL_I82810=y CONFIG_I810_VIDEO_MB_OFF=y # CONFIG_I810_VIDEO_MB_512KB is not set # CONFIG_I810_VIDEO_MB_1MB is not set # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_I82801BX=y # # Super I/O # CONFIG_SUPERIO_SMSC_SMSCSUPERIO=y # # Devices # # CONFIG_VGA_BRIDGE_SETUP is not set # CONFIG_VGA_ROM_RUN is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_AGP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # # Embedded Controllers # # # Generic Drivers # # CONFIG_DRIVERS_OXFORD_OXPCIE is not set # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_PCI_BUS_SEGN_BITS=0 # CONFIG_MMCONF_SUPPORT is not set # # Console # CONFIG_CONSOLE_SERIAL_COM1=y # CONFIG_CONSOLE_SERIAL_COM2 is not set # CONFIG_CONSOLE_SERIAL_COM3 is not set # CONFIG_CONSOLE_SERIAL_COM4 is not set # CONFIG_CONSOLE_SERIAL_115200 is not set # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set CONFIG_CONSOLE_SERIAL_9600=y # CONFIG_HAVE_USBDEBUG is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CONSOLE_LOGBUF is not set # CONFIG_NO_POST is not set CONFIG_POST_PORT=0x80 CONFIG_HAVE_UART_IO_MAPPED=y # CONFIG_HAVE_UART_MEMORY_MAPPED is not set # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_HAVE_ACPI_SLIC is not set CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_MAINBOARD_RESOURCES=y # CONFIG_HAVE_OPTION_TABLE is not set # CONFIG_PIRQ_ROUTE is not set # CONFIG_HAVE_SMI_HANDLER is not set # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_USE_WATCHDOG_ON_BOOT=y # CONFIG_VGA is not set CONFIG_GFXUMA=y CONFIG_HAVE_PIRQ_TABLE=y # CONFIG_GENERATE_ACPI_TABLES is not set # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_SMBIOS_TABLES is not set # # System tables # # CONFIG_WRITE_HIGH_TABLES is not set # CONFIG_MULTIBOOT is not set # # Payload # CONFIG_PAYLOAD_NONE=y # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_SEABIOS is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set # # VGA BIOS # # # Debugging # # CONFIG_GDB_STUB is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_LLSHELL is not set # CONFIG_TRACE is not set # CONFIG_AP_CODE_IN_CAR is not set # CONFIG_RAMINIT_SYSINFO is not set # CONFIG_ENABLE_APIC_EXT_ID is not set # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # # Deprecated # # CONFIG_BOARD_HAS_HARD_RESET is not set # CONFIG_BOARD_HAS_FADT is not set # CONFIG_HAVE_BUS_CONFIG is not set # CONFIG_PCIE_TUNING is not set CONFIG_ID_SECTION_OFFSET=0x80 On Mon, Feb 6, 2012 at 1:40 AM, Ky?sti M?lkki wrote: > On Sun, 2012-02-05 at 18:25 +0330, ali hagigat wrote: >> My motherboard is: Pentium III, 82815, ICH2. >> >> I configured coreboot for Intel, d810e2cb motherboard. The coreboot >> stops printing the following lines on the serial port: >> >> coreboot-4.0-1959-g950f20a-dirty Sun Feb ?5 17:52:27 IRST 2012 starting... >> SMBus controller enabled >> No DIMM found in slot 0 >> No DIMM found in slot 1 >> DRP calculated to 0x00 >> BUFF_SC calculated to 0x0000 >> Loading image. >> Searching for fallback/coreboot_ram >> Check fallback/romstage >> Check fallback/coreboot_ram >> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 >> Stage: done loading. >> Jumping to image. >> >> Where is the problem. I just replaced sdram_enable() with a routine >> which I am sure that it initializes RAM correctly. The rest is the >> pure Coreboot code. >> > > Hi > > Enable most verbose logging (8 ?) and post new logs. Also readers on the > list have currently no clue how You obtained and modified your local > copy of Coreboot. > > Your posted serial log appears exactly as from the coreboot sources. > Double-check you have really changed the call to sdram_enable(), > recompiled, flashed correctly etc. > > If you are running closed-source assembly code copy-pasted and mixed > within coreboot, don't expect much assistance until you have convinced > us that at the minimum ram_check() passes without errors after > sdram_enable() :) > > The following patch contains a replacement ram_check() that I consider > more reliable or thorough: http://review.coreboot.org/294 > > Thanks, > KM > From patrick at georgi-clan.de Mon Feb 6 12:37:03 2012 From: patrick at georgi-clan.de (Patrick Georgi) Date: Mon, 06 Feb 2012 12:37:03 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: Message-ID: <4F2FBB5F.6070503@georgi-clan.de> Am 05.02.2012 13:50, schrieb ali hagigat: > My motherboard is Pentium III, Intel 82815 and ICH2. I want to port > the Coreboot to this motherboard and I already have an assembly > routine which initializes the RAM modules. Where is that assembly routine from? Regards, Patrick From hagigatali at gmail.com Mon Feb 6 12:57:29 2012 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 6 Feb 2012 15:27:29 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <4F2FBB5F.6070503@georgi-clan.de> References: <4F2FBB5F.6070503@georgi-clan.de> Message-ID: I have developed the assembly code by myself and I am sure that it is OK as I have written a simple code in assembly which initializes RAM, serial port and hard disk. Every thing is OK in my code but I want to add this RAM code to Coreboot. I have already done it but Coreboot fails.... Regards On Mon, Feb 6, 2012 at 3:07 PM, Patrick Georgi wrote: > Am 05.02.2012 13:50, schrieb ali hagigat: >> My motherboard is Pentium III, Intel 82815 and ICH2. I want to port >> the Coreboot to this motherboard and I already have an assembly >> routine which initializes the RAM modules. > Where is that assembly routine from? > > > Regards, > Patrick > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From peter at stuge.se Mon Feb 6 15:45:06 2012 From: peter at stuge.se (Peter Stuge) Date: Mon, 6 Feb 2012 15:45:06 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> Message-ID: <20120206144507.22074.qmail@stuge.se> ali hagigat wrote: > I have developed the assembly code by myself and I am sure that it is > OK as I have written a simple code in assembly which initializes RAM, > serial port and hard disk. How did you verify that your code works? //Peter From svn at coreboot.org Mon Feb 6 16:00:02 2012 From: svn at coreboot.org (coreboot tracker) Date: Mon, 06 Feb 2012 16:00:02 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From hagigatali at gmail.com Mon Feb 6 16:47:40 2012 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 6 Feb 2012 19:17:40 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <20120206144507.22074.qmail@stuge.se> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> Message-ID: I can verify that by the assembly code i have. writing to any memory location and reading that. Also I tested it by ram_check() in Coreboot. Both are correct. The last post codes are 0x39, 0x80 and Coreboot seems to stop! Regards On Mon, Feb 6, 2012 at 6:15 PM, Peter Stuge wrote: > ali hagigat wrote: >> I have developed the assembly code by myself and I am sure that it is >> OK as I have written a simple code in assembly which initializes RAM, >> serial port and hard disk. > > How did you verify that your code works? > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From rhyotte at gmail.com Mon Feb 6 16:23:36 2012 From: rhyotte at gmail.com (gary sheppard) Date: Mon, 6 Feb 2012 07:23:36 -0800 Subject: [coreboot] Trinity Support Message-ID: Hello everyone, Recently AMD has stepped up their Trinity awareness. Many of us potential users are looking at Trinity very hard, as the hardware looks quite promising. If the community were to get together on 1 or 2 of the more interesting Trinity powered designs to offer substantial donations, would you the Dev community be interested in getting a couple of Trinity designs fully up and running? I for one do *NOT* want anything to do with UEFI ! Thank you for your consideration, Gary Sheppard -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Mon Feb 6 16:51:32 2012 From: peter at stuge.se (Peter Stuge) Date: Mon, 6 Feb 2012 16:51:32 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> Message-ID: <20120206155132.29374.qmail@stuge.se> ali hagigat wrote: > I can verify that by the assembly code i have. writing to any > memory location and reading that. Also I tested it by ram_check() > in Coreboot. Both are correct. This is not a very good memory test. Try running memtest86. It should be possible as long as you have set up serial correctly. //Peter From hagigatali at gmail.com Mon Feb 6 16:52:41 2012 From: hagigatali at gmail.com (ali hagigat) Date: Mon, 6 Feb 2012 19:22:41 +0330 Subject: [coreboot] FILO can not be built!! Message-ID: I received filo by the Coreboot site, and libpayload was made successfully but making filo stops with the following error: /root/bios/coreboot/payloads/filo> make Found Libpayload /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o /root/bios/coreboot/payloads/filo/i386/linux_load.c:752:5: error: expected identifier or '(' before numeric constant make: *** [/root/bios/coreboot/payloads/filo/build/i386/linux_load.o] Error 1 From peter at stuge.se Mon Feb 6 16:56:18 2012 From: peter at stuge.se (Peter Stuge) Date: Mon, 6 Feb 2012 16:56:18 +0100 Subject: [coreboot] FILO can not be built!! In-Reply-To: References: Message-ID: <20120206155618.29878.qmail@stuge.se> ali hagigat wrote: > I received filo by the Coreboot site, and libpayload was made > successfully but making filo stops with the following error: > > /root/bios/coreboot/payloads/filo> make > Found Libpayload > /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. > CC build/i386/context.o > CC build/i386/segment.o > CC build/i386/timer.o > CC build/i386/sys_info.o > CC build/i386/linux_load.o > /root/bios/coreboot/payloads/filo/i386/linux_load.c:752:5: error: > expected identifier or '(' before numeric constant > make: *** [/root/bios/coreboot/payloads/filo/build/i386/linux_load.o] Error 1 In open source software, when you encounter an error, you typically get to fix it yourself. At the very least, you should do everyone the courtesy of actually looking at the code and analyzing the problem on your own. //Peter From wangqingpei at gmail.com Mon Feb 6 17:10:07 2012 From: wangqingpei at gmail.com (QingPei Wang) Date: Tue, 7 Feb 2012 00:10:07 +0800 Subject: [coreboot] FILO can not be built!! In-Reply-To: <20120206155618.29878.qmail@stuge.se> References: <20120206155618.29878.qmail@stuge.se> Message-ID: hi ali, maybe at least you can provide the code version and the details about the configuration what you did with libpayload/filo. most of the time, there is a small chance that the code can not even being built. i think the libpayload configuration/install may have some problem which caused your error. I would like to say, would please use a more gentle tile about your problems? it may scaring me by "coreboot ** stop", "filo can not be built". :) Best wishes QingPei Wang Phone: 86+018930528086 On Mon, Feb 6, 2012 at 11:56 PM, Peter Stuge wrote: > op -------------- next part -------------- An HTML attachment was scrubbed... URL: From kyosti.malkki at gmail.com Mon Feb 6 20:21:08 2012 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Mon, 06 Feb 2012 21:21:08 +0200 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> Message-ID: <1328556068.5785.66.camel@obelix> On Mon, 2012-02-06 at 19:17 +0330, ali hagigat wrote: > I can verify that by the assembly code i have. writing to any memory > location and reading that. Also I tested it by ram_check() > in Coreboot. Both are correct. > > The last post codes are 0x39, 0x80 and Coreboot seems to stop! > Hi 0x80 seems like a reasonable POST from the very beginning of stage coreboot_ram. Continue your work with src/boot/hardwaremain.c; figure out whether you only lose serial communication or if the execution actually halts. Seems there is a case or two of possible infinite while() loops within the uart8250 serial console code. This is a wild guess, but the uart could end up in a bad state if transmit buffers are non-empty while divisors are programmed etc. Maybe raise the speed to more common and tested 115200. Regards, KM From gerrit at coreboot.org Tue Feb 7 00:06:09 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:06:09 +0100 Subject: [coreboot] Patch merged into coreboot/master: 5254c95 Inagua: Synchronize AMD/inagua mainboard. References: Message-ID: the following patch was just integrated into master: commit 5254c959694e2fae803b1d44f49dd277cc74f81f Author: Kerry Sheh Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: Synchronize AMD/inagua mainboard. AMD/persimmon mainboard code is derived from AMD/inagua mainbard. Persimmom update a lot in the last few month, sync these modification to inagua. Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Thu Jan 19 06:32:45 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:06:07 2012, giving +2 See http://review.coreboot.org/542 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:16:15 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:16:15 +0100 Subject: [coreboot] Patch merged into coreboot/master: d9c56fa libpayload: Fix EHCI driver References: Message-ID: the following patch was just integrated into master: commit d9c56faebed52ad5c583c6337d5b01d2c09ed9bd Author: Patrick Georgi Date: Tue Jan 31 14:37:59 2012 +0100 libpayload: Fix EHCI driver When converting EHCI to not use bitfields, two offsets were converted incorrectly. Change-Id: I0bb4bad0eee42e54ad4fd53d6c35b107e227c41a Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Tue Jan 31 16:50:48 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:16:02 2012, giving +2 See http://review.coreboot.org/593 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:21:19 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:21:19 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7a36e53 Move SeaBIOS output out of coreboot source tree References: Message-ID: the following patch was just integrated into master: commit 7a36e53735757b71befbeba7452666d1754e2463 Author: Stefan Reinauer Date: Sat Jan 21 10:34:22 2012 -0800 Move SeaBIOS output out of coreboot source tree Make sure SeaBIOS build files live under $(OUT) instead of in the source tree. Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec Signed-off-by: Stefan Reinauer Build-Tested: build bot (Jenkins) at Sat Jan 21 20:00:27 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:20:33 2012, giving +2 See http://review.coreboot.org/552 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:23:06 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:23:06 +0100 Subject: [coreboot] Patch merged into coreboot/master: 18d1ed4 Inagua: devicetree.cb update References: Message-ID: the following patch was just integrated into master: commit 18d1ed4c01ca2f9c8286347d9c8987d098072254 Author: Kerry Sheh Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: devicetree.cb update Add the slots connection comments to devicetree.cb Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Thu Jan 19 06:13:25 2012, giving +1 See http://review.coreboot.org/545 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:24:29 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:24:29 +0100 Subject: [coreboot] Patch merged into coreboot/master: f8df726 Inagua: Inagua GNB ddi lanes and pcie lanes config update References: Message-ID: the following patch was just integrated into master: commit f8df7260201d3f579e552ba3239a94d70f631d0b Author: Kerry Sheh Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: Inagua GNB ddi lanes and pcie lanes config update DDI lanes configuration update to make LVDS works. Pcie lanes configuration update to make MiniPcie slot 1 works. Change-Id: I40aaf28119b946b3a6383ceff7c734c9c3fd313e Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Thu Jan 19 06:02:58 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:24:24 2012, giving +2 See http://review.coreboot.org/544 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:24:50 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:24:50 +0100 Subject: [coreboot] Patch merged into coreboot/master: cabbc86 Inagua: mainboard specific GPIO setting References: Message-ID: the following patch was just integrated into master: commit cabbc861db8d8551fb7ef725b3ce6cbbbb507996 Author: Kerry Sheh Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: mainboard specific GPIO setting Pcie device connected to Hudson/sb800 southbridge GPP training can works, by applying this mainbaind specific GPIO PCIE De-Assert setting. Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Thu Jan 19 06:23:12 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:04:45 2012, giving +2 See http://review.coreboot.org/543 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:25:44 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:25:44 +0100 Subject: [coreboot] Patch merged into coreboot/master: 9f6afb5 Inagua: Indent and wihtespace cleanup References: Message-ID: the following patch was just integrated into master: commit 9f6afb597ae330d2246182bb0878fb76bc1212bd Author: Kerry Sheh Date: Thu Jan 19 13:25:55 2012 +0800 Inagua: Indent and wihtespace cleanup Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Thu Jan 19 05:51:59 2012, giving +1 See http://review.coreboot.org/547 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:10:47 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:10:47 +0100 Subject: [coreboot] Patch merged into coreboot/master: 60668d2 Add OPROM mapping support to coreboot References: Message-ID: the following patch was just integrated into master: commit 60668d28abfcf877f1e0592178beb2646efb47ee Author: Stefan Reinauer Date: Mon Jan 23 14:17:52 2012 -0800 Add OPROM mapping support to coreboot This allows to add a PCI ID mapping function for option roms so that the same option rom can be used for a series of devices / PCI IDs. Intel and AMD often use the same option rom for a number of PCI devices with differend IDs. A function to implement such a mapping could look like this (or anything else appropriate): /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do * the mapping ourselfes */ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev=vendev; switch(vendev) { case 0xa0118086: new_vendev=0xa0018086; break; } return new_vendev; } Change-Id: I1be7fe113b895075d43ea48fe706b039cef136d2 Build-Tested: build bot (Jenkins) at Mon Jan 23 23:34:49 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:09:36 2012, giving +2 See http://review.coreboot.org/573 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 00:33:10 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 00:33:10 +0100 Subject: [coreboot] Patch merged into coreboot/master: b7929ad Fix multipleVGA cards resource conflict on Windows References: Message-ID: the following patch was just integrated into master: commit b7929add7bf1b40795e0a16ab08fc47858971ccc Author: Kerry Sheh Date: Wed Jan 4 20:51:47 2012 +0800 Fix multipleVGA cards resource conflict on Windows If multiple VGA-compatible legacy graphic cards decode the IO range 3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF. Windows 7 complain a resource conflict, so only one VGA card can works at the same time. There is a discussion in coreboot mail list before, please reference thread: "how to prevent legacy resource conflictwith multipleVGA cards" http://www.coreboot.org/pipermail/coreboot/2010-October/061508.html Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict, Please see the following linux dmesg log, more information can be found in Linux source dir Documentation/vgaarbiter.txt. But it seems that windows don't dealwith this conflict. ~# dmesg | grep -i vgaarb [ 0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem [ 0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l [ 0.780051] vgaarb: loaded [ 0.784049] vgaarb: bridge control possible 0000:01:00.0 [ 0.788050] vgaarb: bridge control possible 0000:00:01.0 For the second legacy graphic device, coreboot already disabled the IO and MEM decode in function set_vga_bridge_bits(). But it will be enabled again in function pci_set_resource(), if the second legacy vga-compatible graphic device take any IO/MEM resources. Following log printed by enable_resources() shows the problem: ...snip... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 1022/1410 PCI: 00:01.0 cmd <- 07 <== The first graphic device PCI: 00:01.1 subsystem <- 1022/1410 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 07 ...snip... PCI: 01:00.0 cmd <- 03 <== The second graphic device PCI: 01:00.1 cmd <- 02 PCI: 02:00.0 cmd <- 02 PCI: 03:00.0 cmd <- 03 done. ...snip... The IO & MEM decoding on the second vga graphic device should be disabled. Please reference PCI spec. section 3.10 in detail. set_vga_bridge_bits() would do this work for us, it did the right thing, but was put to the wrong place, the setting would be overwritten by assign_resources() later. In order to make sure the set_vga_bridge_bits() setting not be overwritten by others, moving the call of set_vga_bridge_bits() to the end of dev_configure(), instead of at the beginning. This patch resolved the dual graphic cards resource conflict in windows7, multiple vga-compatible graphic cards can work together in windows7. Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d Build-Tested: build bot (Jenkins) at Wed Jan 4 13:17:09 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 7 00:32:50 2012, giving +2 See http://review.coreboot.org/489 for details. -gerrit From r.marek at assembler.cz Tue Feb 7 00:37:56 2012 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 07 Feb 2012 00:37:56 +0100 Subject: [coreboot] How to port core boot In-Reply-To: <1328556068.5785.66.camel@obelix> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> Message-ID: <4F306454.6070405@assembler.cz> > Seems there is a case or two of possible infinite while() loops within > the uart8250 serial console code. This is a wild guess, but the uart Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is always better to boot than to have perfect serial output ;) But in this case I would think memory is not 100% OK. Worth to check if 1M->3M is OK (this is where coreboot ramstage goes) Thanks Rudolf From gerrit at coreboot.org Tue Feb 7 10:51:00 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 10:51:00 +0100 Subject: [coreboot] New patch to review for coreboot: 5364fa9 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/609 -gerrit commit 5364fa99949aae6485bf9a4f123f48a09b348cba Author: Kerry Sheh Date: Tue Feb 7 18:45:55 2012 +0800 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/include/device/pci_ids.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fcd31c0..60399ef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -284,6 +284,9 @@ #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 + #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 #define PCI_DEVICE_ID_ATI_SB600_IDE 0x438C From gerrit at coreboot.org Tue Feb 7 10:51:01 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 10:51:01 +0100 Subject: [coreboot] Patch set updated for coreboot: aaed6c6 RD890: AMD RD890/SR56X0 CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit aaed6c6f999c0002f560fda4402909c393fd406b Author: Kerry Sheh Date: Tue Feb 7 18:46:12 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 257 ++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1159 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..5eaefd1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include + +#include "amd.h" //cimx typedef +#include +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; /// + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..208e5f1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ + From gerrit at coreboot.org Tue Feb 7 10:51:02 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 10:51:02 +0100 Subject: [coreboot] Patch set updated for coreboot: 4a1a46e AGESA F15: AGESA family15 model 00-0fh northbridge wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/556 -gerrit commit 4a1a46e82adbc3c2b4104caea492c648cf91e38f Author: Kerry Sheh Date: Tue Feb 7 18:46:09 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/agesa/Kconfig | 3 +- src/northbridge/amd/agesa/Makefile.inc | 3 +- src/northbridge/amd/agesa/family15/Kconfig | 49 + src/northbridge/amd/agesa/family15/Makefile.inc | 20 + src/northbridge/amd/agesa/family15/bootblock.c | 25 + src/northbridge/amd/agesa/family15/chip.h | 24 + src/northbridge/amd/agesa/family15/northbridge.c | 1168 ++++++++++++++++++++ src/northbridge/amd/agesa/family15/northbridge.h | 26 + .../amd/agesa/family15/root_complex/Kconfig | 2 + .../amd/agesa/family15/root_complex/chip.h | 24 + 10 files changed, 1342 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 3bcb0bb..2ed9fd5 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,4 +24,5 @@ config CONSOLE_VGA_MULTI source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig +source src/northbridge/amd/agesa/family15/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1da8f60..eef1cd3 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,3 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..52f7a1e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY15 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY15 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 +config MMCONF_BUS_NUMBER + int + default 64 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family15/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 + +source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..255fe10 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c new file mode 100644 index 0000000..fc62c3e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..cec1fc4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_ops; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c new file mode 100644 index 0000000..b0fc91d --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -0,0 +1,1168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "root_complex/chip.h" +#include "northbridge.h" +#include "chip.h" + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; ilink[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; ienabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure not exist, usable + * @retval 0 resource exist, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } +} + + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " ", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + device_t io_hub = NULL; + u32 next_unitid = 0x18; + nodeid = amdfam15_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ + if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_10H_NB_HT, +}; + +struct chip_operations northbridge_amd_agesa_family15_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); + + +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} +#endif + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_TABLES_SIZE, high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 6) {//f15 + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ +#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ +#define CFG_PLAT_NUM_IO_APICS 3 +#endif + if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { + lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, cpu_path.apic.apic_id); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " "); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + + +struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") + .enable_dev = root_complex_enable_dev, +}; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h new file mode 100644 index 0000000..7606b32 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15_H +#define NORTHBRIDGE_AMD_AGESA_FAM15_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig new file mode 100644 index 0000000..032b836 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h new file mode 100644 index 0000000..06b3510 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops; From gerrit at coreboot.org Tue Feb 7 10:51:02 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 10:51:02 +0100 Subject: [coreboot] Patch set updated for coreboot: 8789a10 AGESA F15: AGESA family15 model 00-0fh cpu wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/555 -gerrit commit 8789a10ea5b3eae29754b0f5182dd876d1a1703b Author: Kerry Sheh Date: Tue Feb 7 11:38:46 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/cpu/amd/agesa/Kconfig | 7 +- src/cpu/amd/agesa/Makefile.inc | 3 +- src/cpu/amd/agesa/family15/Kconfig | 82 +++++++++++++++ src/cpu/amd/agesa/family15/Makefile.inc | 30 ++++++ src/cpu/amd/agesa/family15/chip.h | 23 +++++ src/cpu/amd/agesa/family15/chip_name.c | 25 +++++ src/cpu/amd/agesa/family15/model_15_init.c | 147 ++++++++++++++++++++++++++++ src/include/cpu/amd/amdfam15.h | 41 ++++++++ 8 files changed, 356 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 60bb74b..8eaa11d 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,11 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_AGESA + bool + default n + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig +source src/cpu/amd/agesa/family15/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..fb536dd 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..0f2f920 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -0,0 +1,82 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15 + bool + select PCI_IO_CFG_EXT + select AMD_AGESA + +if CPU_AMD_AGESA_FAMILY15 + +config CPU_AMD_SOCKET_G34 + bool + default n + help + AMD G34 Socket + +config CPU_AMD_SOCKET_C32 + bool + default n + help + AMD C32 Socket + +config CPU_AMD_SOCKET_AM3R2 + bool + default n + help + AMD AM3r2 Socket + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY15 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..936d3c8 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -0,0 +1,30 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + +ramstage-y += chip_name.c +driver-y += model_15_init.c + diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h new file mode 100644 index 0000000..0171e7f --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family15_ops; + +struct cpu_amd_agesa_family15_config { +}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c new file mode 100644 index 0000000..963a423 --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family15_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c new file mode 100644 index 0000000..d100338 --- /dev/null +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr.lo = 0x04040404; msr.hi = 0x04040404; + wrmsr(0x259, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache (); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h new file mode 100644 index 0000000..3d300de --- /dev/null +++ b/src/include/cpu/amd/amdfam15.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM15_H +#define CPU_AMD_FAM15_H + +#include + +#define MCI_STATUS 0x00000401 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f + +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define CU_CFG_MSR 0xC0011023 +#define CU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +static msr_t rdmsr_amd(u32 index); +static void wrmsr_amd(u32 index, msr_t msr); + +#endif /* CPU_AMD_FAM15_H */ From gerrit at coreboot.org Tue Feb 7 13:01:53 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:01:53 +0100 Subject: [coreboot] Patch set updated for coreboot: 3354884 AGESA F15: AGESA family15 model 00-0fh cpu wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/555 -gerrit commit 33548842f15fb467b28a0a899b4ff84ceccf5116 Author: Kerry Sheh Date: Tue Feb 7 20:31:35 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/cpu/amd/agesa/Kconfig | 22 ++++- src/cpu/amd/agesa/Makefile.inc | 3 +- src/cpu/amd/agesa/family15/Kconfig | 82 +++++++++++++++ src/cpu/amd/agesa/family15/Makefile.inc | 30 ++++++ src/cpu/amd/agesa/family15/chip.h | 23 +++++ src/cpu/amd/agesa/family15/chip_name.c | 25 +++++ src/cpu/amd/agesa/family15/model_15_init.c | 147 ++++++++++++++++++++++++++++ src/include/cpu/amd/amdfam15.h | 41 ++++++++ 8 files changed, 371 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 60bb74b..631724b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,26 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_AGESA + bool + default n + +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 or more kinds of + processor family, compiling several cpu families agesa code + will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig +source src/cpu/amd/agesa/family15/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..fb536dd 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..0f2f920 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -0,0 +1,82 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15 + bool + select PCI_IO_CFG_EXT + select AMD_AGESA + +if CPU_AMD_AGESA_FAMILY15 + +config CPU_AMD_SOCKET_G34 + bool + default n + help + AMD G34 Socket + +config CPU_AMD_SOCKET_C32 + bool + default n + help + AMD C32 Socket + +config CPU_AMD_SOCKET_AM3R2 + bool + default n + help + AMD AM3r2 Socket + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY15 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..936d3c8 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -0,0 +1,30 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + +ramstage-y += chip_name.c +driver-y += model_15_init.c + diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h new file mode 100644 index 0000000..0171e7f --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family15_ops; + +struct cpu_amd_agesa_family15_config { +}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c new file mode 100644 index 0000000..963a423 --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family15_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c new file mode 100644 index 0000000..d100338 --- /dev/null +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr.lo = 0x04040404; msr.hi = 0x04040404; + wrmsr(0x259, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache (); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h new file mode 100644 index 0000000..3d300de --- /dev/null +++ b/src/include/cpu/amd/amdfam15.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM15_H +#define CPU_AMD_FAM15_H + +#include + +#define MCI_STATUS 0x00000401 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f + +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define CU_CFG_MSR 0xC0011023 +#define CU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +static msr_t rdmsr_amd(u32 index); +static void wrmsr_amd(u32 index, msr_t msr); + +#endif /* CPU_AMD_FAM15_H */ From gerrit at coreboot.org Tue Feb 7 13:04:04 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:04:04 +0100 Subject: [coreboot] Patch set updated for coreboot: d59002f pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/609 -gerrit commit d59002f19e9dc56bd94c61f055b26bef62943540 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/include/device/pci_ids.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fcd31c0..60399ef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -284,6 +284,9 @@ #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 + #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 #define PCI_DEVICE_ID_ATI_SB600_IDE 0x438C From gerrit at coreboot.org Tue Feb 7 13:05:27 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:05:27 +0100 Subject: [coreboot] Patch set updated for coreboot: 9bf1cc6 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/556 -gerrit commit 9bf1cc623520b43d95ff7e55770fa30590f3b953 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/agesa/Kconfig | 3 +- src/northbridge/amd/agesa/Makefile.inc | 3 +- src/northbridge/amd/agesa/family15/Kconfig | 49 + src/northbridge/amd/agesa/family15/Makefile.inc | 20 + src/northbridge/amd/agesa/family15/bootblock.c | 25 + src/northbridge/amd/agesa/family15/chip.h | 24 + src/northbridge/amd/agesa/family15/northbridge.c | 1168 ++++++++++++++++++++ src/northbridge/amd/agesa/family15/northbridge.h | 26 + .../amd/agesa/family15/root_complex/Kconfig | 2 + .../amd/agesa/family15/root_complex/chip.h | 24 + 10 files changed, 1342 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 3bcb0bb..2ed9fd5 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,4 +24,5 @@ config CONSOLE_VGA_MULTI source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig +source src/northbridge/amd/agesa/family15/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1da8f60..eef1cd3 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,3 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..52f7a1e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY15 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY15 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 +config MMCONF_BUS_NUMBER + int + default 64 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family15/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 + +source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..255fe10 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c new file mode 100644 index 0000000..fc62c3e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..cec1fc4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_ops; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c new file mode 100644 index 0000000..b0fc91d --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -0,0 +1,1168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#include "root_complex/chip.h" +#include "northbridge.h" +#include "chip.h" + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; ilink[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; ienabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure not exist, usable + * @retval 0 resource exist, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } +} + + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " ", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + device_t io_hub = NULL; + u32 next_unitid = 0x18; + nodeid = amdfam15_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ + if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_10H_NB_HT, +}; + +struct chip_operations northbridge_amd_agesa_family15_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); + + +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} +#endif + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_TABLES_SIZE, high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 6) {//f15 + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ +#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ +#define CFG_PLAT_NUM_IO_APICS 3 +#endif + if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { + lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, cpu_path.apic.apic_id); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " "); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + + +struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") + .enable_dev = root_complex_enable_dev, +}; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h new file mode 100644 index 0000000..7606b32 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15_H +#define NORTHBRIDGE_AMD_AGESA_FAM15_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig new file mode 100644 index 0000000..032b836 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h new file mode 100644 index 0000000..06b3510 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops; From hagigatali at gmail.com Tue Feb 7 13:19:12 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 15:49:12 +0330 Subject: [coreboot] FILO can not be built!! In-Reply-To: References: <20120206155618.29878.qmail@stuge.se> Message-ID: When i get the source code of Coreboot it has, some files as the source codes of libpayload and filo. Should i use these codes or i should download them from Coreboot pages? Regards On Mon, Feb 6, 2012 at 7:40 PM, QingPei Wang wrote: > hi ali, > ? ?maybe at least you can provide the code?version and the details about the > configuration what you did with libpayload/filo. > most of the time, there is a small chance that the code can not even being > built. > i think the libpayload configuration/install may have some problem which > caused your error. > > I would like to say, would please use a more gentle tile about your > problems? > it may scaring me by "coreboot ** stop", "filo can not be built". > > :) > > > > > Best wishes > QingPei Wang > Phone: 86+018930528086 > > > On Mon, Feb 6, 2012 at 11:56 PM, Peter Stuge wrote: >> >> op > > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From gerrit at coreboot.org Tue Feb 7 13:22:10 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:22:10 +0100 Subject: [coreboot] Patch set updated for coreboot: 4a4a0d7 SIO: Add smsc sio1036 superio References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/563 -gerrit commit 4a4a0d7a619c73d2ab748bab27b834bb4148a0b0 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc sio1036 superio Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1036/Makefile.inc | 21 ++++ src/superio/smsc/sio1036/chip.h | 34 +++++++ src/superio/smsc/sio1036/sio1036.h | 25 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 101 ++++++++++++++++++++ src/superio/smsc/sio1036/superio.c | 122 +++++++++++++++++++++++++ 7 files changed, 306 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index ddd5b96..d4f07ec 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,5 +40,7 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SIO1036 + bool config SUPERIO_SMSC_SCH4037 bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bfdc68e..d07afea 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,4 +29,5 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc new file mode 100644 index 0000000..4e48899 --- /dev/null +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c + diff --git a/src/superio/smsc/sio1036/chip.h b/src/superio/smsc/sio1036/chip.h new file mode 100644 index 0000000..abed430 --- /dev/null +++ b/src/superio/smsc/sio1036/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_SIO1036_CHIP_H +#define SUPERIO_SMSC_SIO1036_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_kbc1100_ops; + +struct superio_smsc_sio1036_config { + struct uart8250 com1; +}; + +#endif //SUPERIO_SMSC_SIO1036_CHIP_H + diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h new file mode 100644 index 0000000..cdd5a8b --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SIO1036_SP1 0 /* Com1 */ + +#define UART_POWER_DOWN (1 << 7) +#define LPT_POWER_DOWN (1 << 2) +#define IR_OUPUT_MUX (1 << 6) + diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c new file mode 100644 index 0000000..980e8c5 --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include "sio1036.h" + +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3F8 +#endif +static inline void sio1036_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static inline void sio1036_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static u8 detect_sio1036_chip(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + unsigned data; + sio1036_enter_conf_state (dev); + data = pnp_read_config (dev, 0x0D); + sio1036_exit_conf_state(dev); + /* detect smsc sio1036 chip */ + if (data == 0x82) { + /* Found SMSC SIO1036 chip */ + return 0; + } + else { + return -1; + }; +} + +static inline void sio1036_early_init(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + + if (detect_sio1036_chip(port) != 0) { + /* Not found SMSC SIO1036 */ + return; + } + sio1036_enter_conf_state (dev); + + /* Enable SMSC UART 0 */ + /* Valid configuration cycle */ + pnp_write_config (dev, 0x00, 0x28); + + /* PP power/mode/cr lock */ + pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN); + pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN); + + /*Auto power management*/ + pnp_write_config (dev, 0x07, 0x00 ); + + /*ECP FIFO threhod */ + pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX); + + /*GPIO direction register 2 */ + pnp_write_config (dev, 0x033, 0x00); + + /*UART Mode */ + pnp_write_config (dev, 0x0C, 0x02); + + /* GPIO polarity regisgter 2 */ + pnp_write_config (dev, 0x034, 0x00); + + /* Enable SMSC UART 0 */ + /*Set base io address */ + pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + + /* Set UART IRQ onto 0x04 */ + pnp_write_config (dev, 0x28, 0x04); + + sio1036_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c new file mode 100644 index 0000000..2522d92 --- /dev/null +++ b/src/superio/smsc/sio1036/superio.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC SIO1036 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sio1036.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sio1036_pnp_set_resources(device_t dev); +static void sio1036_pnp_enable_resources(device_t dev); +static void sio1036_pnp_enable(device_t dev); +static void sio1036_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sio1036_pnp_set_resources, + .enable_resources = sio1036_pnp_enable_resources, + .enable = sio1036_pnp_enable, + .init = sio1036_init, +}; + +static struct pnp_info pnp_dev_info[] = { + {}, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sio1036_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sio1036_init(device_t dev) +{ + struct superio_smsc_sio1036_config *conf = dev->chip_info; + struct resource *res0, *res1; + + + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + default: + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + From gerrit at coreboot.org Tue Feb 7 13:22:47 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:22:47 +0100 Subject: [coreboot] Patch set updated for coreboot: ecc400d SIO: Add smsc/sch4037 superio support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit ecc400d056c52a805d64599c87b7ba6db184c3bc Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 ++++ src/superio/smsc/sch4037/chip.h | 34 +++++++ src/superio/smsc/sch4037/sch4037.h | 34 +++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 69 ++++++++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++++++++++++++ 7 files changed, 285 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..8dff3b8 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..9c74062 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config(dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..eebcacd --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_SPEW, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} From gerrit at coreboot.org Tue Feb 7 13:23:31 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:23:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 3904286 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/561 -gerrit commit 3904286e9ec165e90eab5466ef6f1fe6482ce4ef Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/southbridge/amd/Makefile.inc | 1 + src/southbridge/amd/cimx/Kconfig | 3 +- src/southbridge/amd/cimx/Makefile.inc | 3 +- src/southbridge/amd/cimx/sb700/Amd.h | 363 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/AmdSbLib.h | 84 ++++++ src/southbridge/amd/cimx/sb700/Kconfig | 63 +++++ src/southbridge/amd/cimx/sb700/Makefile.inc | 31 +++ src/southbridge/amd/cimx/sb700/Platform.h | 87 +++++++ src/southbridge/amd/cimx/sb700/bootblock.c | 97 +++++++ src/southbridge/amd/cimx/sb700/cbtypes.h | 53 ++++ src/southbridge/amd/cimx/sb700/chip.h | 42 +++ src/southbridge/amd/cimx/sb700/chip_name.c | 25 ++ src/southbridge/amd/cimx/sb700/early.c | 102 ++++++++ src/southbridge/amd/cimx/sb700/late.c | 319 +++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.c | 195 ++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.h | 30 +++ src/southbridge/amd/cimx/sb700/sb_cimx.h | 51 ++++ src/southbridge/amd/cimx/sb700/smbus.c | 266 ++++++++++++++++++++ src/southbridge/amd/cimx/sb700/smbus.h | 82 ++++++ 19 files changed, 1895 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 406a0b3..54245f2 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -12,6 +12,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 8f12b90..f61b75a 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -21,5 +21,6 @@ config AMD_SB_CIMX bool default n +source src/southbridge/amd/cimx/sb700/Kconfig source src/southbridge/amd/cimx/sb800/Kconfig source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 421a11c..80c6378 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h new file mode 100644 index 0000000..fbd5531 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Amd.h @@ -0,0 +1,363 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +// AGESA Types and Definitions +#ifndef NULL +#define NULL 0 +#endif + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT + +#ifndef Int16FromChar +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#endif +#ifndef Int32FromChar +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +#endif + +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') + +typedef unsigned int AGESA_STATUS; + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h new file mode 100644 index 0000000..dbf43ca --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef signed char *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + unsigned int AMDLogo; + unsigned long long CreatorID; + unsigned int Version1; + unsigned int Version2; + unsigned int Version3; + unsigned int ModuleInfoOffset; + unsigned int EntryPoint; + unsigned int ImageBase; + unsigned int RelocTableOffset; + unsigned int ImageSize; + unsigned short CheckSum; + unsigned char ImageType; + unsigned char Reserved2; +} CIMFILEHEADER; + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS AmdSbDispatcher (IN void *pConfig); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig new file mode 100644 index 0000000..27338fc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_CIMX_SB700 + bool + select IOAPIC + select AMD_SB_CIMX + +if SOUTHBRIDGE_AMD_CIMX_SB700 +config SATA_CONTROLLER_MODE + hex + default 0x0 + help + 0x0 = Native IDE mode. + 0x1 = RAID mode. + 0x2 = AHCI mode. + 0x3 = Legacy IDE mode. + 0x4 = IDE->AHCI mode. + 0x5 = AHCI mode as 7804 ID (AMD driver). + 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). + +config PCIB_ENABLE + bool + default n + help + n = Disable PCI Bridge Device 14 Function 4. + y = Enable PCI Bridge Device 14 Function 4. + +config ACPI_SCI_IRQ + hex + default 0x9 + help + Set SCI IRQ to 9. +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/cimx/sb700/bootblock.c" + +config REDIRECT_SBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Southbridge CIMX Trace to serial console" + default n + help + This Option allows you to redirect the AMD Southbridge CIMX Trace + debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. +endif #SOUTHBRIDGE_AMD_CIMX_SB700 + diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..7929cf7 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,31 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# SB700 Platform Files + +romstage-y += early.c +romstage-y += smbus.c + +ramstage-y += late.c + +driver-y += smbus.c +driver-y += lpc.c + + diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h new file mode 100644 index 0000000..15e5b07 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_PLATFORM_H_ +#define _AMD_SB_CIMx_PLATFORM_H_ + +#pragma pack(push,1) + +#include "cbtypes.h" +#include +#include +#ifdef NULL +#undef NULL +#endif +#define NULL 0 + +typedef struct _EXT_PCI_ADDR{ + UINT32 Reg :16; + UINT32 Func:3; + UINT32 Dev :5; + UINT32 Bus :8; +}EXT_PCI_ADDR; + + +typedef union _PCI_ADDR{ + UINT32 ADDR; + EXT_PCI_ADDR Addr; +}PCI_ADDR; + + +#ifdef CIM_DEBUG + +#if CIM_DEBUG & 2 +void TraceDebug( UINT32 Level, CHAR8 *Format, ...); +#define TRACE(Arguments) TraceDebug Arguments +#else +#define TRACE(Arguments) +#endif + +#if CIM_DEBUG & 1 +void TraceCode ( UINT32 Level, UINT32 Code); +#define TRACECODE(Arguments) TraceCode Arguments +#else +#define TRACECODE(Arguments) +#endif +#else + #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL + #define TRACE(Arguments) printk Arguments + #else + #define TRACE(Arguments) do {} while(0) + #endif + #define TRACECODE(Arguments) +#endif + +#define FIXUP_PTR(ptr) ptr + +#pragma pack(pop) + +#include "OEM.h" +#include "Amd.h" +#include "ACPILIB.h" +#include "SBTYPE.h" +#include "sbAMDLIB.h" +#include "SBCMNLIB.h" +#include "SB700.h" +#include "SBDEF.h" + +#define DMSG_SB_TRACE 0x02 + +#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_ + diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c new file mode 100644 index 0000000..401c039 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include + + +#if CONFIG_CONSOLE_POST == 1 + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif // CONFIG_TTYS0_DIV + +#define UART_LCS CONFIG_TTYS0_LCS + +#endif // CONFIG_CONSOLE_POST == 1 + + +static void sb700_enable_rom(void) +{ + u32 word; + u32 dword; + device_t dev; + + dev = PCI_DEV(0, 0x14, 0x03); + /* SB700 LPC Bridge 0:20:3:44h. + * BIT6: Port Enable for serial port 0x3f8-0x3ff + * BIT29: Port Enable for KBC port 0x60 and 0x64 + * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 + */ + dword = pci_io_read_config32(dev, 0x44); + //dword |= (1<<6) | (1<<29) | (1<<30) ; + /*Turn on all of LPC IO Port decode enable */ + dword = 0xffffffff; + pci_io_write_config32(dev, 0x44, dword); + + /* SB700 LPC Bridge 0:20:3:48h. + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) + * BIT6: Port Enable for RTC IO 0x70-0x73 + * BIT21: Port Enable for Port 0x80 + */ + dword = pci_io_read_config32(dev, 0x48); + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + pci_io_write_config32(dev, 0x48, dword); + + /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Set the 4MB enable bits */ + word = pci_io_read_config16(dev, 0x6c); + word = 0xFFC0; + pci_io_write_config16(dev, 0x6c, word); +} + +static void bootblock_southbridge_init(void) +{ + /* Setup the rom access for 2M */ + sb700_enable_rom(); +} diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h new file mode 100644 index 0000000..d37e1e3 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/cbtypes.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include + +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN; +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +#endif diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h new file mode 100644 index 0000000..ef294f4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CIMX_SB700_CHIP_H_ +#define _CIMX_SB700_CHIP_H_ + +extern struct chip_operations southbridge_amd_cimx_sb700_ops; + +/* + * configuration set in mainboard/devicetree.cb + * boot_switch_sata_ide: + * 0 -set SATA as primary, PATA(IDE) as secondary. + * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, + * gpp_configuration - The configuration of General Purpose Port A/B/C/D + * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] + * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] + * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ +struct southbridge_amd_cimx_sb700_config +{ + u32 boot_switch_sata_ide : 1; + u8 gpp_configuration; +}; + +#endif /* _CIMX_SB700_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c new file mode 100644 index 0000000..13d2276 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("AMD South Bridge SB700") +}; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c new file mode 100644 index 0000000..c899320 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +//#include +#include +#include +#include /* inl, outl */ +#include /* device_t */ +#include "Platform.h" +#include "sb_cimx.h" +#include "sb700_cfg.h" /*sb700_cimx_config*/ +#include +#include +#include "smbus.h" + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus) +{ + device_t dev; + + printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), + bus); + + printk(BIOS_SPEW, "SB700 - Early.c - %s - End.\n", __func__); + return (dev >> 15) & 0x1f; +} +#endif + +/** + * @brief Enable A-Link Express Configuration DMA Access. + */ + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of sbPowerOnInit entry point. + */ +void sb_Poweron_Init(void) +{ + AMDSBCFG sb_early_cfg; + + printk(BIOS_SPEW, "cimx/sb700 early.c, %s() Start:\n", __func__); + /* Enable A-Link Base Address */ + //sb_enable_alink (); + + sb700_cimx_config(&sb_early_cfg); + sbPowerOnInit(&sb_early_cfg); + printk(BIOS_SPEW, "cimx/sb700 early.c, %s() End\n", __func__); +} + +void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, base); + reg8 = pci_read_config8(dev, 0x48); + reg8 |= 1 << 2; + pci_write_config8(dev, 0x48, reg8); +} + +void sb7xx_51xx_disable_wideio(u8 wio_index) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, 0); + reg8 = pci_read_config8(dev, 0x48); + reg8 &= ~(1 << 2); + pci_write_config8(dev, 0x48, reg8); +} + diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c new file mode 100644 index 0000000..4e51e0a --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -0,0 +1,319 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include /* device_t */ +#include /* device_operations */ +#include +#include +#include /* smbus_bus_operations */ +#include /* printk */ +#include "lpc.h" /* lpc_read_resources */ +#include "Platform.h" /* Platfrom Specific Definitions */ +#include "sb_cimx.h" +#include "sb700_cfg.h" /* sb700 Cimx configuration */ +#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ + + +/*implement in mainboard.c*/ +void set_pcie_reset(void); +void set_pcie_dereset(void); + +static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config +static AMDSBCFG *sb_config = &sb_late_cfg; + + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_config Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* config) +{ + u32 ret = 0; + + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n"); + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n"); + return ret; +} + + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static void lpc_enable_resources(device_t dev) +{ + + printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__); + pci_dev_enable_resources(dev); + lpc_enable_childrens_resources(dev); + printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); +} + +static struct device_operations lpc_ops = { + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_LPC, +}; + + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390 +}; + +#if CONFIG_USBDEBUG +static void usb_set_resources(struct device *dev) +{ + struct resource *res; + u32 base; + u32 old_debug; + + printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__); + old_debug = get_ehci_debug(); + set_ehci_debug(0); + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x10); + set_ehci_debug(old_debug); + if (!res) + return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); + printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__); +} +#endif + + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, +#if CONFIG_USBDEBUG + .set_resources = usb_set_resources, +#else + .set_resources = pci_dev_set_resources, +#endif + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +/* + * The pci id of usb ctrl 0 and 1 are the same. + */ +static const struct pci_driver usb_ohci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci3_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1, +}; + +static const struct pci_driver usb_ehci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci4_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */ +}; + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver azalia_driver __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_HDA, +}; + + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_PCI, +}; + + +static void sb700_enable(device_t dev) +{ + struct southbridge_amd_cimx_sb700_config *sb_chip = + (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info); + + printk(BIOS_DEBUG, "sb700_enable() "); + switch (dev->path.pci.devfn) { + case (0x11 << 3) | 0: /* 0:11.0 SATA */ + sb700_cimx_config(sb_config); + if (dev->enabled) { + sb_config->SataController = CIMX_OPTION_ENABLED; + if (1 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. + else if (0 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. + } else { + sb_config->SataController = CIMX_OPTION_DISABLED; + } + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + break; + + case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { +#if 1 + u32 ioapic_base; + printk(BIOS_DEBUG, "sm_init().\n"); + ioapic_base = IO_APIC_ADDR; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ +#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); +#elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); +#else +#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" +#endif +#endif + } + break; + + case (0x14 << 3) | 1: /* 0:14:1 IDE */ + break; + + case (0x14 << 3) | 2: /* 0:14:2 HDA */ + if (dev->enabled) { + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; + } + printk(BIOS_DEBUG, "hda enabled\n"); + } else { + sb_config->AzaliaController = AZALIA_DISABLE; + printk(BIOS_DEBUG, "hda disabled\n"); + } + break; + + + case (0x14 << 3) | 3: /* 0:14:3 LPC */ + break; + + case (0x14 << 3) | 4: /* 0:14:4 PCI */ + break; + + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + /* call CIMX entry after last device enable */ + sb_Before_Pci_Init(); + break; + + default: + break; + } +} + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("ATI SB700") + .enable_dev = sb700_enable, +}; + +/** + * @brief SB Cimx entry point sbBeforePciInit wrapper + */ +void sb_Before_Pci_Init(void) +{ + printk(BIOS_SPEW, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbBeforePciInit(sb_config); + printk(BIOS_SPEW, "sb700 %s End\n", __func__); +} + +void sb_After_Pci_Init(void) +{ + printk(BIOS_SPEW, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbAfterPciInit(sb_config); + printk(BIOS_SPEW, "sb700 %s End\n", __func__); +} + +void sb_Late_Post(void) +{ + printk(BIOS_SPEW, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_LATE_POST_INIT; + //AmdSbDispatcher(sb_config); + sbLatePost(sb_config); + printk(BIOS_SPEW, "sb700 %s End\n", __func__); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c new file mode 100644 index 0000000..e43193a --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc.h" +#include +#include +#include /* printk */ +#include + +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xfc, i; + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} + +void lpc_read_resources(device_t dev) +{ + struct resource *res; + + printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + + pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + compact_resources(dev); + printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); +} + +void lpc_set_resources(struct device *dev) +{ + struct resource *res; + + printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); + pci_dev_set_resources(dev); + + /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS); + pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); + printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whos children's resources are to be enabled + * + */ +void lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + + printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__); + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); +/* + printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); +*/ + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + reg |= (1 << 29); + break; + case 0x3f8: /* COM1 */ + reg |= (1 << 6); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 7); + break; + case 0x378: /* Parallal 1 */ + reg |= (1 << 0); + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 26); + break; + case 0x220: /* Aduio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 18); + break; + case 0x400: + reg_x |= (1 << 16); + break; + case 0x480: + reg_x |= (1 << 17); + break; + case 0x500: + reg_x |= (1 << 18); + break; + case 0x580: + reg_x |= (1 << 19); + break; + case 0x4700: + reg_x |= (1 << 22); + break; + case 0xfd60: + reg_x |= (1 << 23); + break; + default: + if (var_num >= 3) + continue; /* only 3 var ; compact them ? */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + break; + case 1: + reg_x |= (1 << 24); + break; + case 2: + reg_x |= (1 << 25); + break; + } + reg_var[var_num++] = + base & 0xffff; + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 2: + pci_write_config16(dev, 0x90, reg_var[2]); + case 1: + pci_write_config16(dev, 0x66, reg_var[1]); + case 0: + //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata + break; + } + printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h new file mode 100644 index 0000000..edb13f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_LPC_H_ +#define _SB700_LPC_H_ + + +#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ + +void lpc_read_resources(device_t dev); +void lpc_set_resources(device_t dev); +void lpc_enable_childrens_resources(device_t dev); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h new file mode 100644 index 0000000..632e4cd --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_H_ +#define _CIMX_H_ + +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +#define REV_SB700_A11 0x11 +#define REV_SB700_A12 0x12 + + +/** + * AMD South Bridge CIMx entry point wrapper + */ +void sb_Poweron_Init(void); +void sb_Before_Pci_Init(void); +void sb_After_Pci_Init(void); +void sb_Mid_Post_Init(void); +void sb_Late_Post(void); + +void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base); +void sb7xx_51xx_disable_wideio(u8 wio_index); + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c new file mode 100644 index 0000000..e155aca --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "smbus.h" +#include /* printk */ + +static inline void smbus_delay(void) +{ + outb(inb(0x80), 0x80); +} + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { /* ready now */ + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; /* mask off reserved bits */ + if (val & 0x1c) { + return -5; /* error */ + } + if (val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + return 0; + } + } while (--loops); + + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n"); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n"); + return byte; +} + +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n"); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n"); + return 0; +} + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n"); + return byte; +} + +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n"); + return 0; +} + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); +} + +/* space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n"); + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n"); +} + diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h new file mode 100644 index 0000000..10e0874 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_SMBUS_H_ +#define _SB700_SMBUS_H_ + +//#include +#include /* SMBUS0_BASE_ADDRESS */ +#ifndef SMBUS0_BASE_ADDRESS +#error SMBUS0_BASE_ADDRESS not define +#endif +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif //_SB700_SMBUS_H_ From gerrit at coreboot.org Tue Feb 7 13:23:32 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:23:32 +0100 Subject: [coreboot] Patch set updated for coreboot: c8657a8 RD890: AMD RD890/SR56X0 CIMX wrapper References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit c8657a8bf8e98a9e19db9f248fd44a72e747632d Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 257 ++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1159 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..5eaefd1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include + +#include "amd.h" //cimx typedef +#include +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; /// + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..208e5f1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ + From gerrit at coreboot.org Tue Feb 7 13:24:26 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:24:26 +0100 Subject: [coreboot] Patch set updated for coreboot: b6bebf4 SIO: Winbond w83627dhg update References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565 -gerrit commit b6bebf4968019fd38a7086cbf350a9c26b4451a3 Author: Kerry Sheh Date: Tue Feb 7 20:32:37 2012 +0800 SIO: Winbond w83627dhg update 1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/superio/winbond/w83627dhg/Makefile.inc | 2 + src/superio/winbond/w83627dhg/early_serial.c | 29 +++++++++++++++++++++++-- src/superio/winbond/w83627dhg/superio.c | 4 +- src/superio/winbond/w83627dhg/w83627dhg.h | 6 +++++ 6 files changed, 38 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 3183c1c..4a1b1c3 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -39,7 +39,7 @@ #include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627dhg/early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index f2525e3..621c27f 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -40,7 +40,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627dhg/early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc index 0b0bb8b..09df47e 100644 --- a/src/superio/winbond/w83627dhg/Makefile.inc +++ b/src/superio/winbond/w83627dhg/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2008 Uwe Hermann +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,5 +19,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index f530dc6..e0be8de 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Uwe Hermann + * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,24 +19,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include #include #include "w83627dhg.h" -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83627dhg_enable_serial(device_t dev, u16 iobase) +void w83627dhg_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -44,3 +47,23 @@ static void w83627dhg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +/** + * Select Pin 89, Pin 90 function as I2C interface SDA, SCL. + * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or + * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} + */ +void w83627dhg_enable_i2c(device_t dev) +{ + u8 val; + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + + val = pnp_read_config(dev, 0x2A); + val |= 1 << 1; + pnp_write_config(dev, 0x2A, val); + + pnp_exit_ext_func_mode(dev); +} + diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1771c26..a936ce1 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -26,13 +26,13 @@ #include "chip.h" #include "w83627dhg.h" -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { outb(0xaa, dev->path.pnp.port); } diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 74761e9..158e60b 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Uwe Hermann + * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,4 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ +void pnp_enter_ext_func_mode(device_t dev); +void pnp_exit_ext_func_mode(device_t dev); +void w83627dhg_enable_serial(device_t dev, u16 iobase); +void w83627dhg_enable_i2c(device_t dev); + #endif From gerrit at coreboot.org Tue Feb 7 13:24:24 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:24:24 +0100 Subject: [coreboot] Patch set updated for coreboot: 7078147 Mainboard: Supermicro/h8qgi mainboard update References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567 -gerrit commit 70781479459d047979d698685b7f1393e9178e95 Author: Kerry Sheh Date: Tue Feb 7 20:32:38 2012 +0800 Mainboard: Supermicro/h8qgi mainboard update 1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/supermicro/h8qgi/Kconfig | 20 +- src/mainboard/supermicro/h8qgi/Makefile.inc | 16 ++- src/mainboard/supermicro/h8qgi/acpi_tables.c | 95 ++++++--- src/mainboard/supermicro/h8qgi/agesawrapper.c | 145 ++++++++------ src/mainboard/supermicro/h8qgi/buildOpts.c | 111 +++++++++-- src/mainboard/supermicro/h8qgi/devicetree.cb | 86 ++------ src/mainboard/supermicro/h8qgi/dimmSpd.c | 85 ++++---- src/mainboard/supermicro/h8qgi/dsdt.asl | 217 ++++++++------------ src/mainboard/supermicro/h8qgi/fadt.c | 61 ++---- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 30 +-- src/mainboard/supermicro/h8qgi/irq_tables.c | 8 +- src/mainboard/supermicro/h8qgi/mainboard.c | 40 +++-- src/mainboard/supermicro/h8qgi/mptable.c | 59 +++--- src/mainboard/supermicro/h8qgi/platform_cfg.h | 54 +++++ src/mainboard/supermicro/h8qgi/platform_oem.c | 4 +- src/mainboard/supermicro/h8qgi/platform_oem.h | 29 --- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 274 +++++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/rd890_cfg.h | 174 ++++++++++++++++ src/mainboard/supermicro/h8qgi/reset.c | 66 ++++++ src/mainboard/supermicro/h8qgi/romstage.c | 50 +++--- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 142 +++++++++++++ src/mainboard/supermicro/h8qgi/sb700_cfg.h | 237 +++++++++++++++++++++ 22 files changed, 1466 insertions(+), 537 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig old mode 100755 new mode 100644 index 5df0bb4..e900ea8 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select CPU_AMD_AGESA_FAMILY10 - select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX - select NORTHBRIDGE_AMD_AGESA_FAMILY10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_HARD_RESET select SERIAL_CPU_INIT - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 + select TINY_BOOTBLOCK #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default supermicro/h8qgi diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc old mode 100755 new mode 100644 index b09c5ca..d49289b --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,15 +17,29 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c +ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += platform_oem.c +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx +AGESA_ROOT ?= $(AGESA_PREFIX)/f15 +NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890 +SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700 + +subdirs-y += ../../../../$(AGESA_ROOT) + diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl old mode 100755 new mode 100644 diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index b8ce0b0..7314283 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end) #endif extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) #else apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif - apicid_sr5650 = apicid_sp5100 + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -89,18 +89,18 @@ unsigned long acpi_fill_madt(unsigned long current) 0 ); - /* IOAPIC on rs5690 */ - gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, dword, gsi_base ); - } + } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, //BUS @@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - //acpi_header_t *ssdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - /* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */ -#ifdef UNUSED_CODE - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); ssdt = (acpi_header_t *) current; - current += ssdt->length; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } - else { + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #endif - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 5bb4a9d..aeeab11 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,7 +34,6 @@ #include "Dispatcher.h" #include "cpuCacheInit.h" #include "amdlib.h" -#include "platform_oem.h" #include "Filecode.h" #include "heapManager.h" #include /* CPU_SPECIFIC_SERVICES */ @@ -54,7 +53,7 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -//VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL; /*---------------------------------------------------------------------------------------- @@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); static UINT32 agesawrapper_amdinitcpuio(VOID) { @@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) UINT32 node; UINT32 sblink; UINT32 i; + UINT32 TOM; /* get the number of coherent nodes in the system */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); @@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) PciData = 0x00000A03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set F0000000-FFFFFFFF to Node0 sbLink. */ + /* Set TOM1-FFFFFFFF to Node0 sbLink. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); PciData = 0x00FFFF00; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciData = 0x00F00000 | 0x03; + TOM = (UINT32)MsrRead(TOP_MEM); + PciData = (TOM >> 8) | 0x03; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */ + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x0000E000; + PciData = 0x00FFF000; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00009033; + PciData = 0x00000033; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800; + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; @@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID) AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdResetParams.HtConfig.Depth = 0; //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default @@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly(AmdEarlyParamsPtr); - status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + status = AmdInitEarly(AmdEarlyParamsPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID) UINT16 i; UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr; UINT32 TscRateInMhz; CPU_SPECIFIC_SERVICES *FamilySpecificServices; @@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + if (status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + } AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID) BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParams; LibAmdMemFill(&AmdParamStruct, 0, @@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitEnv(EnvParams); if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return (UINT32)status; @@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick) return AcpiWheaMce; case PICK_WHEA_CMC: return AcpiWheaCmc; -/* case PICK_ALIB: return AcpiAlib; -*/ default: return NULL; } @@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); @@ -405,34 +426,49 @@ UINT32 agesawrapper_amdinitmid(VOID) UINT32 agesawrapper_amdinitlate(VOID) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - Status = AmdInitLate(&AmdLateParams); + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); ASSERT(Status == AGESA_SUCCESS); } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - //AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } @@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr) ASSERT(Status <= AGESA_UNSUPPORTED); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - // AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } @@ -784,10 +811,6 @@ static void agesa_error(EVENT_PARAMS *event) printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); break; - case MEM_ERROR_ECC_DIS: - printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); - break; - case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); break; @@ -1141,6 +1164,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) */ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) { + printk(BIOS_DEBUG, "enter in %s\n", __func__); AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; @@ -1164,6 +1188,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } + printk(BIOS_DEBUG, "exit %s \n", __func__); return (UINT32)Status; } diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 02cf79b..5837349 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -70,7 +70,10 @@ ////#define BLDOPT_REMOVE_SLIT TRUE //#define BLDOPT_REMOVE_WHEA TRUE //#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + +/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + //#define BLDOPT_REMOVE_HT_ASSIST TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE @@ -107,7 +110,7 @@ #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] = {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + /* Coherent link deemphasis. */ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3}, @@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] = {HT_SOCKET3, HT_LINK1B, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3A, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, - }; CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = { - {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull}, + {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818}, {CPU_LIST_TERMINAL} }; @@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET FALSE//TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE #define AGESA_ENTRY_INIT_RECOVERY FALSE #define AGESA_ENTRY_INIT_EARLY TRUE #define AGESA_ENTRY_INIT_POST TRUE @@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +/* +#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#endif +#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#endif +*/ + +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ #include "MaranelloInstall.h" /*---------------------------------------------------------------------------------------- @@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = *---------------------------------------------------------------------------------------- */ +//reference BKDG Table87: works +#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM. +#define SEED_A 0x54 +#define SEED_B 0x4D +#define SEED_C 0x45 +#define SEED_D 0x40 + +#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM. +//4B 41 51 + /* * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable @@ -486,6 +528,40 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // + + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED), + + /* HW_RXEN_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + */ + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_B, ALL_DIMMS, + SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, + SEED_B), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_C, ALL_DIMMS, + SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, + SEED_C), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_D, ALL_DIMMS, + SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, + SEED_D), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 PSO_END }; @@ -493,7 +569,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { /* * These tables are optional and may be used to adjust memory timing settings */ - //HY Customer table UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout old mode 100755 new mode 100644 diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb old mode 100755 new mode 100644 index 9afaac7..9d77a73 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,20 +16,18 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa/family10/root_complex +chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa/family10 - device lapic 0x10 on end + chip cpu/amd/agesa/family15 + device lapic 0x20 on end #f15 + #device lapic 0x10 on end #f10 end end device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3 - chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 @@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 register "port_enable" = "0x2104" - end #southbridge/amd/sr5650 - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB1 device pci 12.1 on end # USB1 @@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex device pci 13.1 on end # USB2 device pci 13.2 on end # USB2 device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec. + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8qgi not have codec. device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy @@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/sp5100 + end # southbridge/amd/cimx/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - - - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3 - end - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - - device pci 1b.0 on end - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - - - device pci 1c.0 on end - device pci 1c.1 on end - device pci 1c.2 on end - device pci 1c.3 on end - device pci 1c.4 on end - - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.4 on end - - - device pci 1e.0 on end - device pci 1e.1 on end - device pci 1e.2 on end - device pci 1e.3 on end - device pci 1e.4 on end - - device pci 1f.0 on end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.4 on end - - end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex + device pci 18.5 on end #f15 + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #pci_domain -end #northbridge/amd/agesa/family10/root_complex +end #northbridge/amd/agesa/family15/root_complex diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c index 4ff21ee..db7d6b7 100644 --- a/src/mainboard/supermicro/h8qgi/dimmSpd.c +++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,17 +35,27 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * @param reg -GPIO Cntrl Register * @param out -GPIO bitmap * @param out -GPIO enable bitmap + * @return old setting */ -static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) +static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable) { - u8 value; - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS - - value = pci_read_config8(sm_dev, reg); - value &= ~(enable); - value |= out; - value &= ~(enable << 4); - pci_write_config8(sm_dev, reg, value); + u8 value, ret; + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + + value = pci_read_config8(sm_dev, reg); + ret = value; + value &= ~(enable); + value |= out; + value &= ~(enable << 4); + pci_write_config8(sm_dev, reg, value); + + return ret; +} + +static void sp5100_restore_gpio(u8 reg, u8 value) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); + pci_write_config8(sm_dev, reg, value); } /*----------------------------------------------------------------------------- @@ -55,31 +65,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm /* socket 0 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 1 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 2 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 3 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, }; @@ -177,25 +187,17 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) return 0; } -static void writePmReg (int reg, int data) -{ - outb(reg, 0xCD6); - outb(data, 0xCD7); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz + outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */ } AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { + AGESA_STATUS status; int spdAddress, ioBase; u8 i2c_channel; + u8 backup; device_t sm_dev; if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; @@ -211,7 +213,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * 1 0 channel 3 (Socket3) * 1 1 channel 4 (Socket4) */ - sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03); + backup = sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03); spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) @@ -219,11 +221,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA /* * SMBus Base Address was set during southbridge early setup. - * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000 + * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default */ sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0); ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0); setupFch(ioBase); - return readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + sp5100_restore_gpio(SP5100_GPIO53_56, backup); + + return status; } diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl old mode 100755 new mode 100644 index ebdb1eb..3f10012 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -988,73 +988,58 @@ DefinitionBlock ( Scope(\_GPE) { /* Start Scope GPE */ /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L00) { + //DBGO("\\_GPE\\_L00\n") + } /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L01) { + //DBGO("\\_GPE\\_L01\n") + } /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L02) { + //DBGO("\\_GPE\\_L02\n") + } /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ + //DBGO("\\_GPE\\_L00\n") Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L04) { + //DBGO("\\_GPE\\_L04\n") + } /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L05) { + //DBGO("\\_GPE\\_L05\n") + } - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ + /* _L06 General event 6 - Used for GPM6, moved to USB.asl */ + /* _L07 General event 7 - Used for GPM7, moved to USB.asl */ /* Legacy PM event */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ + //DBGO("\\_GPE\\_L08\n") } /* Temp warning (TWarn) event */ Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ + //DBGO("\\_GPE\\_L09\n") Notify (\_TZ.TZ00, 0x80) } /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ + Method(_L0A) { + //DBGO("\\_GPE\\_L0A\n") + } /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ + //DBGO("\\_GPE\\_L0B\n") Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -1065,126 +1050,81 @@ DefinitionBlock ( } /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ + Method(_L0C) { + //DBGO("\\_GPE\\_L0C\n") + } /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ + Method(_L0D) { + //DBGO("\\_GPE\\_L0D\n") + } - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ + /* _L0E GPM9 SCI event - Moved to USB.asl */ /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ + Method(_L0F) { + //DBGO("\\_GPE\\_L0F\n") + } /* ExtEvent0 SCI event */ Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ + //DBGO("\\_GPE\\_L10\n") } /* ExtEvent1 SCI event */ Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ + //DBGO("\\_GPE\\_L11\n") } /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ + Method(_L12) { + //DBGO("\\_GPE\\_L12\n") + } - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ + /* _L13 GPM0 SCI event - Moved to USB.asl */ + /* _L14 GPM1 SCI event - Moved to USB.asl */ + /* _L15 GPM2 SCI event - Moved to USB.asl */ + /* _L16 GPM3 SCI event - Moved to USB.asl */ + /* _L17 GPM8 SCI event - Moved to USB.asl */ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ + //DBGO("\\_GPE\\_L18\n") Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ + /* _L19 GPM4 SCI event - Moved to USB.asl */ + /* _L1A GPM5 SCI event - Moved to USB.asl */ /* Azalia SCI event */ Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ + //DBGO("\\_GPE\\_L1B\n") Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ + Method(_L1C) { + //DBGO("\\_GPE\\_L1C\n") + } /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ + Method(_L1D) { + //DBGO("\\_GPE\\_L1D\n") + } /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ + Method(_L1E) { + //DBGO("\\_GPE\\_L1E\n") + } - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ + /* _L1F SATA SCI event - Moved to sata.asl */ } /* End Scope GPE */ @@ -1569,7 +1509,7 @@ DefinitionBlock ( 0x0CF8, // Range Maximum 0x01, // Alignment 0x08, // Length - ) + ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity @@ -1602,10 +1542,10 @@ DefinitionBlock ( ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity - 0x9000, // Range Minimum - 0xefff, // Range Maximum + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum 0x0000, // Translation Offset - 0x6000, // Length + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space @@ -1613,21 +1553,26 @@ DefinitionBlock ( 0xE0000000, // Address Base 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Granularity - 0xF0000000, // Range Minimum - 0xFFFFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x10000000, // Length - ,, , AddressRangeMemory, TypeStatic) }) Method (_CRS, 0, NotSerialized) { CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - Store (PCBA, BAS1) - Store (PCLN, LEN1) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, BAS1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) + //DBGO(TOM1) Return (CRS) } diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index c2f714d..0c63162 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,21 +28,17 @@ #include #include #include -#include "southbridge/amd/sb700/sb700.h" +#include "Platform.h" /*sb700 platform header*/ -u16 pm_base = SB700_ACPI_IO_BASE; -/* pm_base should be set in sb acpi */ -/* pm_base should be got from bar2 of sb700. Here I compact ACPI - * registers into 32 bytes limit. - * */ +#ifndef ACPI_BLK_BASE + #define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); @@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8); - - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ fadt->pm1_evt_len = 4; @@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; @@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; @@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; @@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; @@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 14e6bca..8c31cbf 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,8 +23,10 @@ #include #include #include -#include #include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -34,22 +36,6 @@ u8 bus_isa; u8 bus_sp5100[2]; u8 bus_sr5650[14]; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* - * HT Chain device num, actually it is unit id base of every ht device in chain, - * assume every chain only have 4 ht device at most - */ -u32 hcdnx[] = { - 0x20202020, -}; u32 bus_type[256]; @@ -106,8 +92,7 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff; - // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sr5650[0] = 0; bus_sp5100[0] = bus_sr5650[0]; /* sp5100 */ @@ -151,4 +136,9 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Late_Post(); +#endif } diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 640a0a6..11e5256 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,9 +27,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index f00b5a0..675c87f 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,36 +25,48 @@ #include #include #include -#include "southbridge/amd/sr5650/cmn.h" +#include #include "chip.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); +void set_pcie_dereset(void *nbconfig); +void set_pcie_reset(void *nbconfig); /** * */ -void set_pcie_reset(void) +void set_pcie_reset(void *nbconfig) { } /** + * Mainboard specific RD890 CIMx callback * Release Resets to PCIe Links - * PCIE_RESET_GPIO1,2,4,5 + * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie */ -void set_pcie_dereset(void) +void set_pcie_dereset(void *nbconfig) { - device_t pcie_core_dev; + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007); + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } } /************************************************* -* enable the dedicated function in h8qgi board. -*************************************************/ + * enable the dedicated function in h8qgi board. + *************************************************/ static void h8qgi_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -69,5 +81,5 @@ int add_mainboard_resources(struct lb_memory *mem) struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") - .enable_dev = h8qgi_enable, + .enable_dev = h8qgi_enable, }; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5c01994..92771bd 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,17 +33,16 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; +extern u8 bus_isa; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; device_t dev; u32 dword; - u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); @@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v) #if CONFIG_MAX_CPUS >= 16 apicid_sp5100 = 0x0; #else - apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif apicid_sr5650 = apicid_sp5100 + 1; - //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); +#ifdef UNUSED_CODE + u8 byte; /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); @@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v) dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); +#endif /* * 00:12.0: PROG SATA : INT F @@ -102,11 +103,11 @@ static void *smp_write_config_table(void *v) /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); - } + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); + } } @@ -155,27 +156,27 @@ static void *smp_write_config_table(void *v) * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); + /* PCI_SLOT 0. */ + PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h new file mode 100644 index 0000000..bbc4ad7 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c index f36b0d8..883cad1 100644 --- a/src/mainboard/supermicro/h8qgi/platform_oem.c +++ b/src/mainboard/supermicro/h8qgi/platform_oem.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,6 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "platform_oem.h" #include "Filecode.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -43,6 +42,7 @@ * **/ /*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h deleted file mode 100644 index ab0d6df..0000000 --- a/src/mainboard/supermicro/h8qgi/platform_oem.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_OEM_H_ -#define _PLATFORM_OEM_H_ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -#endif //_PLATFORM_OEM_H_ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c new file mode 100644 index 0000000..7a947b3 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include +#include + +#ifndef __PRE_RAM__ +#include +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h new file mode 100644 index 0000000..8f45019 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c new file mode 100644 index 0000000..68a39f2 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 08b0eb2..ba8c5e5 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,9 +29,10 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" -#include "southbridge/amd/sr5650/sr5650.h" -#include "southbridge/amd/sb700/sb700.h" +#include +#include #include "superio/nuvoton/wpcm450/wpcm450.h" +#include "superio/winbond/w83627dhg/w83627dhg.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ @@ -39,24 +40,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + post_code(0x30); agesawrapper_amdinitmmio(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - post_code(0x31); - sb7xx_51xx_lpc_port80(); - post_code(0x32); - } + post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); @@ -78,7 +69,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } - post_code(0x38); + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x38); + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + post_code(0x39); + nb_Poweron_Init(); + post_code(0x3A); + sb_Poweron_Init(); + } + post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); @@ -86,12 +89,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } - sr5650_early_setup(); - post_code(0x39); - - sb7xx_51xx_early_setup(); - sr5650_htinit(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + post_code(0x3C); + nb_Ht_Init(); + post_code(0x3D); + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); @@ -103,8 +104,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } - printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); post_code(0x41); val = agesawrapper_amdinitenv(); @@ -114,8 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); post_code(0x50); print_debug("Disabling cache as ram "); diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c new file mode 100644 index 0000000..4cbb8ca --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h new file mode 100644 index 0000000..aac61ec --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_ From gerrit at coreboot.org Tue Feb 7 13:24:27 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:24:27 +0100 Subject: [coreboot] Patch set updated for coreboot: a455ce5 Mainboard: Add AMD dinar mainboard. References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/564 -gerrit commit a455ce529a1a070004693bd7968e3c9e11f5be44 Author: Kerry Sheh Date: Tue Feb 7 20:32:34 2012 +0800 Mainboard: Add AMD dinar mainboard. Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/dinar/BiosCallOuts.c | 563 ++++++++ src/mainboard/amd/dinar/BiosCallOuts.h | 79 + src/mainboard/amd/dinar/Kconfig | 203 +++ src/mainboard/amd/dinar/Makefile.inc | 38 + src/mainboard/amd/dinar/Oem.h | 79 + src/mainboard/amd/dinar/OptionsIds.h | 64 + src/mainboard/amd/dinar/acpi/cpstate.asl | 74 + src/mainboard/amd/dinar/acpi/ide.asl | 244 ++++ src/mainboard/amd/dinar/acpi/routing.asl | 311 ++++ src/mainboard/amd/dinar/acpi/sata.asl | 149 ++ src/mainboard/amd/dinar/acpi_tables.c | 320 ++++ src/mainboard/amd/dinar/agesawrapper.c | 624 ++++++++ src/mainboard/amd/dinar/agesawrapper.h | 136 ++ src/mainboard/amd/dinar/buildOpts.c | 483 +++++++ src/mainboard/amd/dinar/chip.h | 23 + src/mainboard/amd/dinar/cmos.layout | 118 ++ src/mainboard/amd/dinar/devicetree.cb | 104 ++ src/mainboard/amd/dinar/dimmSpd.c | 333 +++++ src/mainboard/amd/dinar/dsdt.asl | 1148 +++++++++++++++ src/mainboard/amd/dinar/fadt.c | 173 +++ src/mainboard/amd/dinar/get_bus_conf.c | 156 ++ src/mainboard/amd/dinar/gpio.c | 482 ++++++ src/mainboard/amd/dinar/gpio.h | 2329 ++++++++++++++++++++++++++++++ src/mainboard/amd/dinar/irq_tables.c | 122 ++ src/mainboard/amd/dinar/mainboard.c | 138 ++ src/mainboard/amd/dinar/mptable.c | 180 +++ src/mainboard/amd/dinar/platform_cfg.h | 54 + src/mainboard/amd/dinar/rd890_cfg.c | 274 ++++ src/mainboard/amd/dinar/rd890_cfg.h | 175 +++ src/mainboard/amd/dinar/reset.c | 66 + src/mainboard/amd/dinar/romstage.c | 162 +++ src/mainboard/amd/dinar/sb700_cfg.c | 142 ++ src/mainboard/amd/dinar/sb700_cfg.h | 237 +++ 34 files changed, 9786 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 62ae584..c6de048 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -7,6 +7,8 @@ config BOARD_AMD_DB800 bool "DB800 (Salsa)" config BOARD_AMD_DBM690T bool "DBM690T (Herring)" +config BOARD_AMD_DINAR + bool "Dinar" config BOARD_AMD_MAHOGANY bool "Mahogany" config BOARD_AMD_MAHOGANY_FAM10 @@ -39,6 +41,7 @@ endchoice source "src/mainboard/amd/db800/Kconfig" source "src/mainboard/amd/dbm690t/Kconfig" +source "src/mainboard/amd/dinar/Kconfig" source "src/mainboard/amd/mahogany/Kconfig" source "src/mainboard/amd/mahogany_fam10/Kconfig" source "src/mainboard/amd/norwich/Kconfig" diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c new file mode 100644 index 0000000..39e1d13 --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -0,0 +1,563 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "SB700.h" + +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG24 +#define SB_GPIO_REG24 24 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + break; + } + } + + if(i >= CallOutCount) + { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = AGESA_SUCCESS; + return Status; +} diff --git a/src/mainboard/amd/dinar/BiosCallOuts.h b/src/mainboard/amd/dinar/BiosCallOuts.h new file mode 100644 index 0000000..22451aa --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig new file mode 100644 index 0000000..d354a49 --- /dev/null +++ b/src/mainboard/amd/dinar/Kconfig @@ -0,0 +1,203 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_DINAR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SCH4037 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select BOARD_ROMSIZE_KB_2048 + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select HAVE_ACPI_TABLES + #TODO select HAVE_ACPI_RESUME + select ENABLE_APIC_EXT_ID + select TINY_BOOTBLOCK + select GFXUMA + +config MAINBOARD_DIR + string + default amd/dinar + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Dinar" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 64 + +config MAX_PHYSICAL_CPUS + int + default 16 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x2e + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + depends on VGA_BIOS + default "1002,515e" + +config AHCI_BIOS + bool + default y + +config AHCI_BIOS_FILE + string "AHCI ROM path and filename" + depends on AHCI_BIOS + default "site-local/ahci/sb700.bin" + +config AHCI_BIOS_ID + string "AHCI device PCI IDs" + depends on AHCI_BIOS + default "1002,4391" + +config XHC_BIOS + bool + default n + +config XHC_BIOS_FILE + string "XHC BIOS path and filename" + depends on XHC_BIOS + default "site-local/xhc/Xhc.rom" + +config XHC_BIOS_ID + string "XHC device PCI IDs" + depends on XHC_BIOS + default "1022,7812" + +config CONSOLE_POST + bool + depends on !NO_POST + default n + +config SATA_CONTROLLER_MODE + hex + default 0x0 + depends on SOUTHBRIDGE_AMD_CIMX_SB700 + +config ONBOARD_LAN + bool + default y + +config ONBOARD_1394 + bool + default y + +config ONBOARD_USB30 + bool + default n + +config ONBOARD_BLUETOOTH + bool + default y + +config ONBOARD_WEBCAM + bool + default y + +config ONBOARD_TRAVIS + bool + default y + +config ONBOARD_LIGHTSENSOR + bool + default n + +config PCI_ROM_RUN + bool + default n + +config UDELAY_IO + bool + default n + +config REDIRECT_CIMX_TRACE_TO_SERIAL + bool "Redirect CIMX Trace to serial console" + default y + +endif # BOARD_AMD_DINAR diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc new file mode 100644 index 0000000..e078df7 --- /dev/null +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -0,0 +1,38 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += sb700_cfg.c +romstage-y += rd890_cfg.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += sb700_cfg.c +ramstage-y += rd890_cfg.c + +ramstage-y += reset.c + +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ + echo `wrong configuration`) diff --git a/src/mainboard/amd/dinar/Oem.h b/src/mainboard/amd/dinar/Oem.h new file mode 100644 index 0000000..67b1314 --- /dev/null +++ b/src/mainboard/amd/dinar/Oem.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define MOVE_PCIEBAR_TO_F0000000 + +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF8000000 +#else +#define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h new file mode 100644 index 0000000..e1d397e --- /dev/null +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl new file mode 100644 index 0000000..64b3f16 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/cpstate.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl new file mode 100644 index 0000000..765a67e --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/dinar/acpi/routing.asl b/src/mainboard/amd/dinar/acpi/routing.asl new file mode 100644 index 0000000..c7a9165 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/routing.asl @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + /* Bus 0, Dev 2 */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + /* Bus 0, Dev 3 */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0010FFFF, 0, 0, 18 }, + Package(){0x0010FFFF, 1, 0, 17 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, 0, 19 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* For Device(PBR2) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* For Device(PBR2) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS3, Package(){ + /* For Device(PBR3) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS3, Package(){ + /* For Device(PBR3) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS4, Package(){ + /* For Device(PBR4) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* For Device(PBR4) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* For Device(PBR5) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* For Device(PBR5) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* For Device(PBR6) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* For Device(PBR6) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* For Device(PBR7) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* For Device(PBR7) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* For Device(PE20) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APE0, Package(){ + /* For Device(PE20) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* For Device(PE21) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APE1, Package(){ + /* For Device(PE21) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* For Device(PE22) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APE2, Package(){ + /* For Device(PE22) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* For Device(PE23) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APE3, Package(){ + /* For Device(PE23) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) +} diff --git a/src/mainboard/amd/dinar/acpi/sata.asl b/src/mainboard/amd/dinar/acpi/sata.asl new file mode 100644 index 0000000..32b9cd9 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c new file mode 100644 index 0000000..ee00e81 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -0,0 +1,320 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + u32 dword; + u32 gsi_base = 0; + u32 apicid_sb700; + u32 apicid_rd890; + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write sb700 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_sb700, + IO_APIC_ADDR, + 0 + ); + + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* sb700 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_rd890, + dword, + gsi_base + ); + } + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, + 0, //BUS + 0, //SOURCE + 2, //gsirq + 0 //flags + ); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + //acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ +#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); +#endif + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); +#endif + + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c new file mode 100644 index 0000000..171deb8 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -0,0 +1,624 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ +/* +BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the +MMIO configuration space range. The size of the MMIO configuration space range varies with this +field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows: +Bits Buses Bits Buses +0h 1 5h 32 +1h 2 6h 64 +2h 4 7h 128 +3h 8 8h 256 +4h 16 Fh-9h Reserved +*/ +UINT8 +GetEndBusNum ( + VOID + ) +{ + UINT64 BusNum; + UINT8 Index; + for (Index = 1; Index <= 8; Index ++ ) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1 ) { + break; + } + } + return Index; +} + +static UINT32 amdinitcpuio(VOID) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 TopMem; + UINT32 NodeCnt; + UINT32 Node; + UINT32 SbLink; + UINT32 Index; + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4] + /* Find out the Link ID of Node0 that connects to the + * Southbridge (system IO hub). e.g. family10 MCM Processor, + * SbLink is Processor0 Link2, internal Node0 Link3 + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + SbLink = (PciData >> 8) & 3; //assume ganged + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ + for (Node = 0; Node < NodeCnt; Node ++) { + /* clear all MMIO Mapped Base/Limit Registers */ + for (Index = 0; Index < 8; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + /* clear all IO Space Base/Limit Registers */ + for (Index = 0; Index < 4; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* Enable MMIO on AMD CPU Address Map Controller */ + + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80); + PciData = (0xA0000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84); + PciData = 0xB0000 >> 8; + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set UMA MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + TopMem = (UINT32)MsrReg; + MsrReg = (MsrReg >> 8) | 3; + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c); + if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { + PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; + } + else { + PciData = (0x100000000ull - 1) >> 8; + } + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set XAPIC MMIO. 24K */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98); + PciData = (0xFEC00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c); + PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0); + PciData = (0xFEE00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8); + PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0); + PciData = 0x13; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4); + PciData = 0x00FFF000; + PciData &= (~0x7F); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | BIT46; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90); + + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Enable memory access */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); + + PciData |= BIT1; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); +#endif + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; +} + +VOID +OemCustomizeInitPost ( + IN AMD_POST_PARAMS *InitPost + ) +{ + InitPost->MemConfig.UmaMode = UMA_AUTO; + InitPost->MemConfig.BottomIo = 0xE0; + InitPost->MemConfig.UmaSize = 0xE0-0xC0; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + /* OEM Should Customize the defaults through this hook */ + OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + + case PICK_PSTATE: + return AcpiPstate; + + case PICK_SRAT: + return AcpiSrat; + + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + printk(BIOS_DEBUG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + /* Enable MMIO on AMD CPU Address Map Controller */ + amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate(VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); + if (Status != AGESA_SUCCESS) { + //agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdLateRunApTask (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h new file mode 100644 index 0000000..6571525 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MMIO_NP_BIT BIT7 + +/* Hudson-2 ACPI PmIO Space Define */ +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +//void brazos_platform_stage(void); +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +void sb_After_Pci_Init (void); +void sb_Mid_Post_Init (void); +void sb_Late_Post (void); +UINT32 agesawrapper_amdreadeventlog (void); +UINT32 agesawrapper_amdinitmmio (void); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c new file mode 100644 index 0000000..fd0464d --- /dev/null +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Sabine/Lynx platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ + */ +#include "AGESA.h" +#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ + + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +/* User makes option selections here + * Comment out the items wanted to be included in the build. + * Uncomment those items you with to REMOVE from the build. + */ +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +//#define BLDOPT_REMOVE_SRAT TRUE +//#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +/* Build configuration values here. +*/ +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_PLAT_NUM_IO_APICS 2 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE +#define BLDCFG_ONLINE_SPARE TRUE +#define BLDCFG_MEMORY_PARITY_ENABLE TRUE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION TRUE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 0 +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 +//#define BLDCFG_USE_ATM_MODE TRUE + +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife +//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 + +//#define IDSOPT_IDS_ENABLED TRUE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE +#define BLDCFG_PSTATE_HPC_MODE FALSE + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap +/* + * Agesa entry points used in this implementation. + */ +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "MarG34PI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} + +// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +#define INSTALL_G34_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_10_SUPPORT TRUE +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT +#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE +#undef INSTALL_FAMILY_10_SUPPORT +#define INSTALL_FAMILY_10_SUPPORT FALSE +#endif +#endif + +#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT +#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE +#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE +#endif +#endif + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0xFF) +#define DFLT_SCRUB_L2_RATE (0x10) +#define DFLT_SCRUB_L3_RATE (0x10) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0x12) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define DFLT_VRM_SLEW_RATE (2500) + +/* Process the options... + * This file include MUST occur + AFTER the user option selection settings + */ +CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF +}; + +#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList + +// And another platform specific one ... +//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = +//{ +// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, +// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, +// HT_LIST_TERMINAL +//}; + +CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList + +// A performance-per-watt optimization. +CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, + HT_LIST_TERMINAL, +}; + +// uncomment the line below to make Perf-per-watt enabled by default. +#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt + + +CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList + +CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = +{ + // Source Socket, Link (4-7 are sublink 1), Target Socket + {0, 0, 1}, + {0, 1, 1}, + {0, 3, 1}, + {0, 4, 1}, + {0, 5, 1}, + {0, 7, 1}, +}; + +#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap + +/* + * PCI Bus numbers for Drachma/Peso board + */ +CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = +{ + // Socket, Link, SecBus, SubBus + 0, 2, 0x00, 0xBF, // RD890 of Dinar + 1, 0, 0xC0, 0xFF, // HTX + HT_LIST_TERMINAL +}; + +#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers + +CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = +{ + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, + 0xFF +}; + +#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList +/* + CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = + { +// {socketA, linkA, socketB, linkB} +{0, 0, 1, 1}, +}; + +#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap +*/ + +/* + * Device Capabilities Override for disabling ID Clumping + */ +CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap + + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterfaceStub.h" +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + + // Dinar has the following routing: + // CS0 M[B,A]_CLK_H/L[0] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[1] + // CS3 M[B,A]_CLK_H/L[3] + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//HY Customer table +UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]); +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h new file mode 100644 index 0000000..42630fa --- /dev/null +++ b/src/mainboard/amd/dinar/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout new file mode 100644 index 0000000..f54529a --- /dev/null +++ b/src/mainboard/amd/dinar/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb new file mode 100644 index 0000000..92fe521 --- /dev/null +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -0,0 +1,104 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +chip northbridge/amd/agesa/family15/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on end # Link 0 + device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) + chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 off end # GPP3a Port0 + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 off end # GPP3a Port4 + device pci a.0 off end # GPP3a Port5 + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x2104" + end # northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on # SM + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/smsc/sch4037 # SIO SMSC SCH4037 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + irq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + end #SIO SMSC307 + end #LPC + device pci 14.4 on end # PCI bridge, 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15/root_complex + diff --git a/src/mainboard/amd/dinar/dimmSpd.c b/src/mainboard/amd/dinar/dimmSpd.c new file mode 100644 index 0000000..f26ec20 --- /dev/null +++ b/src/mainboard/amd/dinar/dimmSpd.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define SMBUS_BASE_ADDR 0xB00 +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define LTC4305_SMBUS_ADDR 0x94 + +typedef struct _DIMM_INFO_SMBUS{ + UINT8 SocketId; + UINT8 MemChannelId; + UINT8 DimmId; + UINT8 SmbusAddress; +} DIMM_INFO_SMBUS; +/* + * SPD address table - porting required + */ +STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = +{ + /* Socket, Channel, Dimm, Smbus */ + {0, 0, 0, 0xAC}, + {0, 0, 1, 0xAE}, + {0, 1, 0, 0xA8}, + {0, 1, 1, 0xAA}, + {0, 2, 0, 0xA4}, + {0, 2, 1, 0xA6}, + {0, 3, 0, 0xA0}, + {0, 3, 1, 0xA2}, + {1, 0, 0, 0xAC}, + {1, 0, 1, 0xAE}, + {1, 1, 0, 0xA8}, + {1, 1, 1, 0xAA}, + {1, 2, 0, 0xA4}, + {1, 2, 1, 0xA6}, + {1, 3, 0, 0xA0}, + {1, 3, 1, 0xA2} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +STATIC +VOID +WritePmReg ( + IN UINT8 Reg, + IN UINT8 Data + ) +{ + __outbyte (0xCD6, Reg); + __outbyte (0xCD7, Data); +} +STATIC +VOID +SetupFch ( + IN UINT16 + IN IoBase + ) +{ + + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + /* set SMBus clock to 400 KHz */ + __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4); +} + +/* + * + * ReadSmbusByteData - read a single SPD byte from any offset + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + + Address |= 1; // set read bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and read bit + __outbyte (Iobase + 2, 0x48); // read byte command + + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + *ByteData = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} +/* + * + * WriteSmbusByteData - Write a single SPD byte onto any offset + * + */ +STATIC +AGESA_STATUS +WriteSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + IN UINT8 ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + Address &= 0xFE; // set write bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and write bit + __outbyte (Iobase + 5, ByteData); // offset in byte data // + __outbyte (Iobase + 2, 0x48); // write byte command + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByte ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *Buffer + ) +{ + UINTN Status; + UINT64 Limit; + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + Buffer [0] = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSpd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + * + */ + +STATIC +AGESA_STATUS +ReadSpd ( + IN UINT16 IoBase, + IN UINT8 SmbusSlaveAddress, + OUT UINT8 *Buffer, + IN UINTN Count + ) +{ + UINTN Index, Status; + + /* read the first byte using offset zero */ + Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0); + if (Status) return Status; + + /* read the remaining bytes using auto-increment for speed */ + for (Index = 1; Index < Count; Index++){ + Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]); + if (Status) return Status; + } + return 0; +} + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ) +{ + AGESA_STATUS Status; + UINT8 SmBusAddress = 0; + UINTN Index; + UINTN MaxSocket = DIMENSION (SpdAddrLookup); + + for (Index = 0; Index < MaxSocket; Index ++){ + if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && + (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && + (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { + SmBusAddress = SpdAddrLookup[Index].SmbusAddress; + break; + } + } + + + if (SmBusAddress == 0) return AGESA_ERROR; + + SetupFch (SMBUS_BASE_ADDR); + + Status = WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + + switch (SpdData->SocketId) { + case 0: + /* Switch onto the First CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + break; + case 1: + /* Switch onto the Second CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x40, 0x03); + break; + default: + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + break; + } + Status = ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 256); + + /*Output SPD Debug Message*/ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + printk(BIOS_DEBUG, " Status = %d\n",Status); + printk(BIOS_DEBUG, "SocketId MemChannelId SpdData->DimmId SmBusAddress Buffer\n"); + printk(BIOS_DEBUG, "%x, %x, %x, %x, %x\n", SpdData->SocketId, SpdData->MemChannelId, SpdData->DimmId, SmBusAddress, SpdData->Buffer); + + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + return Status; +} diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl new file mode 100644 index 0000000..1cbb05e --- /dev/null +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -0,0 +1,1148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "DINAR ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSV, Ones) /* Assume nothing */ + Name(GPIC, 0x1) /* Assume PIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) + Field(PIRQ, ByteAcc, NoLock, Preserve) { + PIDX, 0x00000008, + PDAT, 0x00000008, /* Offset: 1h */ + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + Offset(0x10), + PIRS, 0x00000008, + Offset(0x13), + HDAD, 0x00000008, + , 0x00000008, + GEC, 0x00000008, + Offset(0x30), + USB1, 0x00000008, + USB2, 0x00000008, + USB3, 0x00000008, + USB4, 0x00000008, + USB5, 0x00000008, + USB6, 0x00000008, + USB7, 0x00000008, + Offset(0x40), + IDE, 0x00000008, + SATA, 0x00000008, + Offset(0x50), + GPP0, 0x00000008, + GPP1, 0x00000008, + GPP2, 0x00000008, + GPP3, 0x00000008 + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ + OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) + Field(PMRG, ByteAcc, NoLock, Preserve) { + PMRI, 0x00000008, + PMRD, 0x00000008, + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { + Offset(0x24), + MMSO,32, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x50), + HPAD,32, + Offset(0x60), + P1EB,16, + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xC8), + ,2, + SPRE,1, + TPDE,1, + Offset(0xF0), + ,3, + RSTU,1 + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, NoLock, Preserve) { + ,14, + PEWS,1, + WSTA,1, + ,14, + PEWD,1 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + /* Debug Port registers, 80h. */ + OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) + Field(DBBG, ByteAcc, NoLock, Preserve) { + DBG8, 0x00000008, + } + + Method(_PIC, 1) { + Store(Arg0, GPIC) + If (GPIC) { + Store(0xAA, \_SB.DBG8) + \_SB.DSPI() + } else { + Store(0xAC, \_SB.DBG8) + } + } + + Method(DSPI, 0) { + \_SB.GRUA(0x1F) + \_SB.GRUB(0x1F) + \_SB.GRUC(0x1F) + \_SB.GRUD(0x1F) + Store(0x1F, PIRE) + Store(0x1F, PIRF) + Store(0x1F, PIRG) + Store(0x1F, PIRH) + } + + Method(GRUA, 1) { + Store(Arg0, PIRA) + Store(Arg0, HDAD) + Store(Arg0, GEC) + Store(Arg0, GPP0) + Store(Arg0, GPP0) + } + + Method(GRUB, 1) { + Store(Arg0, PIRB) + Store(Arg0, USB2) + Store(Arg0, USB4) + Store(Arg0, USB6) + Store(Arg0, GPP1) + Store(Arg0, IDE) + } + + Method(GRUC, 1) { + Store(Arg0, PIRC) + Store(Arg0, USB1) + Store(Arg0, USB3) + Store(Arg0, USB5) + Store(Arg0, USB7) + Store(Arg0, GPP2) + } + + Method(GRUD, 1) { + Store(Arg0, PIRD) + Store(Arg0, SATA) + Store(Arg0, GPP3) + } + + Name(IRQB, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 15 + }}) + + Name(IRQP, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 3, 4, 5, 7, 10, 11, 12, 14, 15 + }}) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUA(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUA(Local0) + } + } + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUB(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUB(Local0) + } + } + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUC(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUC(Local0) + } + } + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUD(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUD(Local0) + } + } + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRE) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRE) + } + } + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRF) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRF) + } + } + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRG) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRG) + } + } + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRH) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRH) + } + } + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PEWS, PEWS) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + } /* End Scope GPE */ + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + External (TOM3) + External (TOM4) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + Method(_PRT,0) { + If(GPIC){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Method(_STA,0) { + Return(0x0F) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Method(_PRT,0) { + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* The external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Method(_PRT,0) { + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Method(_PRT,0) { + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Method(_PRT,0) { + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Method(_PRT,0) { + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Method(_PRT,0) { + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Method(_PRT,0) { + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Method(_PRT,0) { + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Method(_PRT,0) { + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Method(_PRT,0) { + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* Describe the Southbridge devices */ + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + } + } /* end AZHD */ + + Device(GEC) { + Name(_ADR, 0x00140006) + } /* end GEC */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + } /* end UOH1 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + } /* end UOH3 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + } /* end UEH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + } /* end UOH2 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + } /* end UOH4 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + } /* end UOH5 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + } /* end XHC0 */ + + Device(XHC1) { + Name(_ADR, 0x00100001) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {8} + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {0} + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IRQNoFlags () {12} + }) + Method (_STA, 0) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + } /* end LIBR */ + + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method(_STA, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(0x0F) + } + Return(0x0) + } + Method(_CRS, 0) { + CreateDWordField(CRS, 0x0A, HPEB) + Store(HPAD, Local0) + And(Local0, 0xFFFFFFC0, HPEB) + Return(CRS) + } + } /* End Device(_SB.PCI0.HPET) */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + Store(\_SB.PCI0.TOM1, MM1B) + Subtract(PCBA, MM1B, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ +} +/* End of ASL file */ diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c new file mode 100644 index 0000000..baf0328 --- /dev/null +++ b/src/mainboard/amd/dinar/fadt.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "Platform.h" /*sb700 platform header*/ + +#ifndef ACPI_BLK_BASE +#define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c new file mode 100644 index 0000000..f66e92c --- /dev/null +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb700[2]; +u8 bus_rd890[14]; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* + * HT Chain device num, actually it is unit id base of every ht device in chain, + * assume every chain only have 4 ht device at most + */ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_sb700; +u32 sbdn_rd890; + +static u32 get_bus_conf_done = 0; + + + + +void get_bus_conf(void) +{ + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); + + sbdn_sb700 = 0; + + for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { + bus_sb700[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) { + bus_rd890[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + + bus_rd890[0] = (pci1234x[0] >> 16) & 0xff; + bus_sb700[0] = bus_rd890[0]; + + /* sb700 */ + dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + + + + if (dev) { + bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb700[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rd890 */ + for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) { + dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0)); + if (dev) { + bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rd890[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rd890[i]] = 1; /* PCI bus. */ + } + } + } + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX +// sb_After_Pci_Init(); +// sb_Late_Post(); +#endif + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); +} diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c new file mode 100644 index 0000000..f18c09d --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.c @@ -0,0 +1,482 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Filecode.h" +#include "Hudson-2.h" +#include "AmdSbLib.h" +#include "gpio.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG07 +#define SB_GPIO_REG07 7 +#endif + +#ifndef SB_GPIO_REG25 +#define SB_GPIO_REG25 25 +#endif + +#ifndef SB_GPIO_REG26 +#define SB_GPIO_REG26 26 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +void gpioEarlyInit (void); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +void +gpioEarlyInit( + void + ) +{ + u8 Flags; + u8 Data8 = 0; + u8 StripInfo = 0; + u8 BoardType = 1; + u8 RegIndex8 = 0; + u8 boardRevC = 0x2; + u16 Data16 = 0; + u32 Index = 0; + u32 AcpiMmioAddr = 0; + u32 GpioMmioAddr = 0; + u32 IoMuxMmioAddr = 0; + u32 MiscMmioAddr = 0; + u32 SmiMmioAddr = 0; + u32 andMask32 = 0; + + // Enable HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + Data8 |= BIT0; + WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + // Get HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); + Data16 = Data8 << 8; + ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); + Data16 |= Data8; + AcpiMmioAddr = (u32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE; + MiscMmioAddr = AcpiMmioAddr + MISC_BASE; + Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); + if ((Data8 & BIT4) == 0) { + BoardType = 0; // external clock board + } + Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); + StripInfo = (Data8 & BIT7) >> 7; + Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); + StripInfo |= (Data8 & BIT7) >> 6; + if (StripInfo < boardRevC) { // for old board. Rev B + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + } + for (Index = 0; Index < MAX_GPIO_NO; Index++) { + if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { + if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { + // Configure multi-funtion + Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); + } + // Configure GPIO + if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { + Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); + Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); + } + if (Index == GPIO_65) { + if ( BoardType == 0 ) { + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + } + } + } + // Configure GEVENT + if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { + SmiMmioAddr = AcpiMmioAddr + SMI_BASE; + + andMask32 = ~(1 << (Index - GEVENT_00)); + + //EventEnable: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); + + //SciTrig: 0-Falling Edge, 1-Rising Edge + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); + + //SciLevl: 0-Edge trigger, 1-Level Trigger + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); + + //SmiSciEn: 0-Not send SMI, 1-Send SMI + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); + + //SciS0En: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); + + //SciMap: 00000b ~ 11111b + RegIndex8=(u8)((Index - GEVENT_00) >> 2); + Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); + + //SmiTrig: 0-Active Low, 1-Active High + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); + + //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + RegIndex8=(u8)((Index - GEVENT_00) >> 4); + Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); + } + } + + // + // config MXM + // GPIO9: Input for MXM_PRESENT2# + // GPIO10: Input for MXM_PRESENT1# + // GPIO28: Input for MXM_PWRGD + // GPIO35: Output for MXM Reset + // GPIO45: Output for MXM Power Enable, active HIGH + // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + // + // set INTE#/GPIO32 as GPO for PCIE_SW + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); + + // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + + // set AD9/GPIO9 as GPI for MXM_PRESENT2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + + // set AD10/GPIO10 as GPI for MXM_PRESENT1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + + // set GNT1#/GPIO44 as GPO for MXM Reset + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + + // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + + // set AD28/GPIO28 as GPI for MXM_PWRGD + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + + // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); + + // + // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). + // + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + + // check if there any GFX card + Flags = 0; + // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); + // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); + ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); + ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + Flags = 1; + } + } + if ( Flags ) + { + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + // WAIT POWER READY: GPIO28 (MXM_PWRGD) + //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + while (!(Data8 && BIT7)) + { + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + } + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset + // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + } + else + { + // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); + } + + // + // APU GPP0: On board LAN + // GPIO25: PCIE_RST#_LAN, LOW active + // GPIO63: LAN_CLKREQ# + // GPIO197: LOM_POWER, HIGH Active + // Clock: GPP_CLK3 + // + // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + + // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 + + // + // APU GPP1: WUSB + // GPIO1: MPCIE_RST2#, LOW active + // GPIO13: WU_DISABLE#, LOW active + // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + // + // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD01/GPIO01 as GPO for MPCIE_RST2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // + // APU GPP2: WWAN + // GPIO0: MPCIE_RST1#, LOW active + // GPIO14: WP_DISABLE#, LOW active + // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + // + // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD00/GPIO00 as GPO for MPCIE_RST1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); + + // + // APU GPP3: 1394 + // GPIO59: Power control, HIGH active + // GPIO27: PCIE_RST#_1394, LOW active + // GPIO41: CLKREQ# + // Clock: GPP_CLK8 + // + // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# + + // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + // To fix glitch issue + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + // + // Enable/Disable OnBoard LAN + // + if (!CONFIG_ONBOARD_LAN) + { // 1 - DISABLED + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); + // } + + + // + // Enable/Disable 1394 + // + if (!CONFIG_ONBOARD_1394) + { // 1 - DISABLED + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); + // + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); + // } + + // + // external USB 3.0 control: + // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO26: PCIE_RST#_USB3.0 + // GPIO46: PCIE_USB30_CLKREQ# + // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + // Clock: GPP_CLK7 + // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { + // disable Onboard NEC USB3.0 controller + if (!CONFIG_ONBOARD_USB30) { + RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + } + // } + + // + // BlueTooth control: BT_ON + // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO07: BT_ON, 0 - OFF, 1 - ON + // + if (!CONFIG_ONBOARD_BLUETOOTH) { + //- if (SystemConfiguration.amdBlueTooth == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); + //- } + } + + // + // WebCam control: + // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + // + if (!CONFIG_ONBOARD_WEBCAM) { + //- if (SystemConfiguration.amdWebCam == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Travis enable: + // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + // + if (!CONFIG_ONBOARD_TRAVIS) { + //- if (SystemConfiguration.amdTravisCtrl == 0) { + RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Disable Light Sensor if needed + // + if (CONFIG_ONBOARD_LIGHTSENSOR) { + //- if (SystemConfiguration.amdLightSensor == 1) { + RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); + //- } + } + +} + + diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h new file mode 100644 index 0000000..c936e50 --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.h @@ -0,0 +1,2329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include +#include + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define Mmio_Address( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) + +#define Mmio32_Ptr( BaseAddr, Register ) \ + ( (volatile u32 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio32_G( BaseAddr, Register ) \ + *Mmio32_Ptr( BaseAddr, Register ) + +#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio32_G( BaseAddr, Register ) = \ +(u32) ( \ + ( Mmio32_G( BaseAddr, Register ) & \ + (u32)(AndData) \ + ) | \ + (u32)(OrData) \ + ) + +#define Mmio8_Ptr( BaseAddr, Register ) \ + ( (volatile u8 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio8_G( BaseAddr, Register ) \ + *Mmio8_Ptr( BaseAddr, Register ) + +#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio8_G( BaseAddr, Register ) = \ +(u8) ( \ + ( Mmio8_G( BaseAddr, Register ) & \ + (u8)(AndData) \ + ) | \ + (u8)(OrData) \ + ) + +#define SMIREG_EVENT_ENABLE 0x04 +#define SMIREG_SCITRIG 0x08 +#define SMIREG_SCILEVEL 0x0C +#define SMIREG_SMISCIEN 0x14 +#define SMIREG_SCIS0EN 0x20 +#define SMIREG_SCIMAP0 0x40 +#define SMIREG_SCIMAP1 0x44 +#define SMIREG_SCIMAP2 0x48 +#define SMIREG_SCIMAP3 0x4C +#define SMIREG_SCIMAP4 0x50 +#define SMIREG_SCIMAP5 0x54 +#define SMIREG_SCIMAP6 0x58 +#define SMIREG_SCIMAP7 0x5C +#define SMIREG_SCIMAP8 0x60 +#define SMIREG_SCIMAP9 0x64 +#define SMIREG_SCIMAP10 0x68 +#define SMIREG_SCIMAP11 0x6C +#define SMIREG_SCIMAP12 0x70 +#define SMIREG_SCIMAP13 0x74 +#define SMIREG_SCIMAP14 0x78 +#define SMIREG_SCIMAP15 0x7C +#define SMIREG_SMITRIG 0x98 +#define SMIREG_SMICONTROL0 0xA0 +#define SMIREG_SMICONTROL1 0xA4 + +#define FUNCTION0 0 +#define FUNCTION1 1 +#define FUNCTION2 2 +#define FUNCTION3 3 +#define NonGpio 0x80 // BIT7 + +// S0-domain General Purpose I/O: GPIO 00~67 +#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT +#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT +#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT +#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED +#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT +#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT +#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED +#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF +#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level +#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 +#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 +#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 +#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default +#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. +#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE +// 1:BATTERY IS FINE(DEFAULT) +// 0:BATTERY IS LOW +#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF +#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default +#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high +#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high +#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high +#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT +#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT +#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 +#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 +// 00 - REVA +// 01 - REVB +// 10 - REVC +// 11 - REVD +#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO +#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. +// 0:USB3.0 I/F in Express CARD +// 1:PCIE I/F in Express CARD detection +#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC +#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. +#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# +#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# +#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF +#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# +#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA +#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ +#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 +#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V +#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 +#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT +#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE +#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE +#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) +// 1:ENABLE; 0:DISABLE +// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 +#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN +#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER +#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER +#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE +#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# +#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 +#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 +#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# +#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 +#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM +#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default +#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +#define GPIO_68_SELECT FUNCTION0+NonGpio +#define GPIO_69_SELECT FUNCTION0+NonGpio +#define GPIO_70_SELECT FUNCTION0+NonGpio +#define GPIO_71_SELECT FUNCTION0+NonGpio +#define GPIO_72_SELECT FUNCTION0+NonGpio +#define GPIO_73_SELECT FUNCTION0+NonGpio +#define GPIO_74_SELECT FUNCTION0+NonGpio +#define GPIO_75_SELECT FUNCTION0+NonGpio +#define GPIO_76_SELECT FUNCTION0+NonGpio +#define GPIO_77_SELECT FUNCTION0+NonGpio +#define GPIO_78_SELECT FUNCTION0+NonGpio +#define GPIO_79_SELECT FUNCTION0+NonGpio +#define GPIO_80_SELECT FUNCTION0+NonGpio +#define GPIO_81_SELECT FUNCTION0+NonGpio +#define GPIO_82_SELECT FUNCTION0+NonGpio +#define GPIO_83_SELECT FUNCTION0+NonGpio +#define GPIO_84_SELECT FUNCTION0+NonGpio +#define GPIO_85_SELECT FUNCTION0+NonGpio +#define GPIO_86_SELECT FUNCTION0+NonGpio +#define GPIO_87_SELECT FUNCTION0+NonGpio +#define GPIO_88_SELECT FUNCTION0+NonGpio +#define GPIO_89_SELECT FUNCTION0+NonGpio +#define GPIO_90_SELECT FUNCTION0+NonGpio +#define GPIO_91_SELECT FUNCTION0+NonGpio +#define GPIO_92_SELECT FUNCTION0+NonGpio +#define GPIO_93_SELECT FUNCTION0+NonGpio +#define GPIO_94_SELECT FUNCTION0+NonGpio +#define GPIO_95_SELECT FUNCTION0+NonGpio +// GEVENT 00~23 are mapped to GPIO 96~119 +#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# +#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# +#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP +#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# +#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# +#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active +#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, +// there is a confliction to IR function when this pin is as a GEVENT. +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, +// special pin difination for SB700 VGA OUTPUT, high active, +// VGA power for Hudson-M2 will be down when it was asserted. +#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active +#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) +#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 +#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 +#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active +// [option for SPI_TPM_CS# in Hudson-M2 A12)] +#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & +// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time +#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, +// plus judge GPIO40 and GPIO19 level,low is assert. +// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) +// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) +#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active +#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, +// low active, when it's low, BIOS will enbale ODD_PWR +#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# +#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK +#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# +#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT +#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +#define GPIO_120_SELECT FUNCTION0+NonGpio +#define GPIO_121_SELECT FUNCTION0+NonGpio +#define GPIO_122_SELECT FUNCTION0+NonGpio +#define GPIO_123_SELECT FUNCTION0+NonGpio +#define GPIO_124_SELECT FUNCTION0+NonGpio +#define GPIO_125_SELECT FUNCTION0+NonGpio +#define GPIO_126_SELECT FUNCTION0+NonGpio +#define GPIO_127_SELECT FUNCTION0+NonGpio +#define GPIO_128_SELECT FUNCTION0+NonGpio +#define GPIO_129_SELECT FUNCTION0+NonGpio +#define GPIO_130_SELECT FUNCTION0+NonGpio +#define GPIO_131_SELECT FUNCTION0+NonGpio +#define GPIO_132_SELECT FUNCTION0+NonGpio +#define GPIO_133_SELECT FUNCTION0+NonGpio +#define GPIO_134_SELECT FUNCTION0+NonGpio +#define GPIO_135_SELECT FUNCTION0+NonGpio +#define GPIO_136_SELECT FUNCTION0+NonGpio +#define GPIO_137_SELECT FUNCTION0+NonGpio +#define GPIO_138_SELECT FUNCTION0+NonGpio +#define GPIO_139_SELECT FUNCTION0+NonGpio +#define GPIO_140_SELECT FUNCTION0+NonGpio +#define GPIO_141_SELECT FUNCTION0+NonGpio +#define GPIO_142_SELECT FUNCTION0+NonGpio +#define GPIO_143_SELECT FUNCTION0+NonGpio +#define GPIO_144_SELECT FUNCTION0+NonGpio +#define GPIO_145_SELECT FUNCTION0+NonGpio +#define GPIO_146_SELECT FUNCTION0+NonGpio +#define GPIO_147_SELECT FUNCTION0+NonGpio +#define GPIO_148_SELECT FUNCTION0+NonGpio +#define GPIO_149_SELECT FUNCTION0+NonGpio +#define GPIO_150_SELECT FUNCTION0+NonGpio +#define GPIO_151_SELECT FUNCTION0+NonGpio +#define GPIO_152_SELECT FUNCTION0+NonGpio +#define GPIO_153_SELECT FUNCTION0+NonGpio +#define GPIO_154_SELECT FUNCTION0+NonGpio +#define GPIO_155_SELECT FUNCTION0+NonGpio +#define GPIO_156_SELECT FUNCTION0+NonGpio +#define GPIO_157_SELECT FUNCTION0+NonGpio +#define GPIO_158_SELECT FUNCTION0+NonGpio +#define GPIO_159_SELECT FUNCTION0+NonGpio +#define GPIO_160_SELECT FUNCTION0+NonGpio + +// S5-domain General Purpose I/O +#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# +#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 +#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 +#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 +#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 +#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. +#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, +#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE +#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 +#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# +#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 +#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 +#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO +#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR +#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 +#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 +#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# +#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE +#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE +// option for HDMI CEC signal OW ACTIVE +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA +#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK +#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active +// RESERVED FOR LCD BACKLIGHT PWM +#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL +#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM +#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF +#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD + +#define TYPE_GPI (1<<5) +#define TYPE_GPO (0<<5) + +#define GPIO_00_TYPE TYPE_GPO +#define GPIO_01_TYPE TYPE_GPO +#define GPIO_02_TYPE TYPE_GPO +#define GPIO_03_TYPE TYPE_GPO +#define GPIO_04_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO +#define GPIO_06_TYPE TYPE_GPO +#define GPIO_07_TYPE TYPE_GPO +#define GPIO_08_TYPE TYPE_GPO +#define GPIO_09_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI +#define GPIO_11_TYPE TYPE_GPO +#define GPIO_12_TYPE TYPE_GPO +#define GPIO_13_TYPE TYPE_GPO +#define GPIO_14_TYPE TYPE_GPO +#define GPIO_15_TYPE TYPE_GPO +#define GPIO_16_TYPE TYPE_GPO +#define GPIO_17_TYPE TYPE_GPO +#define GPIO_18_TYPE TYPE_GPO +#define GPIO_19_TYPE TYPE_GPO +#define GPIO_20_TYPE TYPE_GPO +#define GPIO_21_TYPE TYPE_GPO +#define GPIO_22_TYPE TYPE_GPO +#define GPIO_23_TYPE TYPE_GPO +#define GPIO_24_TYPE TYPE_GPO +#define GPIO_25_TYPE TYPE_GPO +#define GPIO_26_TYPE TYPE_GPO +#define GPIO_27_TYPE TYPE_GPO +#define GPIO_28_TYPE TYPE_GPI +#define GPIO_29_TYPE TYPE_GPO +#define GPIO_30_TYPE TYPE_GPI +#define GPIO_31_TYPE TYPE_GPI +#define GPIO_32_TYPE TYPE_GPO +#define GPIO_33_TYPE TYPE_GPI +#define GPIO_34_TYPE TYPE_GPO +#define GPIO_35_TYPE TYPE_GPO +#define GPIO_36_TYPE TYPE_GPO +#define GPIO_37_TYPE TYPE_GPO +#define GPIO_38_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO +#define GPIO_40_TYPE TYPE_GPO +#define GPIO_41_TYPE TYPE_GPI +#define GPIO_42_TYPE TYPE_GPI +#define GPIO_43_TYPE TYPE_GPO +#define GPIO_44_TYPE TYPE_GPO +#define GPIO_45_TYPE TYPE_GPO +#define GPIO_46_TYPE TYPE_GPI +#define GPIO_47_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO +#define GPIO_50_TYPE TYPE_GPO +#define GPIO_51_TYPE TYPE_GPO +#define GPIO_52_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO +#define GPIO_56_TYPE TYPE_GPI +#define GPIO_57_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO +#define GPIO_59_TYPE TYPE_GPO +#define GPIO_60_TYPE TYPE_GPI +#define GPIO_61_TYPE TYPE_GPI +#define GPIO_62_TYPE TYPE_GPI +#define GPIO_63_TYPE TYPE_GPI +#define GPIO_64_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI +#define GPIO_66_TYPE TYPE_GPO +#define GPIO_67_TYPE TYPE_GPO +#define GPIO_68_TYPE TYPE_GPO +#define GPIO_69_TYPE TYPE_GPO +#define GPIO_70_TYPE TYPE_GPO +#define GPIO_71_TYPE TYPE_GPO +#define GPIO_72_TYPE TYPE_GPO +#define GPIO_73_TYPE TYPE_GPO +#define GPIO_74_TYPE TYPE_GPO +#define GPIO_75_TYPE TYPE_GPO +#define GPIO_76_TYPE TYPE_GPO +#define GPIO_77_TYPE TYPE_GPO +#define GPIO_78_TYPE TYPE_GPO +#define GPIO_79_TYPE TYPE_GPO +#define GPIO_80_TYPE TYPE_GPO +#define GPIO_81_TYPE TYPE_GPO +#define GPIO_82_TYPE TYPE_GPO +#define GPIO_83_TYPE TYPE_GPO +#define GPIO_84_TYPE TYPE_GPO +#define GPIO_85_TYPE TYPE_GPO +#define GPIO_86_TYPE TYPE_GPO +#define GPIO_87_TYPE TYPE_GPO +#define GPIO_88_TYPE TYPE_GPO +#define GPIO_89_TYPE TYPE_GPO +#define GPIO_90_TYPE TYPE_GPO +#define GPIO_91_TYPE TYPE_GPO +#define GPIO_92_TYPE TYPE_GPO +#define GPIO_93_TYPE TYPE_GPO +#define GPIO_94_TYPE TYPE_GPO +#define GPIO_95_TYPE TYPE_GPO + +// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +#define GPIO_96_TYPE TYPE_GPI +#define GPIO_97_TYPE TYPE_GPI +#define GPIO_98_TYPE TYPE_GPI +#define GPIO_99_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI +#define GPIO_101_TYPE TYPE_GPI +#define GPIO_102_TYPE TYPE_GPO +#define GPIO_103_TYPE TYPE_GPO +#define GPIO_104_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI +#define GPIO_106_TYPE TYPE_GPO +#define GPIO_107_TYPE TYPE_GPI +#define GPIO_108_TYPE TYPE_GPI +#define GPIO_109_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI +#define GPIO_111_TYPE TYPE_GPI +#define GPIO_112_TYPE TYPE_GPI +#define GPIO_113_TYPE TYPE_GPI +#define GPIO_114_TYPE TYPE_GPO +#define GPIO_115_TYPE TYPE_GPI +#define GPIO_116_TYPE TYPE_GPI +#define GPIO_117_TYPE TYPE_GPI +#define GPIO_118_TYPE TYPE_GPI +#define GPIO_119_TYPE TYPE_GPI + +#define GPIO_120_TYPE TYPE_GPO +#define GPIO_121_TYPE TYPE_GPO +#define GPIO_122_TYPE TYPE_GPO +#define GPIO_123_TYPE TYPE_GPO +#define GPIO_124_TYPE TYPE_GPO +#define GPIO_125_TYPE TYPE_GPO +#define GPIO_126_TYPE TYPE_GPO +#define GPIO_127_TYPE TYPE_GPO +#define GPIO_128_TYPE TYPE_GPO +#define GPIO_129_TYPE TYPE_GPO +#define GPIO_130_TYPE TYPE_GPO +#define GPIO_131_TYPE TYPE_GPO +#define GPIO_132_TYPE TYPE_GPO +#define GPIO_133_TYPE TYPE_GPO +#define GPIO_134_TYPE TYPE_GPO +#define GPIO_135_TYPE TYPE_GPO +#define GPIO_136_TYPE TYPE_GPO +#define GPIO_137_TYPE TYPE_GPO +#define GPIO_138_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO +#define GPIO_140_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO +#define GPIO_142_TYPE TYPE_GPO +#define GPIO_143_TYPE TYPE_GPO +#define GPIO_144_TYPE TYPE_GPO +#define GPIO_145_TYPE TYPE_GPO +#define GPIO_146_TYPE TYPE_GPO +#define GPIO_147_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO +#define GPIO_150_TYPE TYPE_GPO +#define GPIO_151_TYPE TYPE_GPO +#define GPIO_152_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO +#define GPIO_156_TYPE TYPE_GPO +#define GPIO_157_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO +#define GPIO_159_TYPE TYPE_GPO +#define GPIO_160_TYPE TYPE_GPO +#define GPIO_161_TYPE TYPE_GPO +#define GPIO_162_TYPE TYPE_GPO +#define GPIO_163_TYPE TYPE_GPO +#define GPIO_164_TYPE TYPE_GPI +#define GPIO_165_TYPE TYPE_GPO +#define GPIO_166_TYPE TYPE_GPI +#define GPIO_167_TYPE TYPE_GPI +#define GPIO_168_TYPE TYPE_GPI +#define GPIO_169_TYPE TYPE_GPI +#define GPIO_170_TYPE TYPE_GPO +#define GPIO_171_TYPE TYPE_GPI +#define GPIO_172_TYPE TYPE_GPO +#define GPIO_173_TYPE TYPE_GPI +#define GPIO_174_TYPE TYPE_GPI +#define GPIO_175_TYPE TYPE_GPO +#define GPIO_176_TYPE TYPE_GPO +#define GPIO_177_TYPE TYPE_GPO +#define GPIO_178_TYPE TYPE_GPO +#define GPIO_179_TYPE TYPE_GPO +#define GPIO_180_TYPE TYPE_GPO +#define GPIO_181_TYPE TYPE_GPO +#define GPIO_182_TYPE TYPE_GPO +#define GPIO_183_TYPE TYPE_GPO +#define GPIO_184_TYPE TYPE_GPI +#define GPIO_185_TYPE TYPE_GPO +#define GPIO_186_TYPE TYPE_GPO +#define GPIO_187_TYPE TYPE_GPO +#define GPIO_188_TYPE TYPE_GPO +#define GPIO_189_TYPE TYPE_GPI +#define GPIO_190_TYPE TYPE_GPI +#define GPIO_191_TYPE TYPE_GPO +#define GPIO_192_TYPE TYPE_GPO +#define GPIO_193_TYPE TYPE_GPO +#define GPIO_194_TYPE TYPE_GPO +#define GPIO_195_TYPE TYPE_GPO +#define GPIO_196_TYPE TYPE_GPO +#define GPIO_197_TYPE TYPE_GPO +#define GPIO_198_TYPE TYPE_GPO +#define GPIO_199_TYPE TYPE_GPI +#define GPIO_200_TYPE TYPE_GPO +#define GPIO_201_TYPE TYPE_GPI +#define GPIO_202_TYPE TYPE_GPI +#define GPIO_203_TYPE TYPE_GPI +#define GPIO_204_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI +#define GPIO_206_TYPE TYPE_GPI +#define GPIO_207_TYPE TYPE_GPI +#define GPIO_208_TYPE TYPE_GPI +#define GPIO_209_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO +#define GPIO_211_TYPE TYPE_GPO +#define GPIO_212_TYPE TYPE_GPO +#define GPIO_213_TYPE TYPE_GPO +#define GPIO_214_TYPE TYPE_GPO +#define GPIO_215_TYPE TYPE_GPO +#define GPIO_216_TYPE TYPE_GPO +#define GPIO_217_TYPE TYPE_GPO +#define GPIO_218_TYPE TYPE_GPO +#define GPIO_219_TYPE TYPE_GPO +#define GPIO_220_TYPE TYPE_GPO +#define GPIO_221_TYPE TYPE_GPO +#define GPIO_222_TYPE TYPE_GPO +#define GPIO_223_TYPE TYPE_GPO +#define GPIO_224_TYPE TYPE_GPO +#define GPIO_225_TYPE TYPE_GPO +#define GPIO_226_TYPE TYPE_GPO +#define GPIO_227_TYPE TYPE_GPO +#define GPIO_228_TYPE TYPE_GPO +#define GPIO_229_TYPE TYPE_GPO + +#define GPO_LOW (0<<6) +#define GPO_HI (1<<6) + +#define GPO_00_LEVEL GPO_HI +#define GPO_01_LEVEL GPO_HI +#define GPO_02_LEVEL GPO_HI +#define GPO_03_LEVEL GPO_HI +#define GPO_04_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI +#define GPO_06_LEVEL GPO_HI +#define GPO_07_LEVEL GPO_HI +#define GPO_08_LEVEL GPO_HI +#define GPO_09_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW +#define GPO_11_LEVEL GPO_HI +#define GPO_12_LEVEL GPO_HI +#define GPO_13_LEVEL GPO_HI +#define GPO_14_LEVEL GPO_HI +#define GPO_15_LEVEL GPO_HI +#define GPO_16_LEVEL GPO_HI +#define GPO_17_LEVEL GPO_HI +#define GPO_18_LEVEL GPO_HI +#define GPO_19_LEVEL GPO_LOW +#define GPO_20_LEVEL GPO_LOW +#define GPO_21_LEVEL GPO_LOW +#define GPO_22_LEVEL GPO_HI +#define GPO_23_LEVEL GPO_HI +#define GPO_24_LEVEL GPO_HI +#define GPO_25_LEVEL GPO_HI +#define GPO_26_LEVEL GPO_HI +#define GPO_27_LEVEL GPO_HI +#define GPO_28_LEVEL GPO_LOW +#define GPO_29_LEVEL GPO_HI +#define GPO_30_LEVEL GPO_LOW +#define GPO_31_LEVEL GPO_LOW +#define GPO_32_LEVEL GPO_HI +#define GPO_33_LEVEL GPO_LOW +#define GPO_34_LEVEL GPO_LOW +#define GPO_35_LEVEL GPO_LOW +#define GPO_36_LEVEL GPO_LOW +#define GPO_37_LEVEL GPO_HI +#define GPO_38_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI +#define GPO_40_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW +#define GPO_42_LEVEL GPO_LOW +#define GPO_43_LEVEL GPO_LOW +#define GPO_44_LEVEL GPO_HI +#define GPO_45_LEVEL GPO_HI +#define GPO_46_LEVEL GPO_LOW +#define GPO_47_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW +#define GPO_49_LEVEL GPO_HI +#define GPO_50_LEVEL GPO_HI +#define GPO_51_LEVEL GPO_LOW +#define GPO_52_LEVEL GPO_HI +#define GPO_53_LEVEL GPO_HI +#define GPO_54_LEVEL GPO_LOW +#define GPO_55_LEVEL GPO_LOW +#define GPO_56_LEVEL GPO_LOW +#define GPO_57_LEVEL GPO_HI +#define GPO_58_LEVEL GPO_HI +#define GPO_59_LEVEL GPO_HI +#define GPO_60_LEVEL GPO_LOW +#define GPO_61_LEVEL GPO_LOW +#define GPO_62_LEVEL GPO_LOW +#define GPO_63_LEVEL GPO_LOW +#define GPO_64_LEVEL GPO_LOW +#define GPO_65_LEVEL GPO_LOW +#define GPO_66_LEVEL GPO_LOW +#define GPO_67_LEVEL GPO_LOW +#define GPO_68_LEVEL GPO_LOW +#define GPO_69_LEVEL GPO_LOW +#define GPO_70_LEVEL GPO_LOW +#define GPO_71_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW +#define GPO_73_LEVEL GPO_LOW +#define GPO_74_LEVEL GPO_LOW +#define GPO_75_LEVEL GPO_LOW +#define GPO_76_LEVEL GPO_LOW +#define GPO_77_LEVEL GPO_LOW +#define GPO_78_LEVEL GPO_LOW +#define GPO_79_LEVEL GPO_LOW +#define GPO_80_LEVEL GPO_LOW +#define GPO_81_LEVEL GPO_LOW +#define GPO_82_LEVEL GPO_LOW +#define GPO_83_LEVEL GPO_LOW +#define GPO_84_LEVEL GPO_LOW +#define GPO_85_LEVEL GPO_LOW +#define GPO_86_LEVEL GPO_LOW +#define GPO_87_LEVEL GPO_LOW +#define GPO_88_LEVEL GPO_LOW +#define GPO_89_LEVEL GPO_LOW +#define GPO_90_LEVEL GPO_LOW +#define GPO_91_LEVEL GPO_LOW +#define GPO_92_LEVEL GPO_LOW +#define GPO_93_LEVEL GPO_LOW +#define GPO_94_LEVEL GPO_LOW +#define GPO_95_LEVEL GPO_LOW +#define GPO_96_LEVEL GPO_LOW +#define GPO_97_LEVEL GPO_LOW +#define GPO_98_LEVEL GPO_LOW +#define GPO_99_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW +#define GPO_101_LEVEL GPO_LOW +#define GPO_102_LEVEL GPO_LOW +#define GPO_103_LEVEL GPO_LOW +#define GPO_104_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW +#define GPO_106_LEVEL GPO_LOW +#define GPO_107_LEVEL GPO_LOW +#define GPO_108_LEVEL GPO_HI +#define GPO_109_LEVEL GPO_LOW +#define GPO_110_LEVEL GPO_HI +#define GPO_111_LEVEL GPO_HI +#define GPO_112_LEVEL GPO_HI +#define GPO_113_LEVEL GPO_LOW +#define GPO_114_LEVEL GPO_LOW +#define GPO_115_LEVEL GPO_LOW +#define GPO_116_LEVEL GPO_LOW +#define GPO_117_LEVEL GPO_LOW +#define GPO_118_LEVEL GPO_LOW +#define GPO_119_LEVEL GPO_LOW +#define GPO_120_LEVEL GPO_LOW +#define GPO_121_LEVEL GPO_LOW +#define GPO_122_LEVEL GPO_LOW +#define GPO_123_LEVEL GPO_LOW +#define GPO_124_LEVEL GPO_LOW +#define GPO_125_LEVEL GPO_LOW +#define GPO_126_LEVEL GPO_LOW +#define GPO_127_LEVEL GPO_LOW +#define GPO_128_LEVEL GPO_LOW +#define GPO_129_LEVEL GPO_LOW +#define GPO_130_LEVEL GPO_LOW +#define GPO_131_LEVEL GPO_LOW +#define GPO_132_LEVEL GPO_LOW +#define GPO_133_LEVEL GPO_LOW +#define GPO_134_LEVEL GPO_LOW +#define GPO_135_LEVEL GPO_LOW +#define GPO_136_LEVEL GPO_LOW +#define GPO_137_LEVEL GPO_LOW +#define GPO_138_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW +#define GPO_140_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW +#define GPO_142_LEVEL GPO_LOW +#define GPO_143_LEVEL GPO_LOW +#define GPO_144_LEVEL GPO_LOW +#define GPO_145_LEVEL GPO_LOW +#define GPO_146_LEVEL GPO_LOW +#define GPO_147_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW +#define GPO_149_LEVEL GPO_LOW +#define GPO_150_LEVEL GPO_LOW +#define GPO_151_LEVEL GPO_LOW +#define GPO_152_LEVEL GPO_LOW +#define GPO_153_LEVEL GPO_LOW +#define GPO_154_LEVEL GPO_LOW +#define GPO_155_LEVEL GPO_LOW +#define GPO_156_LEVEL GPO_LOW +#define GPO_157_LEVEL GPO_LOW +#define GPO_158_LEVEL GPO_LOW +#define GPO_159_LEVEL GPO_LOW +#define GPO_160_LEVEL GPO_LOW +#define GPO_161_LEVEL GPO_LOW +#define GPO_162_LEVEL GPO_LOW +#define GPO_163_LEVEL GPO_LOW +#define GPO_164_LEVEL GPO_LOW +#define GPO_165_LEVEL GPO_LOW +#define GPO_166_LEVEL GPO_LOW +#define GPO_167_LEVEL GPO_LOW +#define GPO_168_LEVEL GPO_LOW +#define GPO_169_LEVEL GPO_LOW +#define GPO_170_LEVEL GPO_HI +#define GPO_171_LEVEL GPO_LOW +#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_173_LEVEL GPO_LOW +#define GPO_174_LEVEL GPO_LOW +#define GPO_175_LEVEL GPO_LOW +#define GPO_176_LEVEL GPO_LOW +#define GPO_177_LEVEL GPO_LOW +#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_179_LEVEL GPO_HI +#define GPO_180_LEVEL GPO_HI +#define GPO_181_LEVEL GPO_LOW +#define GPO_182_LEVEL GPO_HI +#define GPO_183_LEVEL GPO_LOW +#define GPO_184_LEVEL GPO_LOW +#define GPO_185_LEVEL GPO_LOW +#define GPO_186_LEVEL GPO_LOW +#define GPO_187_LEVEL GPO_LOW +#define GPO_188_LEVEL GPO_LOW +#define GPO_189_LEVEL GPO_LOW +#define GPO_190_LEVEL GPO_LOW +#define GPO_191_LEVEL GPO_LOW +#define GPO_192_LEVEL GPO_LOW +#define GPO_193_LEVEL GPO_LOW +#define GPO_194_LEVEL GPO_LOW +#define GPO_195_LEVEL GPO_LOW +#define GPO_196_LEVEL GPO_LOW +#define GPO_197_LEVEL GPO_LOW +#define GPO_198_LEVEL GPO_LOW +#define GPO_199_LEVEL GPO_LOW +#define GPO_200_LEVEL GPO_HI +#define GPO_201_LEVEL GPO_LOW +#define GPO_202_LEVEL GPO_LOW +#define GPO_203_LEVEL GPO_LOW +#define GPO_204_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW +#define GPO_206_LEVEL GPO_LOW +#define GPO_207_LEVEL GPO_LOW +#define GPO_208_LEVEL GPO_LOW +#define GPO_209_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW +#define GPO_211_LEVEL GPO_LOW +#define GPO_212_LEVEL GPO_LOW +#define GPO_213_LEVEL GPO_LOW +#define GPO_214_LEVEL GPO_LOW +#define GPO_215_LEVEL GPO_LOW +#define GPO_216_LEVEL GPO_LOW +#define GPO_217_LEVEL GPO_LOW +#define GPO_218_LEVEL GPO_LOW +#define GPO_219_LEVEL GPO_LOW +#define GPO_220_LEVEL GPO_LOW +#define GPO_221_LEVEL GPO_LOW +#define GPO_222_LEVEL GPO_LOW +#define GPO_223_LEVEL GPO_LOW +#define GPO_224_LEVEL GPO_LOW +#define GPO_225_LEVEL GPO_LOW +#define GPO_226_LEVEL GPO_LOW +#define GPO_227_LEVEL GPO_LOW +#define GPO_228_LEVEL GPO_LOW +#define GPO_229_LEVEL GPO_LOW + +#define GPIO_NONSTICKY (0<<2) +#define GPIO_STICKY (1<<2) + +#define GPIO_00_STICKY GPIO_NONSTICKY +#define GPIO_01_STICKY GPIO_NONSTICKY +#define GPIO_02_STICKY GPIO_NONSTICKY +#define GPIO_03_STICKY GPIO_NONSTICKY +#define GPIO_04_STICKY GPIO_NONSTICKY +#define GPIO_05_STICKY GPIO_NONSTICKY +#define GPIO_06_STICKY GPIO_NONSTICKY +#define GPIO_07_STICKY GPIO_NONSTICKY +#define GPIO_08_STICKY GPIO_NONSTICKY +#define GPIO_09_STICKY GPIO_NONSTICKY +#define GPIO_10_STICKY GPIO_NONSTICKY +#define GPIO_11_STICKY GPIO_NONSTICKY +#define GPIO_12_STICKY GPIO_NONSTICKY +#define GPIO_13_STICKY GPIO_NONSTICKY +#define GPIO_14_STICKY GPIO_NONSTICKY +#define GPIO_15_STICKY GPIO_NONSTICKY +#define GPIO_16_STICKY GPIO_NONSTICKY +#define GPIO_17_STICKY GPIO_STICKY +#define GPIO_18_STICKY GPIO_NONSTICKY +#define GPIO_19_STICKY GPIO_NONSTICKY +#define GPIO_20_STICKY GPIO_NONSTICKY +#define GPIO_21_STICKY GPIO_NONSTICKY +#define GPIO_22_STICKY GPIO_NONSTICKY +#define GPIO_23_STICKY GPIO_NONSTICKY +#define GPIO_24_STICKY GPIO_NONSTICKY +#define GPIO_25_STICKY GPIO_NONSTICKY +#define GPIO_26_STICKY GPIO_NONSTICKY +#define GPIO_27_STICKY GPIO_NONSTICKY +#define GPIO_28_STICKY GPIO_NONSTICKY +#define GPIO_29_STICKY GPIO_NONSTICKY +#define GPIO_30_STICKY GPIO_NONSTICKY +#define GPIO_31_STICKY GPIO_NONSTICKY +#define GPIO_32_STICKY GPIO_NONSTICKY +#define GPIO_33_STICKY GPIO_NONSTICKY +#define GPIO_34_STICKY GPIO_NONSTICKY +#define GPIO_35_STICKY GPIO_NONSTICKY +#define GPIO_36_STICKY GPIO_NONSTICKY +#define GPIO_37_STICKY GPIO_NONSTICKY +#define GPIO_38_STICKY GPIO_NONSTICKY +#define GPIO_39_STICKY GPIO_NONSTICKY +#define GPIO_40_STICKY GPIO_NONSTICKY +#define GPIO_41_STICKY GPIO_NONSTICKY +#define GPIO_42_STICKY GPIO_NONSTICKY +#define GPIO_43_STICKY GPIO_NONSTICKY +#define GPIO_44_STICKY GPIO_NONSTICKY +#define GPIO_45_STICKY GPIO_NONSTICKY +#define GPIO_46_STICKY GPIO_NONSTICKY +#define GPIO_47_STICKY GPIO_NONSTICKY +#define GPIO_48_STICKY GPIO_NONSTICKY +#define GPIO_49_STICKY GPIO_NONSTICKY +#define GPIO_50_STICKY GPIO_NONSTICKY +#define GPIO_51_STICKY GPIO_NONSTICKY +#define GPIO_52_STICKY GPIO_NONSTICKY +#define GPIO_53_STICKY GPIO_NONSTICKY +#define GPIO_54_STICKY GPIO_NONSTICKY +#define GPIO_55_STICKY GPIO_NONSTICKY +#define GPIO_56_STICKY GPIO_NONSTICKY +#define GPIO_57_STICKY GPIO_NONSTICKY +#define GPIO_58_STICKY GPIO_NONSTICKY +#define GPIO_59_STICKY GPIO_NONSTICKY +#define GPIO_60_STICKY GPIO_NONSTICKY +#define GPIO_61_STICKY GPIO_NONSTICKY +#define GPIO_62_STICKY GPIO_NONSTICKY +#define GPIO_63_STICKY GPIO_NONSTICKY +#define GPIO_64_STICKY GPIO_NONSTICKY +#define GPIO_65_STICKY GPIO_NONSTICKY +#define GPIO_66_STICKY GPIO_NONSTICKY +#define GPIO_67_STICKY GPIO_NONSTICKY +#define GPIO_68_STICKY GPIO_NONSTICKY +#define GPIO_69_STICKY GPIO_NONSTICKY +#define GPIO_70_STICKY GPIO_NONSTICKY +#define GPIO_71_STICKY GPIO_NONSTICKY +#define GPIO_72_STICKY GPIO_NONSTICKY +#define GPIO_73_STICKY GPIO_NONSTICKY +#define GPIO_74_STICKY GPIO_NONSTICKY +#define GPIO_75_STICKY GPIO_NONSTICKY +#define GPIO_76_STICKY GPIO_NONSTICKY +#define GPIO_77_STICKY GPIO_NONSTICKY +#define GPIO_78_STICKY GPIO_NONSTICKY +#define GPIO_79_STICKY GPIO_NONSTICKY +#define GPIO_80_STICKY GPIO_NONSTICKY +#define GPIO_81_STICKY GPIO_NONSTICKY +#define GPIO_82_STICKY GPIO_NONSTICKY +#define GPIO_83_STICKY GPIO_NONSTICKY +#define GPIO_84_STICKY GPIO_NONSTICKY +#define GPIO_85_STICKY GPIO_NONSTICKY +#define GPIO_86_STICKY GPIO_NONSTICKY +#define GPIO_87_STICKY GPIO_NONSTICKY +#define GPIO_88_STICKY GPIO_NONSTICKY +#define GPIO_89_STICKY GPIO_NONSTICKY +#define GPIO_90_STICKY GPIO_NONSTICKY +#define GPIO_91_STICKY GPIO_NONSTICKY +#define GPIO_92_STICKY GPIO_NONSTICKY +#define GPIO_93_STICKY GPIO_NONSTICKY +#define GPIO_94_STICKY GPIO_NONSTICKY +#define GPIO_95_STICKY GPIO_NONSTICKY +#define GPIO_96_STICKY GPIO_NONSTICKY +#define GPIO_97_STICKY GPIO_NONSTICKY +#define GPIO_98_STICKY GPIO_NONSTICKY +#define GPIO_99_STICKY GPIO_NONSTICKY +#define GPIO_100_STICKY GPIO_NONSTICKY +#define GPIO_101_STICKY GPIO_NONSTICKY +#define GPIO_102_STICKY GPIO_STICKY +#define GPIO_103_STICKY GPIO_STICKY +#define GPIO_104_STICKY GPIO_NONSTICKY +#define GPIO_105_STICKY GPIO_NONSTICKY +#define GPIO_106_STICKY GPIO_NONSTICKY +#define GPIO_107_STICKY GPIO_NONSTICKY +#define GPIO_108_STICKY GPIO_STICKY +#define GPIO_109_STICKY GPIO_NONSTICKY +#define GPIO_110_STICKY GPIO_NONSTICKY +#define GPIO_111_STICKY GPIO_NONSTICKY +#define GPIO_112_STICKY GPIO_NONSTICKY +#define GPIO_113_STICKY GPIO_NONSTICKY +#define GPIO_114_STICKY GPIO_NONSTICKY +#define GPIO_115_STICKY GPIO_NONSTICKY +#define GPIO_116_STICKY GPIO_NONSTICKY +#define GPIO_117_STICKY GPIO_NONSTICKY +#define GPIO_118_STICKY GPIO_NONSTICKY +#define GPIO_119_STICKY GPIO_NONSTICKY +#define GPIO_120_STICKY GPIO_NONSTICKY +#define GPIO_121_STICKY GPIO_NONSTICKY +#define GPIO_122_STICKY GPIO_NONSTICKY +#define GPIO_123_STICKY GPIO_NONSTICKY +#define GPIO_124_STICKY GPIO_NONSTICKY +#define GPIO_125_STICKY GPIO_NONSTICKY +#define GPIO_126_STICKY GPIO_NONSTICKY +#define GPIO_127_STICKY GPIO_NONSTICKY +#define GPIO_128_STICKY GPIO_NONSTICKY +#define GPIO_129_STICKY GPIO_NONSTICKY +#define GPIO_130_STICKY GPIO_NONSTICKY +#define GPIO_131_STICKY GPIO_NONSTICKY +#define GPIO_132_STICKY GPIO_NONSTICKY +#define GPIO_133_STICKY GPIO_NONSTICKY +#define GPIO_134_STICKY GPIO_NONSTICKY +#define GPIO_135_STICKY GPIO_NONSTICKY +#define GPIO_136_STICKY GPIO_NONSTICKY +#define GPIO_137_STICKY GPIO_NONSTICKY +#define GPIO_138_STICKY GPIO_NONSTICKY +#define GPIO_139_STICKY GPIO_NONSTICKY +#define GPIO_140_STICKY GPIO_NONSTICKY +#define GPIO_141_STICKY GPIO_NONSTICKY +#define GPIO_142_STICKY GPIO_NONSTICKY +#define GPIO_143_STICKY GPIO_NONSTICKY +#define GPIO_144_STICKY GPIO_NONSTICKY +#define GPIO_145_STICKY GPIO_NONSTICKY +#define GPIO_146_STICKY GPIO_NONSTICKY +#define GPIO_147_STICKY GPIO_NONSTICKY +#define GPIO_148_STICKY GPIO_NONSTICKY +#define GPIO_149_STICKY GPIO_NONSTICKY +#define GPIO_150_STICKY GPIO_NONSTICKY +#define GPIO_151_STICKY GPIO_NONSTICKY +#define GPIO_152_STICKY GPIO_NONSTICKY +#define GPIO_153_STICKY GPIO_NONSTICKY +#define GPIO_154_STICKY GPIO_NONSTICKY +#define GPIO_155_STICKY GPIO_NONSTICKY +#define GPIO_156_STICKY GPIO_NONSTICKY +#define GPIO_157_STICKY GPIO_NONSTICKY +#define GPIO_158_STICKY GPIO_NONSTICKY +#define GPIO_159_STICKY GPIO_NONSTICKY +#define GPIO_160_STICKY GPIO_NONSTICKY +#define GPIO_161_STICKY GPIO_NONSTICKY +#define GPIO_162_STICKY GPIO_NONSTICKY +#define GPIO_163_STICKY GPIO_NONSTICKY +#define GPIO_164_STICKY GPIO_NONSTICKY +#define GPIO_165_STICKY GPIO_NONSTICKY +#define GPIO_166_STICKY GPIO_NONSTICKY +#define GPIO_167_STICKY GPIO_NONSTICKY +#define GPIO_168_STICKY GPIO_NONSTICKY +#define GPIO_169_STICKY GPIO_NONSTICKY +#define GPIO_170_STICKY GPIO_STICKY +#define GPIO_171_STICKY GPIO_NONSTICKY +#define GPIO_172_STICKY GPIO_STICKY +#define GPIO_173_STICKY GPIO_NONSTICKY +#define GPIO_174_STICKY GPIO_NONSTICKY +#define GPIO_175_STICKY GPIO_NONSTICKY +#define GPIO_176_STICKY GPIO_NONSTICKY +#define GPIO_177_STICKY GPIO_NONSTICKY +#define GPIO_178_STICKY GPIO_NONSTICKY +#define GPIO_179_STICKY GPIO_NONSTICKY +#define GPIO_180_STICKY GPIO_NONSTICKY +#define GPIO_181_STICKY GPIO_NONSTICKY +#define GPIO_182_STICKY GPIO_NONSTICKY +#define GPIO_183_STICKY GPIO_NONSTICKY +#define GPIO_184_STICKY GPIO_NONSTICKY +#define GPIO_185_STICKY GPIO_NONSTICKY +#define GPIO_186_STICKY GPIO_NONSTICKY +#define GPIO_187_STICKY GPIO_NONSTICKY +#define GPIO_188_STICKY GPIO_NONSTICKY +#define GPIO_189_STICKY GPIO_NONSTICKY +#define GPIO_190_STICKY GPIO_NONSTICKY +#define GPIO_191_STICKY GPIO_NONSTICKY +#define GPIO_192_STICKY GPIO_NONSTICKY +#define GPIO_193_STICKY GPIO_NONSTICKY +#define GPIO_194_STICKY GPIO_NONSTICKY +#define GPIO_195_STICKY GPIO_NONSTICKY +#define GPIO_196_STICKY GPIO_NONSTICKY +#define GPIO_197_STICKY GPIO_NONSTICKY +#define GPIO_198_STICKY GPIO_NONSTICKY +#define GPIO_199_STICKY GPIO_NONSTICKY +#define GPIO_200_STICKY GPIO_NONSTICKY +#define GPIO_201_STICKY GPIO_NONSTICKY +#define GPIO_202_STICKY GPIO_NONSTICKY +#define GPIO_203_STICKY GPIO_NONSTICKY +#define GPIO_204_STICKY GPIO_NONSTICKY +#define GPIO_205_STICKY GPIO_NONSTICKY +#define GPIO_206_STICKY GPIO_NONSTICKY +#define GPIO_207_STICKY GPIO_NONSTICKY +#define GPIO_208_STICKY GPIO_NONSTICKY +#define GPIO_209_STICKY GPIO_NONSTICKY +#define GPIO_210_STICKY GPIO_NONSTICKY +#define GPIO_211_STICKY GPIO_NONSTICKY +#define GPIO_212_STICKY GPIO_NONSTICKY +#define GPIO_213_STICKY GPIO_NONSTICKY +#define GPIO_214_STICKY GPIO_NONSTICKY +#define GPIO_215_STICKY GPIO_NONSTICKY +#define GPIO_216_STICKY GPIO_NONSTICKY +#define GPIO_217_STICKY GPIO_NONSTICKY +#define GPIO_218_STICKY GPIO_NONSTICKY +#define GPIO_219_STICKY GPIO_NONSTICKY +#define GPIO_220_STICKY GPIO_NONSTICKY +#define GPIO_221_STICKY GPIO_NONSTICKY +#define GPIO_222_STICKY GPIO_NONSTICKY +#define GPIO_223_STICKY GPIO_NONSTICKY +#define GPIO_224_STICKY GPIO_NONSTICKY +#define GPIO_225_STICKY GPIO_NONSTICKY +#define GPIO_226_STICKY GPIO_NONSTICKY +#define GPIO_227_STICKY GPIO_NONSTICKY +#define GPIO_228_STICKY GPIO_NONSTICKY +#define GPIO_229_STICKY GPIO_NONSTICKY + +#define PULLUP_ENABLE (0<<3) +#define PULLUP_DISABLE (1<<3) + +#define GPIO_00_PULLUP PULLUP_DISABLE +#define GPIO_01_PULLUP PULLUP_DISABLE +#define GPIO_02_PULLUP PULLUP_DISABLE +#define GPIO_03_PULLUP PULLUP_DISABLE +#define GPIO_04_PULLUP PULLUP_DISABLE +#define GPIO_05_PULLUP PULLUP_DISABLE +#define GPIO_06_PULLUP PULLUP_DISABLE +#define GPIO_07_PULLUP PULLUP_DISABLE +#define GPIO_08_PULLUP PULLUP_DISABLE +#define GPIO_09_PULLUP PULLUP_DISABLE +#define GPIO_10_PULLUP PULLUP_DISABLE +#define GPIO_11_PULLUP PULLUP_DISABLE +#define GPIO_12_PULLUP PULLUP_DISABLE +#define GPIO_13_PULLUP PULLUP_DISABLE +#define GPIO_14_PULLUP PULLUP_DISABLE +#define GPIO_15_PULLUP PULLUP_DISABLE +#define GPIO_16_PULLUP PULLUP_DISABLE +#define GPIO_17_PULLUP PULLUP_DISABLE +#define GPIO_18_PULLUP PULLUP_DISABLE +#define GPIO_19_PULLUP PULLUP_DISABLE +#define GPIO_20_PULLUP PULLUP_DISABLE +#define GPIO_21_PULLUP PULLUP_DISABLE +#define GPIO_22_PULLUP PULLUP_DISABLE +#define GPIO_23_PULLUP PULLUP_DISABLE +#define GPIO_24_PULLUP PULLUP_DISABLE +#define GPIO_25_PULLUP PULLUP_DISABLE +#define GPIO_26_PULLUP PULLUP_DISABLE +#define GPIO_27_PULLUP PULLUP_DISABLE +#define GPIO_28_PULLUP PULLUP_DISABLE +#define GPIO_29_PULLUP PULLUP_DISABLE +#define GPIO_30_PULLUP PULLUP_DISABLE +#define GPIO_31_PULLUP PULLUP_DISABLE +#define GPIO_32_PULLUP PULLUP_DISABLE +#define GPIO_33_PULLUP PULLUP_DISABLE +#define GPIO_34_PULLUP PULLUP_DISABLE +#define GPIO_35_PULLUP PULLUP_DISABLE +#define GPIO_36_PULLUP PULLUP_DISABLE +#define GPIO_37_PULLUP PULLUP_DISABLE +#define GPIO_38_PULLUP PULLUP_DISABLE +#define GPIO_39_PULLUP PULLUP_DISABLE +#define GPIO_40_PULLUP PULLUP_DISABLE +#define GPIO_41_PULLUP PULLUP_DISABLE +#define GPIO_42_PULLUP PULLUP_DISABLE +#define GPIO_43_PULLUP PULLUP_DISABLE +#define GPIO_44_PULLUP PULLUP_DISABLE +#define GPIO_45_PULLUP PULLUP_DISABLE +#define GPIO_46_PULLUP PULLUP_DISABLE +#define GPIO_47_PULLUP PULLUP_DISABLE +#define GPIO_48_PULLUP PULLUP_DISABLE +#define GPIO_49_PULLUP PULLUP_DISABLE +#define GPIO_50_PULLUP PULLUP_DISABLE +#define GPIO_51_PULLUP PULLUP_DISABLE +#define GPIO_52_PULLUP PULLUP_DISABLE +#define GPIO_53_PULLUP PULLUP_DISABLE +#define GPIO_54_PULLUP PULLUP_DISABLE +#define GPIO_55_PULLUP PULLUP_DISABLE +#define GPIO_56_PULLUP PULLUP_DISABLE +#define GPIO_57_PULLUP PULLUP_DISABLE +#define GPIO_58_PULLUP PULLUP_DISABLE +#define GPIO_59_PULLUP PULLUP_DISABLE +#define GPIO_60_PULLUP PULLUP_DISABLE +#define GPIO_61_PULLUP PULLUP_DISABLE +#define GPIO_62_PULLUP PULLUP_DISABLE +#define GPIO_63_PULLUP PULLUP_DISABLE +#define GPIO_64_PULLUP PULLUP_DISABLE +#define GPIO_65_PULLUP PULLUP_DISABLE +#define GPIO_66_PULLUP PULLUP_DISABLE +#define GPIO_67_PULLUP PULLUP_DISABLE +#define GPIO_68_PULLUP PULLUP_DISABLE +#define GPIO_69_PULLUP PULLUP_DISABLE +#define GPIO_70_PULLUP PULLUP_DISABLE +#define GPIO_71_PULLUP PULLUP_DISABLE +#define GPIO_72_PULLUP PULLUP_DISABLE +#define GPIO_73_PULLUP PULLUP_DISABLE +#define GPIO_74_PULLUP PULLUP_DISABLE +#define GPIO_75_PULLUP PULLUP_DISABLE +#define GPIO_76_PULLUP PULLUP_DISABLE +#define GPIO_77_PULLUP PULLUP_DISABLE +#define GPIO_78_PULLUP PULLUP_DISABLE +#define GPIO_79_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_81_PULLUP PULLUP_DISABLE +#define GPIO_82_PULLUP PULLUP_DISABLE +#define GPIO_83_PULLUP PULLUP_DISABLE +#define GPIO_84_PULLUP PULLUP_DISABLE +#define GPIO_85_PULLUP PULLUP_DISABLE +#define GPIO_86_PULLUP PULLUP_DISABLE +#define GPIO_87_PULLUP PULLUP_DISABLE +#define GPIO_88_PULLUP PULLUP_DISABLE +#define GPIO_89_PULLUP PULLUP_DISABLE +#define GPIO_90_PULLUP PULLUP_DISABLE +#define GPIO_91_PULLUP PULLUP_DISABLE +#define GPIO_92_PULLUP PULLUP_DISABLE +#define GPIO_93_PULLUP PULLUP_DISABLE +#define GPIO_94_PULLUP PULLUP_DISABLE +#define GPIO_95_PULLUP PULLUP_DISABLE +#define GPIO_96_PULLUP PULLUP_DISABLE +#define GPIO_97_PULLUP PULLUP_DISABLE +#define GPIO_98_PULLUP PULLUP_DISABLE +#define GPIO_99_PULLUP PULLUP_DISABLE +#define GPIO_100_PULLUP PULLUP_DISABLE +#define GPIO_101_PULLUP PULLUP_DISABLE +#define GPIO_102_PULLUP PULLUP_DISABLE +#define GPIO_103_PULLUP PULLUP_DISABLE +#define GPIO_104_PULLUP PULLUP_DISABLE +#define GPIO_105_PULLUP PULLUP_DISABLE +#define GPIO_106_PULLUP PULLUP_DISABLE +#define GPIO_107_PULLUP PULLUP_DISABLE +#define GPIO_108_PULLUP PULLUP_DISABLE +#define GPIO_109_PULLUP PULLUP_DISABLE +#define GPIO_110_PULLUP PULLUP_DISABLE +#define GPIO_111_PULLUP PULLUP_DISABLE +#define GPIO_112_PULLUP PULLUP_DISABLE +#define GPIO_113_PULLUP PULLUP_DISABLE +#define GPIO_114_PULLUP PULLUP_DISABLE +#define GPIO_115_PULLUP PULLUP_DISABLE +#define GPIO_116_PULLUP PULLUP_DISABLE +#define GPIO_117_PULLUP PULLUP_DISABLE +#define GPIO_118_PULLUP PULLUP_ENABLE +#define GPIO_119_PULLUP PULLUP_DISABLE +#define GPIO_120_PULLUP PULLUP_DISABLE +#define GPIO_121_PULLUP PULLUP_DISABLE +#define GPIO_122_PULLUP PULLUP_DISABLE +#define GPIO_123_PULLUP PULLUP_DISABLE +#define GPIO_124_PULLUP PULLUP_DISABLE +#define GPIO_125_PULLUP PULLUP_DISABLE +#define GPIO_126_PULLUP PULLUP_DISABLE +#define GPIO_127_PULLUP PULLUP_DISABLE +#define GPIO_128_PULLUP PULLUP_DISABLE +#define GPIO_129_PULLUP PULLUP_DISABLE +#define GPIO_130_PULLUP PULLUP_DISABLE +#define GPIO_131_PULLUP PULLUP_DISABLE +#define GPIO_132_PULLUP PULLUP_DISABLE +#define GPIO_133_PULLUP PULLUP_DISABLE +#define GPIO_134_PULLUP PULLUP_DISABLE +#define GPIO_135_PULLUP PULLUP_DISABLE +#define GPIO_136_PULLUP PULLUP_DISABLE +#define GPIO_137_PULLUP PULLUP_DISABLE +#define GPIO_138_PULLUP PULLUP_DISABLE +#define GPIO_139_PULLUP PULLUP_DISABLE +#define GPIO_140_PULLUP PULLUP_DISABLE +#define GPIO_141_PULLUP PULLUP_DISABLE +#define GPIO_142_PULLUP PULLUP_DISABLE +#define GPIO_143_PULLUP PULLUP_DISABLE +#define GPIO_144_PULLUP PULLUP_DISABLE +#define GPIO_145_PULLUP PULLUP_DISABLE +#define GPIO_146_PULLUP PULLUP_DISABLE +#define GPIO_147_PULLUP PULLUP_DISABLE +#define GPIO_148_PULLUP PULLUP_DISABLE +#define GPIO_149_PULLUP PULLUP_DISABLE +#define GPIO_150_PULLUP PULLUP_DISABLE +#define GPIO_151_PULLUP PULLUP_DISABLE +#define GPIO_152_PULLUP PULLUP_DISABLE +#define GPIO_153_PULLUP PULLUP_DISABLE +#define GPIO_154_PULLUP PULLUP_DISABLE +#define GPIO_155_PULLUP PULLUP_DISABLE +#define GPIO_156_PULLUP PULLUP_DISABLE +#define GPIO_157_PULLUP PULLUP_DISABLE +#define GPIO_158_PULLUP PULLUP_DISABLE +#define GPIO_159_PULLUP PULLUP_DISABLE +#define GPIO_160_PULLUP PULLUP_DISABLE +#define GPIO_161_PULLUP PULLUP_DISABLE +#define GPIO_162_PULLUP PULLUP_DISABLE +#define GPIO_163_PULLUP PULLUP_DISABLE +#define GPIO_164_PULLUP PULLUP_DISABLE +#define GPIO_165_PULLUP PULLUP_DISABLE +#define GPIO_166_PULLUP PULLUP_DISABLE +#define GPIO_167_PULLUP PULLUP_DISABLE +#define GPIO_168_PULLUP PULLUP_DISABLE +#define GPIO_169_PULLUP PULLUP_DISABLE +#define GPIO_170_PULLUP PULLUP_DISABLE +#define GPIO_171_PULLUP PULLUP_DISABLE +#define GPIO_172_PULLUP PULLUP_DISABLE +#define GPIO_173_PULLUP PULLUP_DISABLE +#define GPIO_174_PULLUP PULLUP_DISABLE +#define GPIO_175_PULLUP PULLUP_DISABLE +#define GPIO_176_PULLUP PULLUP_DISABLE +#define GPIO_177_PULLUP PULLUP_DISABLE +#define GPIO_178_PULLUP PULLUP_DISABLE +#define GPIO_179_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_181_PULLUP PULLUP_DISABLE +#define GPIO_182_PULLUP PULLUP_DISABLE +#define GPIO_183_PULLUP PULLUP_DISABLE +#define GPIO_184_PULLUP PULLUP_DISABLE +#define GPIO_185_PULLUP PULLUP_DISABLE +#define GPIO_186_PULLUP PULLUP_DISABLE +#define GPIO_187_PULLUP PULLUP_DISABLE +#define GPIO_188_PULLUP PULLUP_DISABLE +#define GPIO_189_PULLUP PULLUP_DISABLE +#define GPIO_190_PULLUP PULLUP_DISABLE +#define GPIO_191_PULLUP PULLUP_DISABLE +#define GPIO_192_PULLUP PULLUP_DISABLE +#define GPIO_193_PULLUP PULLUP_DISABLE +#define GPIO_194_PULLUP PULLUP_DISABLE +#define GPIO_195_PULLUP PULLUP_DISABLE +#define GPIO_196_PULLUP PULLUP_DISABLE +#define GPIO_197_PULLUP PULLUP_DISABLE +#define GPIO_198_PULLUP PULLUP_DISABLE +#define GPIO_199_PULLUP PULLUP_DISABLE +#define GPIO_200_PULLUP PULLUP_DISABLE +#define GPIO_201_PULLUP PULLUP_DISABLE +#define GPIO_202_PULLUP PULLUP_DISABLE +#define GPIO_203_PULLUP PULLUP_DISABLE +#define GPIO_204_PULLUP PULLUP_DISABLE +#define GPIO_205_PULLUP PULLUP_DISABLE +#define GPIO_206_PULLUP PULLUP_DISABLE +#define GPIO_207_PULLUP PULLUP_DISABLE +#define GPIO_208_PULLUP PULLUP_DISABLE +#define GPIO_209_PULLUP PULLUP_DISABLE +#define GPIO_210_PULLUP PULLUP_DISABLE +#define GPIO_211_PULLUP PULLUP_DISABLE +#define GPIO_212_PULLUP PULLUP_DISABLE +#define GPIO_213_PULLUP PULLUP_DISABLE +#define GPIO_214_PULLUP PULLUP_DISABLE +#define GPIO_215_PULLUP PULLUP_DISABLE +#define GPIO_216_PULLUP PULLUP_DISABLE +#define GPIO_217_PULLUP PULLUP_DISABLE +#define GPIO_218_PULLUP PULLUP_DISABLE +#define GPIO_219_PULLUP PULLUP_DISABLE +#define GPIO_220_PULLUP PULLUP_DISABLE +#define GPIO_221_PULLUP PULLUP_DISABLE +#define GPIO_222_PULLUP PULLUP_DISABLE +#define GPIO_223_PULLUP PULLUP_DISABLE +#define GPIO_224_PULLUP PULLUP_DISABLE +#define GPIO_225_PULLUP PULLUP_DISABLE +#define GPIO_226_PULLUP PULLUP_DISABLE +#define GPIO_227_PULLUP PULLUP_DISABLE +#define GPIO_228_PULLUP PULLUP_DISABLE +#define GPIO_229_PULLUP PULLUP_DISABLE + +#define PULLDOWN_ENABLE (1<<4) +#define PULLDOWN_DISABLE (0<<4) + +#define GPIO_00_PULLDOWN PULLDOWN_DISABLE +#define GPIO_01_PULLDOWN PULLDOWN_DISABLE +#define GPIO_02_PULLDOWN PULLDOWN_DISABLE +#define GPIO_03_PULLDOWN PULLDOWN_DISABLE +#define GPIO_04_PULLDOWN PULLDOWN_DISABLE +#define GPIO_05_PULLDOWN PULLDOWN_DISABLE +#define GPIO_06_PULLDOWN PULLDOWN_DISABLE +#define GPIO_07_PULLDOWN PULLDOWN_DISABLE +#define GPIO_08_PULLDOWN PULLDOWN_DISABLE +#define GPIO_09_PULLDOWN PULLDOWN_DISABLE +#define GPIO_10_PULLDOWN PULLDOWN_DISABLE +#define GPIO_11_PULLDOWN PULLDOWN_DISABLE +#define GPIO_12_PULLDOWN PULLDOWN_DISABLE +#define GPIO_13_PULLDOWN PULLDOWN_DISABLE +#define GPIO_14_PULLDOWN PULLDOWN_DISABLE +#define GPIO_15_PULLDOWN PULLDOWN_DISABLE +#define GPIO_16_PULLDOWN PULLDOWN_DISABLE +#define GPIO_17_PULLDOWN PULLDOWN_DISABLE +#define GPIO_18_PULLDOWN PULLDOWN_DISABLE +#define GPIO_19_PULLDOWN PULLDOWN_DISABLE +#define GPIO_20_PULLDOWN PULLDOWN_DISABLE +#define GPIO_21_PULLDOWN PULLDOWN_DISABLE +#define GPIO_22_PULLDOWN PULLDOWN_DISABLE +#define GPIO_23_PULLDOWN PULLDOWN_DISABLE +#define GPIO_24_PULLDOWN PULLDOWN_DISABLE +#define GPIO_25_PULLDOWN PULLDOWN_DISABLE +#define GPIO_26_PULLDOWN PULLDOWN_DISABLE +#define GPIO_27_PULLDOWN PULLDOWN_DISABLE +#define GPIO_28_PULLDOWN PULLDOWN_DISABLE +#define GPIO_29_PULLDOWN PULLDOWN_DISABLE +#define GPIO_30_PULLDOWN PULLDOWN_DISABLE +#define GPIO_31_PULLDOWN PULLDOWN_DISABLE +#define GPIO_32_PULLDOWN PULLDOWN_DISABLE +#define GPIO_33_PULLDOWN PULLDOWN_DISABLE +#define GPIO_34_PULLDOWN PULLDOWN_DISABLE +#define GPIO_35_PULLDOWN PULLDOWN_DISABLE +#define GPIO_36_PULLDOWN PULLDOWN_DISABLE +#define GPIO_37_PULLDOWN PULLDOWN_DISABLE +#define GPIO_38_PULLDOWN PULLDOWN_DISABLE +#define GPIO_39_PULLDOWN PULLDOWN_DISABLE +#define GPIO_40_PULLDOWN PULLDOWN_DISABLE +#define GPIO_41_PULLDOWN PULLDOWN_DISABLE +#define GPIO_42_PULLDOWN PULLDOWN_DISABLE +#define GPIO_43_PULLDOWN PULLDOWN_DISABLE +#define GPIO_44_PULLDOWN PULLDOWN_DISABLE +#define GPIO_45_PULLDOWN PULLDOWN_DISABLE +#define GPIO_46_PULLDOWN PULLDOWN_DISABLE +#define GPIO_47_PULLDOWN PULLDOWN_DISABLE +#define GPIO_48_PULLDOWN PULLDOWN_DISABLE +#define GPIO_49_PULLDOWN PULLDOWN_DISABLE +#define GPIO_50_PULLDOWN PULLDOWN_DISABLE +#define GPIO_51_PULLDOWN PULLDOWN_DISABLE +#define GPIO_52_PULLDOWN PULLDOWN_DISABLE +#define GPIO_53_PULLDOWN PULLDOWN_DISABLE +#define GPIO_54_PULLDOWN PULLDOWN_DISABLE +#define GPIO_55_PULLDOWN PULLDOWN_DISABLE +#define GPIO_56_PULLDOWN PULLDOWN_DISABLE +#define GPIO_57_PULLDOWN PULLDOWN_DISABLE +#define GPIO_58_PULLDOWN PULLDOWN_DISABLE +#define GPIO_59_PULLDOWN PULLDOWN_DISABLE +#define GPIO_60_PULLDOWN PULLDOWN_DISABLE +#define GPIO_61_PULLDOWN PULLDOWN_DISABLE +#define GPIO_62_PULLDOWN PULLDOWN_DISABLE +#define GPIO_63_PULLDOWN PULLDOWN_DISABLE +#define GPIO_64_PULLDOWN PULLDOWN_DISABLE +#define GPIO_65_PULLDOWN PULLDOWN_DISABLE +#define GPIO_66_PULLDOWN PULLDOWN_DISABLE +#define GPIO_67_PULLDOWN PULLDOWN_DISABLE +#define GPIO_68_PULLDOWN PULLDOWN_DISABLE +#define GPIO_69_PULLDOWN PULLDOWN_DISABLE +#define GPIO_70_PULLDOWN PULLDOWN_DISABLE +#define GPIO_71_PULLDOWN PULLDOWN_DISABLE +#define GPIO_72_PULLDOWN PULLDOWN_DISABLE +#define GPIO_73_PULLDOWN PULLDOWN_DISABLE +#define GPIO_74_PULLDOWN PULLDOWN_DISABLE +#define GPIO_75_PULLDOWN PULLDOWN_DISABLE +#define GPIO_76_PULLDOWN PULLDOWN_DISABLE +#define GPIO_77_PULLDOWN PULLDOWN_DISABLE +#define GPIO_78_PULLDOWN PULLDOWN_DISABLE +#define GPIO_79_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_81_PULLDOWN PULLDOWN_DISABLE +#define GPIO_82_PULLDOWN PULLDOWN_DISABLE +#define GPIO_83_PULLDOWN PULLDOWN_DISABLE +#define GPIO_84_PULLDOWN PULLDOWN_DISABLE +#define GPIO_85_PULLDOWN PULLDOWN_DISABLE +#define GPIO_86_PULLDOWN PULLDOWN_DISABLE +#define GPIO_87_PULLDOWN PULLDOWN_DISABLE +#define GPIO_88_PULLDOWN PULLDOWN_DISABLE +#define GPIO_89_PULLDOWN PULLDOWN_DISABLE +#define GPIO_90_PULLDOWN PULLDOWN_DISABLE +#define GPIO_91_PULLDOWN PULLDOWN_DISABLE +#define GPIO_92_PULLDOWN PULLDOWN_DISABLE +#define GPIO_93_PULLDOWN PULLDOWN_DISABLE +#define GPIO_94_PULLDOWN PULLDOWN_DISABLE +#define GPIO_95_PULLDOWN PULLDOWN_DISABLE +#define GPIO_96_PULLDOWN PULLDOWN_DISABLE +#define GPIO_97_PULLDOWN PULLDOWN_DISABLE +#define GPIO_98_PULLDOWN PULLDOWN_DISABLE +#define GPIO_99_PULLDOWN PULLDOWN_DISABLE +#define GPIO_100_PULLDOWN PULLDOWN_DISABLE +#define GPIO_101_PULLDOWN PULLDOWN_DISABLE +#define GPIO_102_PULLDOWN PULLDOWN_DISABLE +#define GPIO_103_PULLDOWN PULLDOWN_DISABLE +#define GPIO_104_PULLDOWN PULLDOWN_DISABLE +#define GPIO_105_PULLDOWN PULLDOWN_DISABLE +#define GPIO_106_PULLDOWN PULLDOWN_DISABLE +#define GPIO_107_PULLDOWN PULLDOWN_DISABLE +#define GPIO_108_PULLDOWN PULLDOWN_DISABLE +#define GPIO_109_PULLDOWN PULLDOWN_DISABLE +#define GPIO_110_PULLDOWN PULLDOWN_DISABLE +#define GPIO_111_PULLDOWN PULLDOWN_DISABLE +#define GPIO_112_PULLDOWN PULLDOWN_DISABLE +#define GPIO_113_PULLDOWN PULLDOWN_DISABLE +#define GPIO_114_PULLDOWN PULLDOWN_DISABLE +#define GPIO_115_PULLDOWN PULLDOWN_DISABLE +#define GPIO_116_PULLDOWN PULLDOWN_DISABLE +#define GPIO_117_PULLDOWN PULLDOWN_DISABLE +#define GPIO_118_PULLDOWN PULLDOWN_DISABLE +#define GPIO_119_PULLDOWN PULLDOWN_DISABLE +#define GPIO_120_PULLDOWN PULLDOWN_DISABLE +#define GPIO_121_PULLDOWN PULLDOWN_DISABLE +#define GPIO_122_PULLDOWN PULLDOWN_DISABLE +#define GPIO_123_PULLDOWN PULLDOWN_DISABLE +#define GPIO_124_PULLDOWN PULLDOWN_DISABLE +#define GPIO_125_PULLDOWN PULLDOWN_DISABLE +#define GPIO_126_PULLDOWN PULLDOWN_DISABLE +#define GPIO_127_PULLDOWN PULLDOWN_DISABLE +#define GPIO_128_PULLDOWN PULLDOWN_DISABLE +#define GPIO_129_PULLDOWN PULLDOWN_DISABLE +#define GPIO_130_PULLDOWN PULLDOWN_DISABLE +#define GPIO_131_PULLDOWN PULLDOWN_DISABLE +#define GPIO_132_PULLDOWN PULLDOWN_DISABLE +#define GPIO_133_PULLDOWN PULLDOWN_DISABLE +#define GPIO_134_PULLDOWN PULLDOWN_DISABLE +#define GPIO_135_PULLDOWN PULLDOWN_DISABLE +#define GPIO_136_PULLDOWN PULLDOWN_DISABLE +#define GPIO_137_PULLDOWN PULLDOWN_DISABLE +#define GPIO_138_PULLDOWN PULLDOWN_DISABLE +#define GPIO_139_PULLDOWN PULLDOWN_DISABLE +#define GPIO_140_PULLDOWN PULLDOWN_DISABLE +#define GPIO_141_PULLDOWN PULLDOWN_DISABLE +#define GPIO_142_PULLDOWN PULLDOWN_DISABLE +#define GPIO_143_PULLDOWN PULLDOWN_DISABLE +#define GPIO_144_PULLDOWN PULLDOWN_DISABLE +#define GPIO_145_PULLDOWN PULLDOWN_DISABLE +#define GPIO_146_PULLDOWN PULLDOWN_DISABLE +#define GPIO_147_PULLDOWN PULLDOWN_DISABLE +#define GPIO_148_PULLDOWN PULLDOWN_DISABLE +#define GPIO_149_PULLDOWN PULLDOWN_DISABLE +#define GPIO_150_PULLDOWN PULLDOWN_DISABLE +#define GPIO_151_PULLDOWN PULLDOWN_DISABLE +#define GPIO_152_PULLDOWN PULLDOWN_DISABLE +#define GPIO_153_PULLDOWN PULLDOWN_DISABLE +#define GPIO_154_PULLDOWN PULLDOWN_DISABLE +#define GPIO_155_PULLDOWN PULLDOWN_DISABLE +#define GPIO_156_PULLDOWN PULLDOWN_DISABLE +#define GPIO_157_PULLDOWN PULLDOWN_DISABLE +#define GPIO_158_PULLDOWN PULLDOWN_DISABLE +#define GPIO_159_PULLDOWN PULLDOWN_DISABLE +#define GPIO_160_PULLDOWN PULLDOWN_DISABLE +#define GPIO_161_PULLDOWN PULLDOWN_DISABLE +#define GPIO_162_PULLDOWN PULLDOWN_ENABLE +#define GPIO_163_PULLDOWN PULLDOWN_ENABLE +#define GPIO_164_PULLDOWN PULLDOWN_ENABLE +#define GPIO_165_PULLDOWN PULLDOWN_DISABLE +#define GPIO_166_PULLDOWN PULLDOWN_DISABLE +#define GPIO_167_PULLDOWN PULLDOWN_ENABLE +#define GPIO_168_PULLDOWN PULLDOWN_DISABLE +#define GPIO_169_PULLDOWN PULLDOWN_DISABLE +#define GPIO_170_PULLDOWN PULLDOWN_DISABLE +#define GPIO_171_PULLDOWN PULLDOWN_DISABLE +#define GPIO_172_PULLDOWN PULLDOWN_DISABLE +#define GPIO_173_PULLDOWN PULLDOWN_DISABLE +#define GPIO_174_PULLDOWN PULLDOWN_DISABLE +#define GPIO_175_PULLDOWN PULLDOWN_DISABLE +#define GPIO_176_PULLDOWN PULLDOWN_DISABLE +#define GPIO_177_PULLDOWN PULLDOWN_DISABLE +#define GPIO_178_PULLDOWN PULLDOWN_DISABLE +#define GPIO_179_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_181_PULLDOWN PULLDOWN_DISABLE +#define GPIO_182_PULLDOWN PULLDOWN_DISABLE +#define GPIO_183_PULLDOWN PULLDOWN_DISABLE +#define GPIO_184_PULLDOWN PULLDOWN_DISABLE +#define GPIO_185_PULLDOWN PULLDOWN_ENABLE +#define GPIO_186_PULLDOWN PULLDOWN_ENABLE +#define GPIO_187_PULLDOWN PULLDOWN_DISABLE +#define GPIO_188_PULLDOWN PULLDOWN_DISABLE +#define GPIO_189_PULLDOWN PULLDOWN_DISABLE +#define GPIO_190_PULLDOWN PULLDOWN_DISABLE +#define GPIO_191_PULLDOWN PULLDOWN_DISABLE +#define GPIO_192_PULLDOWN PULLDOWN_DISABLE +#define GPIO_193_PULLDOWN PULLDOWN_DISABLE +#define GPIO_194_PULLDOWN PULLDOWN_DISABLE +#define GPIO_195_PULLDOWN PULLDOWN_DISABLE +#define GPIO_196_PULLDOWN PULLDOWN_DISABLE +#define GPIO_197_PULLDOWN PULLDOWN_DISABLE +#define GPIO_198_PULLDOWN PULLDOWN_DISABLE +#define GPIO_199_PULLDOWN PULLDOWN_DISABLE +#define GPIO_200_PULLDOWN PULLDOWN_DISABLE +#define GPIO_201_PULLDOWN PULLDOWN_DISABLE +#define GPIO_202_PULLDOWN PULLDOWN_DISABLE +#define GPIO_203_PULLDOWN PULLDOWN_DISABLE +#define GPIO_204_PULLDOWN PULLDOWN_DISABLE +#define GPIO_205_PULLDOWN PULLDOWN_DISABLE +#define GPIO_206_PULLDOWN PULLDOWN_DISABLE +#define GPIO_207_PULLDOWN PULLDOWN_DISABLE +#define GPIO_208_PULLDOWN PULLDOWN_DISABLE +#define GPIO_209_PULLDOWN PULLDOWN_DISABLE +#define GPIO_210_PULLDOWN PULLDOWN_DISABLE +#define GPIO_211_PULLDOWN PULLDOWN_DISABLE +#define GPIO_212_PULLDOWN PULLDOWN_DISABLE +#define GPIO_213_PULLDOWN PULLDOWN_DISABLE +#define GPIO_214_PULLDOWN PULLDOWN_DISABLE +#define GPIO_215_PULLDOWN PULLDOWN_DISABLE +#define GPIO_216_PULLDOWN PULLDOWN_DISABLE +#define GPIO_217_PULLDOWN PULLDOWN_DISABLE +#define GPIO_218_PULLDOWN PULLDOWN_DISABLE +#define GPIO_219_PULLDOWN PULLDOWN_DISABLE +#define GPIO_220_PULLDOWN PULLDOWN_DISABLE +#define GPIO_221_PULLDOWN PULLDOWN_DISABLE +#define GPIO_222_PULLDOWN PULLDOWN_DISABLE +#define GPIO_223_PULLDOWN PULLDOWN_DISABLE +#define GPIO_224_PULLDOWN PULLDOWN_DISABLE +#define GPIO_225_PULLDOWN PULLDOWN_DISABLE +#define GPIO_226_PULLDOWN PULLDOWN_DISABLE +#define GPIO_227_PULLDOWN PULLDOWN_DISABLE +#define GPIO_228_PULLDOWN PULLDOWN_DISABLE +#define GPIO_229_PULLDOWN PULLDOWN_DISABLE + +#define EVENT_DISABLE 0 +#define EVENT_ENABLE 1 + +#define GEVENT_00_EVENTENABLE EVENT_DISABLE +#define GEVENT_01_EVENTENABLE EVENT_DISABLE +#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# +#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# +#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# +#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_06_EVENTENABLE EVENT_DISABLE +#define GEVENT_07_EVENTENABLE EVENT_DISABLE +#define GEVENT_08_EVENTENABLE EVENT_DISABLE +#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_10_EVENTENABLE EVENT_DISABLE +#define GEVENT_11_EVENTENABLE EVENT_DISABLE +#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_13_EVENTENABLE EVENT_DISABLE +#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# +#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# +#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA +#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_18_EVENTENABLE EVENT_DISABLE +#define GEVENT_19_EVENTENABLE EVENT_DISABLE +#define GEVENT_20_EVENTENABLE EVENT_DISABLE +#define GEVENT_21_EVENTENABLE EVENT_DISABLE +#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# +#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# + +#define SCITRIG_LOW 0 +#define SCITRIG_HI 1 + +#define GEVENT_00_SCITRIG SCITRIG_LOW +#define GEVENT_01_SCITRIG SCITRIG_LOW +#define GEVENT_02_SCITRIG SCITRIG_LOW +#define GEVENT_03_SCITRIG SCITRIG_LOW +#define GEVENT_04_SCITRIG SCITRIG_LOW +#define GEVENT_05_SCITRIG SCITRIG_LOW +#define GEVENT_06_SCITRIG SCITRIG_LOW +#define GEVENT_07_SCITRIG SCITRIG_LOW +#define GEVENT_08_SCITRIG SCITRIG_LOW +#define GEVENT_09_SCITRIG SCITRIG_LOW +#define GEVENT_10_SCITRIG SCITRIG_LOW +#define GEVENT_11_SCITRIG SCITRIG_LOW +#define GEVENT_12_SCITRIG SCITRIG_LOW +#define GEVENT_13_SCITRIG SCITRIG_LOW +#define GEVENT_14_SCITRIG SCITRIG_LOW +#define GEVENT_15_SCITRIG SCITRIG_LOW +#define GEVENT_16_SCITRIG SCITRIG_LOW +#define GEVENT_17_SCITRIG SCITRIG_HI +#define GEVENT_18_SCITRIG SCITRIG_LOW +#define GEVENT_19_SCITRIG SCITRIG_LOW +#define GEVENT_20_SCITRIG SCITRIG_LOW +#define GEVENT_21_SCITRIG SCITRIG_LOW +#define GEVENT_22_SCITRIG SCITRIG_LOW +#define GEVENT_23_SCITRIG SCITRIG_LOW + +#define SCILEVEL_EDGE 0 +#define SCILEVEL_LEVEL 1 + +#define GEVENT_00_SCILEVEL SCILEVEL_EDGE +#define GEVENT_01_SCILEVEL SCILEVEL_EDGE +#define GEVENT_02_SCILEVEL SCILEVEL_EDGE +#define GEVENT_03_SCILEVEL SCILEVEL_EDGE +#define GEVENT_04_SCILEVEL SCILEVEL_EDGE +#define GEVENT_05_SCILEVEL SCILEVEL_EDGE +#define GEVENT_06_SCILEVEL SCILEVEL_EDGE +#define GEVENT_07_SCILEVEL SCILEVEL_EDGE +#define GEVENT_08_SCILEVEL SCILEVEL_EDGE +#define GEVENT_09_SCILEVEL SCILEVEL_EDGE +#define GEVENT_10_SCILEVEL SCILEVEL_EDGE +#define GEVENT_11_SCILEVEL SCILEVEL_EDGE +#define GEVENT_12_SCILEVEL SCILEVEL_EDGE +#define GEVENT_13_SCILEVEL SCILEVEL_EDGE +#define GEVENT_14_SCILEVEL SCILEVEL_EDGE +#define GEVENT_15_SCILEVEL SCILEVEL_EDGE +#define GEVENT_16_SCILEVEL SCILEVEL_EDGE +#define GEVENT_17_SCILEVEL SCILEVEL_EDGE +#define GEVENT_18_SCILEVEL SCILEVEL_EDGE +#define GEVENT_19_SCILEVEL SCILEVEL_EDGE +#define GEVENT_20_SCILEVEL SCILEVEL_EDGE +#define GEVENT_21_SCILEVEL SCILEVEL_EDGE +#define GEVENT_22_SCILEVEL SCILEVEL_EDGE +#define GEVENT_23_SCILEVEL SCILEVEL_EDGE + +#define SMISCI_DISABLE 0 +#define SMISCI_ENABLE 1 + +#define GEVENT_00_SMISCIEN SMISCI_DISABLE +#define GEVENT_01_SMISCIEN SMISCI_DISABLE +#define GEVENT_02_SMISCIEN SMISCI_DISABLE +#define GEVENT_03_SMISCIEN SMISCI_DISABLE +#define GEVENT_04_SMISCIEN SMISCI_DISABLE +#define GEVENT_05_SMISCIEN SMISCI_DISABLE +#define GEVENT_06_SMISCIEN SMISCI_DISABLE +#define GEVENT_07_SMISCIEN SMISCI_DISABLE +#define GEVENT_08_SMISCIEN SMISCI_DISABLE +#define GEVENT_09_SMISCIEN SMISCI_DISABLE +#define GEVENT_10_SMISCIEN SMISCI_DISABLE +#define GEVENT_11_SMISCIEN SMISCI_DISABLE +#define GEVENT_12_SMISCIEN SMISCI_DISABLE +#define GEVENT_13_SMISCIEN SMISCI_DISABLE +#define GEVENT_14_SMISCIEN SMISCI_DISABLE +#define GEVENT_15_SMISCIEN SMISCI_DISABLE +#define GEVENT_16_SMISCIEN SMISCI_DISABLE +#define GEVENT_17_SMISCIEN SMISCI_DISABLE +#define GEVENT_18_SMISCIEN SMISCI_DISABLE +#define GEVENT_19_SMISCIEN SMISCI_DISABLE +#define GEVENT_20_SMISCIEN SMISCI_DISABLE +#define GEVENT_21_SMISCIEN SMISCI_DISABLE +#define GEVENT_22_SMISCIEN SMISCI_DISABLE +#define GEVENT_23_SMISCIEN SMISCI_DISABLE + +#define SCIS0_DISABLE 0 +#define SCIS0_ENABLE 1 + +#define GEVENT_00_SCIS0EN SCIS0_DISABLE +#define GEVENT_01_SCIS0EN SCIS0_DISABLE +#define GEVENT_02_SCIS0EN SCIS0_DISABLE +#define GEVENT_03_SCIS0EN SCIS0_DISABLE +#define GEVENT_04_SCIS0EN SCIS0_DISABLE +#define GEVENT_05_SCIS0EN SCIS0_DISABLE +#define GEVENT_06_SCIS0EN SCIS0_DISABLE +#define GEVENT_07_SCIS0EN SCIS0_DISABLE +#define GEVENT_08_SCIS0EN SCIS0_DISABLE +#define GEVENT_09_SCIS0EN SCIS0_DISABLE +#define GEVENT_10_SCIS0EN SCIS0_DISABLE +#define GEVENT_11_SCIS0EN SCIS0_DISABLE +#define GEVENT_12_SCIS0EN SCIS0_DISABLE +#define GEVENT_13_SCIS0EN SCIS0_DISABLE +#define GEVENT_14_SCIS0EN SCIS0_DISABLE +#define GEVENT_15_SCIS0EN SCIS0_DISABLE +#define GEVENT_16_SCIS0EN SCIS0_DISABLE +#define GEVENT_17_SCIS0EN SCIS0_DISABLE +#define GEVENT_18_SCIS0EN SCIS0_DISABLE +#define GEVENT_19_SCIS0EN SCIS0_DISABLE +#define GEVENT_20_SCIS0EN SCIS0_DISABLE +#define GEVENT_21_SCIS0EN SCIS0_DISABLE +#define GEVENT_22_SCIS0EN SCIS0_DISABLE +#define GEVENT_23_SCIS0EN SCIS0_DISABLE + +#define GEVENT_SCIMASK 0x1F +#define GEVENT_00_SCIMAP 0 +#define GEVENT_01_SCIMAP 1 +#define GEVENT_02_SCIMAP 2 +#define GEVENT_03_SCIMAP 3 +#define GEVENT_04_SCIMAP 4 +#define GEVENT_05_SCIMAP 5 +#define GEVENT_06_SCIMAP 6 +#define GEVENT_07_SCIMAP 7 +#define GEVENT_08_SCIMAP 8 +#define GEVENT_09_SCIMAP 9 +#define GEVENT_10_SCIMAP 10 +#define GEVENT_11_SCIMAP 11 +#define GEVENT_12_SCIMAP 12 +#define GEVENT_13_SCIMAP 13 +#define GEVENT_14_SCIMAP 14 +#define GEVENT_15_SCIMAP 15 +#define GEVENT_16_SCIMAP 16 +#define GEVENT_17_SCIMAP 17 +#define GEVENT_18_SCIMAP 18 +#define GEVENT_19_SCIMAP 19 +#define GEVENT_20_SCIMAP 20 +#define GEVENT_21_SCIMAP 21 +#define GEVENT_22_SCIMAP 22 +#define GEVENT_23_SCIMAP 23 + +#define SMITRIG_LOW 0 +#define SMITRIG_HI 1 + +#define GEVENT_00_SMITRIG SMITRIG_HI +#define GEVENT_01_SMITRIG SMITRIG_HI +#define GEVENT_02_SMITRIG SMITRIG_HI +#define GEVENT_03_SMITRIG SMITRIG_HI +#define GEVENT_04_SMITRIG SMITRIG_HI +#define GEVENT_05_SMITRIG SMITRIG_HI +#define GEVENT_06_SMITRIG SMITRIG_HI +#define GEVENT_07_SMITRIG SMITRIG_HI +#define GEVENT_08_SMITRIG SMITRIG_HI +#define GEVENT_09_SMITRIG SMITRIG_HI +#define GEVENT_10_SMITRIG SMITRIG_HI +#define GEVENT_11_SMITRIG SMITRIG_HI +#define GEVENT_12_SMITRIG SMITRIG_HI +#define GEVENT_13_SMITRIG SMITRIG_HI +#define GEVENT_14_SMITRIG SMITRIG_HI +#define GEVENT_15_SMITRIG SMITRIG_HI +#define GEVENT_16_SMITRIG SMITRIG_HI +#define GEVENT_17_SMITRIG SMITRIG_HI +#define GEVENT_18_SMITRIG SMITRIG_HI +#define GEVENT_19_SMITRIG SMITRIG_HI +#define GEVENT_20_SMITRIG SMITRIG_HI +#define GEVENT_21_SMITRIG SMITRIG_HI +#define GEVENT_22_SMITRIG SMITRIG_HI +#define GEVENT_23_SMITRIG SMITRIG_HI + +#define SMICONTROL_MASK 3 +#define SMICONTROL_DISABLE 0 +#define SMICONTROL_SMI 1 +#define SMICONTROL_NMI 2 +#define SMICONTROL_IRQ13 3 + +#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE + +#define GPIO_RSVD_ZONE0_S GPIO_81 +#define GPIO_RSVD_ZONE0_E GPIO_95 +#define GPIO_RSVD_ZONE1_S GPIO_120 +#define GPIO_RSVD_ZONE1_E GPIO_127 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef enum _GPIO_COUNT +{ + GPIO_00=0, + GPIO_01, + GPIO_02, + GPIO_03, + GPIO_04, + GPIO_05, + GPIO_06, + GPIO_07, + GPIO_08, + GPIO_09, + GPIO_10, + GPIO_11, + GPIO_12, + GPIO_13, + GPIO_14, + GPIO_15, + GPIO_16, + GPIO_17, + GPIO_18, + GPIO_19, + GPIO_20, + GPIO_21, + GPIO_22, + GPIO_23, + GPIO_24, + GPIO_25, + GPIO_26, + GPIO_27, + GPIO_28, + GPIO_29, + GPIO_30, + GPIO_31, + GPIO_32, + GPIO_33, + GPIO_34, + GPIO_35, + GPIO_36, + GPIO_37, + GPIO_38, + GPIO_39, + GPIO_40, + GPIO_41, + GPIO_42, + GPIO_43, + GPIO_44, + GPIO_45, + GPIO_46, + GPIO_47, + GPIO_48, + GPIO_49, + GPIO_50, + GPIO_51, + GPIO_52, + GPIO_53, + GPIO_54, + GPIO_55, + GPIO_56, + GPIO_57, + GPIO_58, + GPIO_59, + GPIO_60, + GPIO_61, + GPIO_62, + GPIO_63, + GPIO_64, + GPIO_65, + GPIO_66, + GPIO_67, + GPIO_68, + GPIO_69, + GPIO_70, + GPIO_71, + GPIO_72, + GPIO_73, + GPIO_74, + GPIO_75, + GPIO_76, + GPIO_77, + GPIO_78, + GPIO_79, + GPIO_80, + GPIO_81, + GPIO_82, + GPIO_83, + GPIO_84, + GPIO_85, + GPIO_86, + GPIO_87, + GPIO_88, + GPIO_89, + GPIO_90, + GPIO_91, + GPIO_92, + GPIO_93, + GPIO_94, + GPIO_95, + GPIO_96, + GPIO_97, + GPIO_98, + GPIO_99, + GPIO_100, + GPIO_101, + GPIO_102, + GPIO_103, + GPIO_104, + GPIO_105, + GPIO_106, + GPIO_107, + GPIO_108, + GPIO_109, + GPIO_110, + GPIO_111, + GPIO_112, + GPIO_113, + GPIO_114, + GPIO_115, + GPIO_116, + GPIO_117, + GPIO_118, + GPIO_119, + GPIO_120, + GPIO_121, + GPIO_122, + GPIO_123, + GPIO_124, + GPIO_125, + GPIO_126, + GPIO_127, + GPIO_128, + GPIO_129, + GPIO_130, + GPIO_131, + GPIO_132, + GPIO_133, + GPIO_134, + GPIO_135, + GPIO_136, + GPIO_137, + GPIO_138, + GPIO_139, + GPIO_140, + GPIO_141, + GPIO_142, + GPIO_143, + GPIO_144, + GPIO_145, + GPIO_146, + GPIO_147, + GPIO_148, + GPIO_149, + GPIO_150, + GPIO_151, + GPIO_152, + GPIO_153, + GPIO_154, + GPIO_155, + GPIO_156, + GPIO_157, + GPIO_158, + GPIO_159, + GPIO_160, + GPIO_161, + GPIO_162, + GPIO_163, + GPIO_164, + GPIO_165, + GPIO_166, + GPIO_167, + GPIO_168, + GPIO_169, + GPIO_170, + GPIO_171, + GPIO_172, + GPIO_173, + GPIO_174, + GPIO_175, + GPIO_176, + GPIO_177, + GPIO_178, + GPIO_179, + GPIO_180, + GPIO_181, + GPIO_182, + GPIO_183, + GPIO_184, + GPIO_185, + GPIO_186, + GPIO_187, + GPIO_188, + GPIO_189, + GPIO_190, + GPIO_191, + GPIO_192, + GPIO_193, + GPIO_194, + GPIO_195, + GPIO_196, + GPIO_197, + GPIO_198, + GPIO_199, + GPIO_200, + GPIO_201, + GPIO_202, + GPIO_203, + GPIO_204, + GPIO_205, + GPIO_206, + GPIO_207, + GPIO_208, + GPIO_209, + GPIO_210, + GPIO_211, + GPIO_212, + GPIO_213, + GPIO_214, + GPIO_215, + GPIO_216, + GPIO_217, + GPIO_218, + GPIO_219, + GPIO_220, + GPIO_221, + GPIO_222, + GPIO_223, + GPIO_224, + GPIO_225, + GPIO_226, + GPIO_227, + GPIO_228, + GPIO_229, + MAX_GPIO_NO +} GPIO_COUNT; + +typedef struct _GPIO_SETTINGS +{ + u8 select; + u8 type; + u8 value; + u8 NonGpioGevent; +} GPIO_SETTINGS; + +GPIO_SETTINGS gpio_table[]= +{ + {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT}, + {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT}, + {GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT}, + {GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT}, + {GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT}, + {GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT}, + {GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT}, + {GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT}, + {GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT}, + {GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT}, + {GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT}, + {GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT}, + {GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT}, + {GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT}, + {GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT}, + {GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT}, + {GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT}, + {GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT}, + {GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT}, + {GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT}, + {GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT}, + {GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT}, + {GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT}, + {GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT}, + {GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT}, + {GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT}, + {GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT}, + {GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT}, + {GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT}, + {GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT}, + {GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT}, + {GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT}, + {GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT}, + {GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT}, + {GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT}, + {GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT}, + {GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT}, + {GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT}, + {GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT}, + {GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT}, + {GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT}, + {GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT}, + {GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT}, + {GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT}, + {GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT}, + {GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT}, + {GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT}, + {GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT}, + {GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT}, + {GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT}, + {GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT}, + {GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT}, + {GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT}, + {GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT}, + {GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT}, + {GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT}, + {GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT}, + {GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT}, + {GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT}, + {GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT}, + {GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT}, + {GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT}, + {GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT}, + {GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT}, + {GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT}, + {GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT}, + {GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT}, + {GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT}, + {GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT}, + {GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT}, + {GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT}, + {GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT}, + {GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT}, + {GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT}, + {GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT}, + {GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT}, + {GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT}, + {GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT}, + {GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT}, + {GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT}, + {GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT}, + {GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT}, + {GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT}, + {GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT}, + {GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT}, + {GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT}, + {GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT}, + {GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT}, + {GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT}, + {GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT}, + {GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT}, + {GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT}, + {GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT}, + {GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT}, + {GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT}, + {GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT}, + {GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT}, + {GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT}, + {GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT}, + {GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT}, + {GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT}, + {GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT}, + {GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT}, + {GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT}, + {GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT}, + {GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT}, + {GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT}, + {GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT}, + {GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT}, + {GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT}, + {GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT}, + {GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT}, + {GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT}, + {GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT}, + {GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT}, + {GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT}, + {GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT}, + {GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT}, + {GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT}, + {GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT}, + {GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT}, + {GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT}, + {GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT}, + {GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT}, + {GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT}, + {GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT}, + {GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT}, + {GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT}, + {GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT}, + {GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT}, + {GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT}, + {GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT}, + {GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT}, + {GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT}, + {GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT}, + {GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT}, + {GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT}, + {GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT}, + {GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT}, + {GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT}, + {GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT}, + {GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT}, + {GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT}, + {GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT}, + {GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT}, + {GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT}, + {GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT}, + {GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT}, + {GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT}, + {GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT}, + {GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT}, + {GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT}, + {GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT}, + {GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT}, + {GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT}, + {GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT}, + {GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT}, + {GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT}, + {GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT}, + {GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT}, + {GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT}, + {GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT}, + {GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT}, + {GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT}, + {GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT}, + {GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT}, + {GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT}, + {GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT}, + {GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT}, + {GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT}, + {GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT}, + {GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT}, + {GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT}, + {GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT}, + {GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT}, + {GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT}, + {GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT}, + {GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT}, + {GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT}, + {GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT}, + {GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT}, + {GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT}, + {GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT}, + {GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT}, + {GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT}, + {GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT}, + {GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT}, + {GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT}, + {GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT}, + {GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT}, + {GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT}, + {GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT}, + {GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT}, + {GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT}, + {GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT}, + {GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT}, + {GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT}, + {GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT}, + {GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT}, + {GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT}, + {GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT}, + {GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT}, + {GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT}, + {GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT}, + {GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT}, + {GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT}, + {GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT}, + {GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT}, + {GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT}, + {GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT}, + {GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT}, + {GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT}, + {GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT}, + {GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT}, + {GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT}, + {GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT}, + {GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT}, + {GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT}, + {GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT}, + {GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT}, + {GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT}, + {GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT}, + {GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT}, + {GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT}, + {GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT}, + {GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT}, + {GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT}, + {GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT}, + {GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT}, + {GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT}, +}; + +typedef enum _GEVENT_COUNT +{ + GEVENT_00=0x60, + GEVENT_01, + GEVENT_02, + GEVENT_03, + GEVENT_04, + GEVENT_05, + GEVENT_06, + GEVENT_07, + GEVENT_08, + GEVENT_09, + GEVENT_10, + GEVENT_11, + GEVENT_12, + GEVENT_13, + GEVENT_14, + GEVENT_15, + GEVENT_16, + GEVENT_17, + GEVENT_18, + GEVENT_19, + GEVENT_20, + GEVENT_21, + GEVENT_22, + GEVENT_23 +} GEVENT_COUNT; + +typedef struct _GEVENT_SETTINGS +{ + u8 EventEnable; // 0: Disable, 1: Enable + u8 SciTrig; // 0: Falling Edge, 1: Rising Edge + u8 SciLevl; // 0: Edge trigger, 1: Level Trigger + u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI + u8 SciS0En; // 0: Disable, 1: Enable + u8 SciMap; // 0000b->1111b + u8 SmiTrig; // 0: Active Low, 1: Active High + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 +} GEVENT_SETTINGS; + +GEVENT_SETTINGS gevent_table[] = +{ + {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL}, + {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL}, + {GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL}, + {GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL}, + {GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL}, + {GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL}, + {GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL}, + {GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL}, + {GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL}, + {GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL}, + {GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL}, + {GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL}, + {GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL}, + {GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL}, + {GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL}, + {GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL}, + {GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL}, + {GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL}, + {GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL}, + {GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL}, + {GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL}, + {GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL}, + {GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL}, + {GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL}, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c new file mode 100644 index 0000000..afd8c67 --- /dev/null +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include + + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb700[2]; +extern unsigned long sbdn_sb700; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb700[0]; + pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c new file mode 100644 index 0000000..9d10390 --- /dev/null +++ b/src/mainboard/amd/dinar/mainboard.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define ONE_MB 0x100000 +//#define SMBUS_IO_BASE 0x6000 + +void set_pcie_reset(void *nbconfig); +void set_pcie_dereset(void *nbconfig); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void *nbconfig) +{ +} + +/** + * Mainboard specific RD890 CIMx callback + * Release Resets to PCIe Links + * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie + */ +void set_pcie_dereset(void *nbconfig) +{ + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; + + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } +} + +uint64_t uma_memory_base, uma_memory_size; + +/************************************************* + * enable the dedicated function in dinar board. + *************************************************/ +static void dinar_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeOR () */ + /* + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + */ + sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + uma_memory_size = 512 * ONE_MB; + } else if (sys_mem >= 1024 * ONE_MB) { + uma_memory_size = 256 * ONE_MB; + } else { + uma_memory_size = 64 * ONE_MB; + } + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ + uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ +#endif + +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME("AMD DINAR Mainboard") + .enable_dev = dinar_enable, +}; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c new file mode 100644 index 0000000..b43080d --- /dev/null +++ b/src/mainboard/amd/dinar/mptable.c @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_rd890[14]; +extern u8 bus_sb700[2]; +extern u32 bus_type[256]; +extern u32 sbdn_rd890; +extern u32 sbdn_sb700; + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicid_sb700; + u32 apicid_rd890; + device_t dev; + u32 dword; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + get_bus_conf(); + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. + dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + if (dev) { + /* Set sb700 IOAPIC ID */ + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb700, 0x20, dword); + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + + /* Set RS5650 IOAPIC ID */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_rd890, 0x20, dword); + } + + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) + + /* SMBUS */ + //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x2, 0x10); + + /* USB */ + /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ + /* EHCI hard-wired to 02h, corresponding to using INTB# */ + /* USB1 */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ + PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ + PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ + + /* USB2 */ + PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ + PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ + PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ + + /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ + PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + + /* on board NIC & Slot PCIE. */ + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13); + */ + + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h new file mode 100644 index 0000000..8265f87 --- /dev/null +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c new file mode 100644 index 0000000..9518691 --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include +#include + +#ifndef __PRE_RAM__ +#include +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h new file mode 100644 index 0000000..a4f4e1a --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +#define RD890_IOAPIC_ADDR 0xC8000000 +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c new file mode 100644 index 0000000..4cc1efd --- /dev/null +++ b/src/mainboard/amd/dinar/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c new file mode 100644 index 0000000..6f3911a --- /dev/null +++ b/src/mainboard/amd/dinar/romstage.c @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpu/x86/bist.h" +#include "superio/smsc/sch4037/sch4037_early_init.c" +#include "superio/smsc/sio1036/sio1036_early_init.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "pc80/i8254.c" +#include "pc80/i8259.c" +#include "nb_cimx.h" +#include "sb_cimx.h" +#include "Platform.h" +#include + +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +u32 agesawrapper_amdinitmmio (void); +u32 agesawrapper_amdinitreset (void); +u32 agesawrapper_amdinitearly (void); +u32 agesawrapper_amdinitenv (void); +u32 agesawrapper_amdinitlate (void); +u32 agesawrapper_amdinitpost (void); +u32 agesawrapper_amdinitmid (void); + + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + if (!cpu_init_detectedx && boot_cpu()) { + + post_code(0x30); + + sch4037_early_init (CONFIG_SIO_PORT); + + /* Detect SMSC SIO1036 LPC Debug Card status */ + if (detect_sio1036_chip(0x4E)) { + /* Found SMSC SIO1036 LPC Debug Card */ + sio1036_early_init(0x4E); + } + + post_code(0x31); + uart_init(); + console_init(); + + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + } + + post_code(0x32); + val = agesawrapper_amdinitmmio(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); + } + + /* Halt if there was a built in self test failure */ + post_code(0x33); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + if(boot_cpu()) { + post_code(0x34); + sb_Poweron_Init(); + } + + post_code(0x35); + val = agesawrapper_amdinitreset(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); + } + + post_code(0x36); + val = agesawrapper_amdinitearly (); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); + } + + post_code(0x37); + nb_Poweron_Init(); + post_code(0x38); + nb_Ht_Init(); + + + post_code(0x39); + val = agesawrapper_amdinitpost (); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); + } + + post_code(0x40); + val = agesawrapper_amdinitenv (); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); + } + + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x43); + print_debug("Disabling cache as ram "); + disable_cache_as_ram(); + print_debug("done\n"); + + post_code(0x44); + copy_and_run(0); + + post_code(0x45); // Should never see this post code. +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c new file mode 100644 index 0000000..b2f3d17 --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - No sb_config.\n", __func__); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - Start.\n", __func__); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__); +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h new file mode 100644 index 0000000..b405f0e --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_ From gerrit at coreboot.org Tue Feb 7 13:24:31 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Tue, 7 Feb 2012 13:24:31 +0100 Subject: [coreboot] Patch set updated for coreboot: b0eef97 HWM: Nuvoton W83795G/ADG HWM support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569 -gerrit commit b0eef97a218291d9efa44891b67f7ab74e434e51 Author: Kerry Sheh Date: Tue Feb 7 20:33:21 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/drivers/i2c/Kconfig | 1 + src/drivers/i2c/Makefile.inc | 1 + src/drivers/i2c/w83795/Kconfig | 2 + src/drivers/i2c/w83795/Makefile.inc | 1 + src/drivers/i2c/w83795/chip.h | 4 + src/drivers/i2c/w83795/w83795.c | 261 ++++++++++++++++++++++++++ src/drivers/i2c/w83795/w83795.h | 73 +++++++ src/mainboard/supermicro/h8qgi/Kconfig | 1 + src/mainboard/supermicro/h8qgi/devicetree.cb | 8 +- src/mainboard/supermicro/h8qgi/romstage.c | 6 + 10 files changed, 356 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig index 91ad025..09c306b 100644 --- a/src/drivers/i2c/Kconfig +++ b/src/drivers/i2c/Kconfig @@ -4,3 +4,4 @@ source src/drivers/i2c/adt7463/Kconfig source src/drivers/i2c/i2cmux/Kconfig source src/drivers/i2c/i2cmux2/Kconfig source src/drivers/i2c/lm63/Kconfig +source src/drivers/i2c/w83795/Kconfig diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc index d462b69..97e9729 100644 --- a/src/drivers/i2c/Makefile.inc +++ b/src/drivers/i2c/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += adt7463 subdirs-y += i2cmux subdirs-y += i2cmux2 subdirs-y += lm63 +subdirs-y += w83795 diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig new file mode 100644 index 0000000..80856e2 --- /dev/null +++ b/src/drivers/i2c/w83795/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_W83795 + bool diff --git a/src/drivers/i2c/w83795/Makefile.inc b/src/drivers/i2c/w83795/Makefile.inc new file mode 100644 index 0000000..708a170 --- /dev/null +++ b/src/drivers/i2c/w83795/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h new file mode 100644 index 0000000..2900636 --- /dev/null +++ b/src/drivers/i2c/w83795/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations drivers_i2c_w83795_ops; + +struct drivers_i2c_w83795_config { +}; diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c new file mode 100644 index 0000000..392471a --- /dev/null +++ b/src/drivers/i2c/w83795/w83795.c @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include "w83795.h" + +static u32 w83795_set_bank(u8 bank) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); +} + +static u8 w83795_read(u16 reg) +{ + u32 ret; + + ret = w83795_set_bank(reg >> 8); + if (ret < 0) { + printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8); + return -1; + } + + ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff); + return ret; +} + +static u8 w83795_write(u16 reg, u8 value) +{ + u32 err; + + err = w83795_set_bank(reg >> 8); + if (err < 0) { + printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8); + return -1; + } + + err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value); + return err; +} + +/* + * Enable Digital Temperature Sensor + */ +static void w83795_dts_enable(u8 dts_src) +{ + u8 val; + + /* DIS */ + val = w83795_read(W83795_REG_DTSC); + val |= (dts_src & 0x01); + w83795_write(W83795_REG_DTSC, val); + + /* DTSE */ + val = w83795_read(W83795_REG_DTSE); + val |= 0xFF; + w83795_write(W83795_REG_DTSE, val); + + /* store bank3 regs first before enable DTS */ + + /* + * TD/TR1-4 termal diode by default + * 0x00 Disable + * 0x01 thermistors on motherboard + * 0x10 different mode voltage + * 0x11 CPU internal thermal diode output + * + * TR5-6 thermistors by default TRn + */ + val = 0x55; /* thermal diode */ + w83795_write(W83795_REG_TEMP_CTRL2, val); + + /* Enable Digital Temperature Sensor */ + val = w83795_read(W83795_REG_TEMP_CTRL1); + val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */ + w83795_write(W83795_REG_TEMP_CTRL1, val); +} + +static void w83795_set_tfmr(w83795_fan_mode_t mode) +{ + u8 val; + u8 i; + + if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) { + val = 0xFF; + } else { + val = 0x00; + } + + for (i = 0; i < 6; i++) + w83795_write(W83795_REG_TFMR(i), val); +} + +static u32 w83795_set_fan_mode(w83795_fan_mode_t mode) +{ + if (mode == SPEED_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS1, 0xFF); + printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n"); + } else { + w83795_write(W83795_REG_FCMS1, 0x00); + if (mode == THERMAL_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS2, 0x00); + printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n"); + } else if (mode == SMART_FAN_MODE) { + w83795_write(W83795_REG_FCMS2, 0x3F); + printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n"); + } else { + printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n"); + return -1; + } + } + + return 0; +} + +static void w83795_set_tss(void) +{ + u8 val; + + val = 0x00; + w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */ + w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */ + w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */ +} + +static void w83795_set_fan(w83795_fan_mode_t mode) +{ + u8 i; + + /* select temperature sensor (TSS)*/ + w83795_set_tss(); + + /* select Temperature to Fan mapping Relationships (TFMR)*/ + w83795_set_tfmr(mode); + + /* set fan output controlled mode (FCMS)*/ + w83795_set_fan_mode(mode); + + /* Set Critical Temperature to Full Speed all fan (CTFS) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */ + } + + if (mode == THERMAL_CRUISE_MODE) { + /* Set Target Temperature of Temperature Inputs (TTTI) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */ + } + } else if (mode == SMART_FAN_MODE) { + /* Set the Relative Register-at SMART FAN IV Control Mode Table */ + //SFIV TODO + } + + /* Set Hystersis of Temperature (HT) */ + //TODO +} + +static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +{ + u8 i; + u8 val; + + if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } + val = w83795_read(W83795_REG_CONFIG); + if ((val & W83795_REG_CONFIG_CONFIG48) == 0) + printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); + else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); + + /* Reset */ + val |= W83795_REG_CONFIG_INIT; + w83795_write(W83795_REG_CONFIG, val); + + /* Fan monitoring setting */ + val = 0xFF; /* FAN1-FAN8 */ + w83795_write(W83795_REG_FANIN_CTRL1, val); + val = 0x3F; /* FAN9-FAN14 */ + w83795_write(W83795_REG_FANIN_CTRL2, val); + + /* enable monitoring operations */ + val = w83795_read(W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(W83795_REG_CONFIG, val); + + w83795_dts_enable(dts_src); + w83795_set_fan(mode); + + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + for (i = 0; i < 6; i++) { + val = w83795_read(W83795_REG_CTFS(i)); + printk(BIOS_INFO, " %x %d", i, val); + val = w83795_read(W83795_REG_TTTI(i)); + printk(BIOS_INFO, " %d\n", val); + } + + /* Temperature ReadOut */ + for (i = 0; i < 9; i++) { + val = w83795_read(W83795_REG_DTS(i)); + printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val); + } +} + +static void w83795_hwm_init(device_t dev) +{ + struct device *cpu; + struct cpu_info *info; + + info = cpu_info(); + cpu = info->cpu; + if (!cpu) + die("CPU: missing cpu device structure"); + + if (cpu->vendor == X86_VENDOR_AMD) + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); + else if (cpu->vendor == X86_VENDOR_INTEL) + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_INTEL_PECI); + else + printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); +} + +static void w83795_noop(device_t dummy) +{ +} + +static struct device_operations w83795_operations = { + .read_resources = w83795_noop, + .set_resources = w83795_noop, + .enable_resources = w83795_noop, + .init = w83795_hwm_init, +}; + +static void enable_dev(device_t dev) +{ + dev->ops = &w83795_operations; +} + +struct chip_operations drivers_i2c_w83795_ops = { + CHIP_NAME("Nuvoton W83795G/ADG Hardware Monitor") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h new file mode 100644 index 0000000..de0a554 --- /dev/null +++ b/src/drivers/i2c/w83795/w83795.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _W83795_H_ +#define _W83795_H_ + +#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ + +#define W83795_REG_I2C_ADDR 0xFC +#define W83795_REG_BANKSEL 0x00 +#define W83795_REG_CONFIG 0x01 +#define W83795_REG_CONFIG_START 0x01 +#define W83795_REG_CONFIG_CONFIG48 0x04 +#define W83795_REG_CONFIG_INIT 0x80 + +#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ +#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ +#define W83795_REG_FANIN_CTRL1 0x06 +#define W83795_REG_FANIN_CTRL2 0x07 +#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ +#define DTS_SRC_INTEL_PECI (0 << 0) +#define DTS_SRC_AMD_SBTSI (1 << 0) + +#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ +#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ +#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ +#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ +#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ + +#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ +#define W83795_REG_DTS(n) (0x26 + (n)) +#define W83795_REG_VRLSB 0x3C + +#define W83795_TEMP_REG_TR1 0x21 +#define W83795_TEMP_REG_TR2 0x22 +#define W83795_TEMP_REG_TR3 0x23 +#define W83795_TEMP_REG_TR4 0x24 +#define W83795_TEMP_REG_TR5 0x1F +#define W83795_TEMP_REG_TR6 0x20 + +#define W83795_REG_FCMS1 0x201 +#define W83795_REG_FCMS2 0x208 +#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ +#define W83795_REG_DFSP 0x20C + +#define W83795_REG_FTSH(n) (0x240 + (n) * 2) +#define W83795_REG_FTSL(n) (0x241 + (n) * 2) +#define W83795_REG_TFTS 0x250 + +typedef enum w83795_fan_mode { + SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range + THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI + SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed + MANUAL_MODE, ///< control manually +} w83795_fan_mode_t; + +#endif diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..58f5692 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select DRIVERS_I2C_W83795 select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 9d77a73..8ecf968 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -84,8 +84,8 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 0x01 #keyboard irq 0x72 = 0x0C #mouse end - #device pnp 2e.6 off # SPI - #end + device pnp 2e.6 off # SPI + end device pnp 2e.307 off # GPIO6 end device pnp 2e.8 off # WDTO#, PLED @@ -106,6 +106,10 @@ chip northbridge/amd/agesa/family15/root_complex device pnp 2e.c off # PECI, SST end end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 end # LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ba8c5e5..d4354fd 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -90,6 +90,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ From gerrit at coreboot.org Tue Feb 7 13:41:04 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Feb 2012 13:41:04 +0100 Subject: [coreboot] New patch to review for coreboot: 5768f68 Delete hard-coded driver includes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/610 -gerrit commit 5768f68244998e1b2c1596540509d4dfcf419286 Author: Ky?sti M?lkki Date: Tue Feb 7 14:19:43 2012 +0200 Delete hard-coded driver includes Driver components are conditionally included in the build using the Kconfig options. Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58 Signed-off-by: Ky?sti M?lkki --- src/mainboard/amd/serengeti_cheetah/Kconfig | 5 +++-- src/mainboard/amd/serengeti_cheetah/Makefile.inc | 1 - src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 1 + .../amd/serengeti_cheetah_fam10/Makefile.inc | 1 - src/mainboard/asus/m2v-mx_se/Kconfig | 1 + src/mainboard/broadcom/blast/Kconfig | 1 + src/mainboard/broadcom/blast/Makefile.inc | 1 - src/mainboard/hp/dl145_g1/Kconfig | 1 + src/mainboard/hp/dl145_g1/Makefile.inc | 1 - src/mainboard/msi/ms9282/Kconfig | 2 ++ src/mainboard/msi/ms9282/Makefile.inc | 4 ---- src/mainboard/supermicro/h8dme/Kconfig | 1 + src/mainboard/supermicro/h8dme/Makefile.inc | 2 -- src/mainboard/supermicro/x6dhe_g/Makefile.inc | 1 - src/mainboard/supermicro/x6dhe_g2/Makefile.inc | 1 - src/mainboard/tyan/s2881/Kconfig | 1 + src/mainboard/tyan/s2881/Makefile.inc | 1 - src/mainboard/tyan/s2892/Kconfig | 1 + src/mainboard/tyan/s2892/Makefile.inc | 2 -- 19 files changed, 12 insertions(+), 17 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index fcdeb49..b44de64 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -3,8 +3,9 @@ if BOARD_AMD_SERENGETI_CHEETAH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select SOUTHBRIDGE_AMD_AMD8132 - select SOUTHBRIDGE_AMD_AMD8151 + select DRIVERS_I2C_I2CMUX + select SOUTHBRIDGE_AMD_AMD8132 + select SOUTHBRIDGE_AMD_AMD8151 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc index b8cdba5..1ba662e 100644 --- a/src/mainboard/amd/serengeti_cheetah/Makefile.inc +++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc @@ -17,4 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += ../../../drivers/i2c/i2cmux/i2cmux.c diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index feecdec..576eaae 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -3,6 +3,7 @@ if BOARD_AMD_SERENGETI_CHEETAH_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_I2CMUX2 select CPU_AMD_SOCKET_F_1207 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc index 70b429d..1ba662e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc @@ -17,4 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 6434306..99da857 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -21,6 +21,7 @@ if BOARD_ASUS_M2V_MX_SE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select SOUTHBRIDGE_VIA_K8T890 select CPU_AMD_SOCKET_AM2 select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index 4bad57d..1a9574b 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -3,6 +3,7 @@ if BOARD_BROADCOM_BLAST config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_I2CMUX2 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX diff --git a/src/mainboard/broadcom/blast/Makefile.inc b/src/mainboard/broadcom/blast/Makefile.inc index 9e76151..77fa6eb 100644 --- a/src/mainboard/broadcom/blast/Makefile.inc +++ b/src/mainboard/broadcom/blast/Makefile.inc @@ -1,4 +1,3 @@ # Needed by irq_tables and mptable and acpi_tables. -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index ebd7ffd..88ca996 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -3,6 +3,7 @@ if BOARD_HP_DL145_G1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_I2CMUX select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX diff --git a/src/mainboard/hp/dl145_g1/Makefile.inc b/src/mainboard/hp/dl145_g1/Makefile.inc index d3097a1..e69de29 100644 --- a/src/mainboard/hp/dl145_g1/Makefile.inc +++ b/src/mainboard/hp/dl145_g1/Makefile.inc @@ -1 +0,0 @@ -ramstage-y += ../../../drivers/i2c/i2cmux/i2cmux.c \ No newline at end of file diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index 3ccc3f9..802b8c5 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -3,6 +3,8 @@ if BOARD_MSI_MS9282 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_ADM1027 + select DRIVERS_I2C_I2CMUX2 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc index e8d9af1..1ba662e 100644 --- a/src/mainboard/msi/ms9282/Makefile.inc +++ b/src/mainboard/msi/ms9282/Makefile.inc @@ -17,7 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME drivers should be selected through Kconfig -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c -ramstage-y += ../../../drivers/i2c/adm1027/adm1027.c - diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index ce49a47..e66b159 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -3,6 +3,7 @@ if BOARD_SUPERMICRO_H8DME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_I2CMUX2 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/supermicro/h8dme/Makefile.inc b/src/mainboard/supermicro/h8dme/Makefile.inc index 765096d..71baa03 100644 --- a/src/mainboard/supermicro/h8dme/Makefile.inc +++ b/src/mainboard/supermicro/h8dme/Makefile.inc @@ -17,6 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c - # Needed by irq_tables and mptable and acpi_tables. diff --git a/src/mainboard/supermicro/x6dhe_g/Makefile.inc b/src/mainboard/supermicro/x6dhe_g/Makefile.inc index 30eacbd..495602d 100644 --- a/src/mainboard/supermicro/x6dhe_g/Makefile.inc +++ b/src/mainboard/supermicro/x6dhe_g/Makefile.inc @@ -19,4 +19,3 @@ ## ROMCCFLAGS=-mcpu=p4 -O2 -ramstage-y += ../../../drivers/generic/debug/debug_dev.c diff --git a/src/mainboard/supermicro/x6dhe_g2/Makefile.inc b/src/mainboard/supermicro/x6dhe_g2/Makefile.inc index 30eacbd..495602d 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Makefile.inc +++ b/src/mainboard/supermicro/x6dhe_g2/Makefile.inc @@ -19,4 +19,3 @@ ## ROMCCFLAGS=-mcpu=p4 -O2 -ramstage-y += ../../../drivers/generic/debug/debug_dev.c diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index fd5fca8..92346a1 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -3,6 +3,7 @@ if BOARD_TYAN_S2881 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_ADT7463 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX diff --git a/src/mainboard/tyan/s2881/Makefile.inc b/src/mainboard/tyan/s2881/Makefile.inc index 1de4a6c..e69de29 100644 --- a/src/mainboard/tyan/s2881/Makefile.inc +++ b/src/mainboard/tyan/s2881/Makefile.inc @@ -1 +0,0 @@ -ramstage-y += ../../../drivers/i2c/adt7463/adt7463.c diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index 88703f3..11da7f7 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -3,6 +3,7 @@ if BOARD_TYAN_S2892 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select DRIVERS_I2C_ADM1027 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX diff --git a/src/mainboard/tyan/s2892/Makefile.inc b/src/mainboard/tyan/s2892/Makefile.inc index c371ad0..e69de29 100644 --- a/src/mainboard/tyan/s2892/Makefile.inc +++ b/src/mainboard/tyan/s2892/Makefile.inc @@ -1,2 +0,0 @@ - -ramstage-y += ../../../drivers/i2c/adm1027/adm1027.c From gerrit at coreboot.org Tue Feb 7 14:01:30 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Feb 2012 14:01:30 +0100 Subject: [coreboot] Patch set updated for coreboot: 3b31dca Delete hard-coded driver includes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/610 -gerrit commit 3b31dcaa10f1db54a1a2b15728011a47e789353f Author: Ky?sti M?lkki Date: Tue Feb 7 14:59:07 2012 +0200 Delete hard-coded driver includes Driver components are conditionally included in the build using the Kconfig options. Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58 Signed-off-by: Ky?sti M?lkki --- src/mainboard/amd/serengeti_cheetah/Kconfig | 5 +++-- src/mainboard/amd/serengeti_cheetah/Makefile.inc | 1 - src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 1 + .../amd/serengeti_cheetah_fam10/Makefile.inc | 1 - src/mainboard/broadcom/blast/Kconfig | 1 + src/mainboard/broadcom/blast/Makefile.inc | 1 - src/mainboard/hp/dl145_g1/Kconfig | 1 + src/mainboard/hp/dl145_g1/Makefile.inc | 1 - src/mainboard/msi/ms9282/Kconfig | 2 ++ src/mainboard/msi/ms9282/Makefile.inc | 4 ---- src/mainboard/supermicro/h8dme/Kconfig | 1 + src/mainboard/supermicro/h8dme/Makefile.inc | 2 -- src/mainboard/supermicro/x6dhe_g/Makefile.inc | 1 - src/mainboard/supermicro/x6dhe_g2/Makefile.inc | 1 - src/mainboard/tyan/s2881/Kconfig | 1 + src/mainboard/tyan/s2881/Makefile.inc | 1 - src/mainboard/tyan/s2892/Kconfig | 1 + src/mainboard/tyan/s2892/Makefile.inc | 2 -- 18 files changed, 11 insertions(+), 17 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index fcdeb49..5cd07c6 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -3,8 +3,8 @@ if BOARD_AMD_SERENGETI_CHEETAH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select SOUTHBRIDGE_AMD_AMD8132 - select SOUTHBRIDGE_AMD_AMD8151 + select SOUTHBRIDGE_AMD_AMD8132 + select SOUTHBRIDGE_AMD_AMD8151 select CPU_AMD_SOCKET_F select DIMM_DDR2 select DIMM_REGISTERED @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_I2CMUX config MAINBOARD_DIR string diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc index b8cdba5..1ba662e 100644 --- a/src/mainboard/amd/serengeti_cheetah/Makefile.inc +++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc @@ -17,4 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += ../../../drivers/i2c/i2cmux/i2cmux.c diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index feecdec..df71444 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_APIC_EXT_ID select LIFT_BSP_APIC_ID select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_I2CMUX2 config MAINBOARD_DIR string diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc index 70b429d..1ba662e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc @@ -17,4 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index 4bad57d..b2f923d 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_I2CMUX2 config MAINBOARD_DIR string diff --git a/src/mainboard/broadcom/blast/Makefile.inc b/src/mainboard/broadcom/blast/Makefile.inc index 9e76151..77fa6eb 100644 --- a/src/mainboard/broadcom/blast/Makefile.inc +++ b/src/mainboard/broadcom/blast/Makefile.inc @@ -1,4 +1,3 @@ # Needed by irq_tables and mptable and acpi_tables. -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index ebd7ffd..d2de8a2 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_I2CMUX config MAINBOARD_DIR string diff --git a/src/mainboard/hp/dl145_g1/Makefile.inc b/src/mainboard/hp/dl145_g1/Makefile.inc index d3097a1..e69de29 100644 --- a/src/mainboard/hp/dl145_g1/Makefile.inc +++ b/src/mainboard/hp/dl145_g1/Makefile.inc @@ -1 +0,0 @@ -ramstage-y += ../../../drivers/i2c/i2cmux/i2cmux.c \ No newline at end of file diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index 3ccc3f9..9e8cf4e 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_ADM1027 + select DRIVERS_I2C_I2CMUX2 config MAINBOARD_DIR string diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc index e8d9af1..1ba662e 100644 --- a/src/mainboard/msi/ms9282/Makefile.inc +++ b/src/mainboard/msi/ms9282/Makefile.inc @@ -17,7 +17,3 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# FIXME drivers should be selected through Kconfig -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c -ramstage-y += ../../../drivers/i2c/adm1027/adm1027.c - diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index ce49a47..376b81a 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE select SET_FIDVID + select DRIVERS_I2C_I2CMUX2 config MAINBOARD_DIR string diff --git a/src/mainboard/supermicro/h8dme/Makefile.inc b/src/mainboard/supermicro/h8dme/Makefile.inc index 765096d..71baa03 100644 --- a/src/mainboard/supermicro/h8dme/Makefile.inc +++ b/src/mainboard/supermicro/h8dme/Makefile.inc @@ -17,6 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += ../../../drivers/i2c/i2cmux2/i2cmux2.c - # Needed by irq_tables and mptable and acpi_tables. diff --git a/src/mainboard/supermicro/x6dhe_g/Makefile.inc b/src/mainboard/supermicro/x6dhe_g/Makefile.inc index 30eacbd..495602d 100644 --- a/src/mainboard/supermicro/x6dhe_g/Makefile.inc +++ b/src/mainboard/supermicro/x6dhe_g/Makefile.inc @@ -19,4 +19,3 @@ ## ROMCCFLAGS=-mcpu=p4 -O2 -ramstage-y += ../../../drivers/generic/debug/debug_dev.c diff --git a/src/mainboard/supermicro/x6dhe_g2/Makefile.inc b/src/mainboard/supermicro/x6dhe_g2/Makefile.inc index 30eacbd..495602d 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Makefile.inc +++ b/src/mainboard/supermicro/x6dhe_g2/Makefile.inc @@ -19,4 +19,3 @@ ## ROMCCFLAGS=-mcpu=p4 -O2 -ramstage-y += ../../../drivers/generic/debug/debug_dev.c diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index fd5fca8..0073ebb 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SB_HT_CHAIN_UNITID_OFFSET_ONLY select DRIVERS_SIL_3114 select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_ADT7463 config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s2881/Makefile.inc b/src/mainboard/tyan/s2881/Makefile.inc index 1de4a6c..e69de29 100644 --- a/src/mainboard/tyan/s2881/Makefile.inc +++ b/src/mainboard/tyan/s2881/Makefile.inc @@ -1 +0,0 @@ -ramstage-y += ../../../drivers/i2c/adt7463/adt7463.c diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index 88703f3..d58f5ab 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select QRANK_DIMM_SUPPORT + select DRIVERS_I2C_ADM1027 config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s2892/Makefile.inc b/src/mainboard/tyan/s2892/Makefile.inc index c371ad0..e69de29 100644 --- a/src/mainboard/tyan/s2892/Makefile.inc +++ b/src/mainboard/tyan/s2892/Makefile.inc @@ -1,2 +0,0 @@ - -ramstage-y += ../../../drivers/i2c/adm1027/adm1027.c From hagigatali at gmail.com Tue Feb 7 14:57:05 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 17:27:05 +0330 Subject: [coreboot] I can not add FILO as a payload Message-ID: I want to add FILO as a payload. There are some errors. I got the Coreboot source by : git clone http://review.coreboot.org/p/coreboot Then inside the project I had: /root/bios/coreboot/payloads/libpayload, /root/bios/coreboot/payloads/filo I executed the some steps according to the following file: /root/bios/coreboot/payloads/filo/README cd payloads/libpayload/ /root/bios/coreboot/payloads/libpayload> make defconfig /root/bios/coreboot/payloads/libpayload> make /root/bios/coreboot/payloads/libpayload> make DESTDIR=../filo/build install /root/bios/coreboot/payloads/libpayload> cd ../filo /root/bios/coreboot/payloads/filo> make menuconfig /root/bios/coreboot/payloads/filo> make Found Libpayload /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/ipchecksum.o CC build/main/grub/grub.o CC build/main/grub/builtins.o CC build/main/grub/cmdline.o CC build/main/grub/char_io.o CC build/main/grub/completions.o CC build/main/grub/md5.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o CC build/fs/fsys_fat.o CC build/fs/fsys_reiserfs.o CC build/fs/fsys_iso9660.o CC build/fs/fsys_cbfs.o CC build/fs/cbfs.o /root/bios/coreboot/payloads/filo/fs/cbfs.c:113:20: error: conflicting types for 'cbfs_find_file' /root/bios/coreboot/payloads/filo/build/libpayload/include/cbfs_core.h:175:7: note: previous declaration of 'cbfs_find_file' was here make: *** [/root/bios/coreboot/payloads/filo/build/fs/cbfs.o] Error 1 I am copying the .config files of filo and lipayload: /root/bios/coreboot/payloads/filo> cat .config # # Automatically generated make config: don't edit # FILO version: 0.6.0 # Tue Feb 7 17:12:41 2012 # CONFIG_TARGET_I386=y # # Interface Options # CONFIG_USE_GRUB=y CONFIG_PROMPT="filo" CONFIG_MENULST_FILE="hda3:/boot/filo/menu.lst" CONFIG_MENULST_TIMEOUT=0 CONFIG_USE_MD5_PASSWORDS=y # CONFIG_ISOLINUX_PARSER is not set # # Drivers # CONFIG_IDE_DISK=y CONFIG_IDE_DISK_POLL_DELAY=0 # CONFIG_SLOW_SATA is not set # CONFIG_PCMCIA_CF is not set CONFIG_USB_DISK=y # CONFIG_FLASH_DISK is not set CONFIG_SUPPORT_PCI=y # CONFIG_PCI_BRUTE_SCAN is not set # CONFIG_SUPPORT_SOUND is not set # # Filesystems # CONFIG_FSYS_EXT2FS=y CONFIG_FSYS_FAT=y # CONFIG_FSYS_JFS is not set # CONFIG_FSYS_MINIX is not set CONFIG_FSYS_REISERFS=y # CONFIG_FSYS_XFS is not set CONFIG_FSYS_ISO9660=y CONFIG_ELTORITO=y # CONFIG_FSYS_CRAMFS is not set # CONFIG_FSYS_SQUASHFS is not set CONFIG_FSYS_CBFS=y # # Loaders # CONFIG_LINUX_LOADER=y # CONFIG_WINCE_LOADER is not set # CONFIG_ARTEC_BOOT is not set # # Debugging & Experimental # # CONFIG_EXPERIMENTAL is not set # CONFIG_DEBUG_ALL is not set # CONFIG_DEBUG_ELFBOOT is not set # CONFIG_DEBUG_SEGMENT is not set # CONFIG_DEBUG_SYS_INFO is not set # CONFIG_DEBUG_BLOCKDEV is not set # CONFIG_DEBUG_VFS is not set # CONFIG_DEBUG_FSYS_EXT2FS is not set # CONFIG_DEBUG_PCI is not set # CONFIG_DEBUG_LINUXLOAD is not set # CONFIG_DEBUG_IDE is not set # CONFIG_DEBUG_USB is not set # CONFIG_DEBUG_ELTORITO is not set CONFIG_DEVELOPER_TOOLS=y /root/bios/coreboot/payloads/libpayload> cat ./.config # # Automatically generated make config: don't edit # libpayload version: 0.2.0 # Tue Feb 7 17:08:09 2012 # # # Generic Options # # CONFIG_EXPERIMENTAL is not set # CONFIG_OBSOLETE is not set # CONFIG_DEVELOPER is not set # # Architecture Options # CONFIG_TARGET_I386=y # CONFIG_TARGET_POWERPC is not set # CONFIG_MEMMAP_RAM_ONLY is not set # CONFIG_MULTIBOOT is not set # # Standard Libraries # CONFIG_LIBC=y CONFIG_CURSES=y # CONFIG_TINYCURSES is not set CONFIG_PDCURSES=y CONFIG_CBFS=y CONFIG_LZMA=y # # Console Options # CONFIG_SERIAL_CONSOLE=y CONFIG_SERIAL_IOBASE=0x3f8 # CONFIG_SERIAL_SET_SPEED is not set # CONFIG_SERIAL_ACS_FALLBACK is not set CONFIG_VIDEO_CONSOLE=y CONFIG_VGA_VIDEO_CONSOLE=y # CONFIG_GEODELX_VIDEO_CONSOLE is not set CONFIG_COREBOOT_VIDEO_CONSOLE=y CONFIG_PC_KEYBOARD=y CONFIG_PC_KEYBOARD_LAYOUT_US=y # CONFIG_PC_KEYBOARD_LAYOUT_DE is not set # # Drivers # CONFIG_PCI=y CONFIG_NVRAM=y # CONFIG_RTC_PORT_EXTENDED_VIA is not set CONFIG_SPEAKER=y CONFIG_USB=y CONFIG_USB_UHCI=y CONFIG_USB_OHCI=y CONFIG_USB_EHCI=y CONFIG_USB_XHCI=y CONFIG_USB_HID=y CONFIG_USB_HUB=y CONFIG_USB_MSC=y What caused the problem then? From peter at stuge.se Tue Feb 7 15:15:21 2012 From: peter at stuge.se (Peter Stuge) Date: Tue, 7 Feb 2012 15:15:21 +0100 Subject: [coreboot] I can not add FILO as a payload In-Reply-To: References: Message-ID: <20120207141521.5164.qmail@stuge.se> ali hagigat wrote: > cd payloads/libpayload/ > /root/bios/coreboot/payloads/libpayload> make defconfig > /root/bios/coreboot/payloads/libpayload> make > /root/bios/coreboot/payloads/libpayload> make DESTDIR=../filo/build install > /root/bios/coreboot/payloads/libpayload> cd ../filo > /root/bios/coreboot/payloads/filo> make menuconfig So far so good. > /root/bios/coreboot/payloads/filo> make .. > CC build/fs/cbfs.o > /root/bios/coreboot/payloads/filo/fs/cbfs.c:113:20: error: conflicting types for 'cbfs_find_file' > /root/bios/coreboot/payloads/filo/build/libpayload/include/cbfs_core.h:175:7: note: previous declaration of 'cbfs_find_file' was here > make: *** [/root/bios/coreboot/payloads/filo/build/fs/cbfs.o] Error 1 .. > What caused the problem then? Look more closely at the error message. It is actually a very clear error message. Then you look at the source code pointed to by the error message. This process is the *very first* problem resolution process that *every* programmer in this world encounters. It is amazing that you seem to not know it. :\ FILO is probably not quite up to date with the latest libpayload API, so you now have an opportunity to fix this and make FILO better for everyone. //Peter From hagigatali at gmail.com Tue Feb 7 15:38:19 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 18:08:19 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <1328556068.5785.66.camel@obelix> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> Message-ID: Thank you, Ky?sti, for the reply. I tested the modified Coreboot by 115200 Buad rate, again the same message(latest post code seems to be 0x11)(modified Coreboot contains sdram_enable() changed and some fuction calls was commented out in romstage.c and i am using build/coreboot.rom as the final image on ROM chip): coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 17:40:50 IRST 2012 starting... Testing DRAM : 02000000 - 10000000 DRAM fill: 0x02000000-0x10000000 10000000 DRAM filled DRAM verify: 0x02000000-0x10000000 10000000 DRAM range verified. Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 lzma: Decoding error = 1 FATAL: Essential component is missing. My .config is: /root/bios/coreboot> cat ./.config # # Automatically generated make config: don't edit # coreboot version: 4.0-1959-g950f20a-dirty # Tue Feb 7 17:30:36 2012 # # # General setup # # CONFIG_EXPERT is not set CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_SCANBUILD_ENABLE is not set # CONFIG_CCACHE is not set # CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y # # Mainboard # # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTEC_GROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_DIGITAL_LOGIC is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PC_ENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/d810e2cb" CONFIG_MAINBOARD_PART_NUMBER="D810E2CB" CONFIG_IRQ_SLOT_COUNT=7 CONFIG_MAINBOARD_VENDOR="Intel" CONFIG_MAX_CPUS=1 CONFIG_MAX_PHYSICAL_CPUS=1 CONFIG_RAMTOP=0x200000 CONFIG_HEAP_SIZE=0x4000 CONFIG_RAMBASE=0x100000 CONFIG_VGA_BIOS_ID="8086,7121" CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0 CONFIG_SERIAL_CPU_INIT=y CONFIG_ACPI_SSDTX_NUM=0 # CONFIG_VGA_BIOS is not set CONFIG_STACK_SIZE=0x8000 CONFIG_DRIVERS_PS2_KEYBOARD=y CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_CONSOLE_POST is not set # CONFIG_PCI_64BIT_PREF_MEM is not set # CONFIG_MMCONF_SUPPORT_DEFAULT is not set CONFIG_BOARD_INTEL_D810E2CB=y # CONFIG_BOARD_INTEL_D945GCLF is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_JARRELL is not set # CONFIG_BOARD_INTEL_MTARVON is not set # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_XE7501DEVKIT is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_LOGICAL_CPUS=y # CONFIG_IOAPIC is not set CONFIG_SMP=y CONFIG_TTYS0_BAUD=115200 CONFIG_TTYS0_BASE=0x3f8 CONFIG_TTYS0_LCS=3 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 CONFIG_CONSOLE_SERIAL8250=y CONFIG_PCI_ROM_RUN=y # CONFIG_USBDEBUG is not set CONFIG_VAR_MTRR_HOLE=y # CONFIG_LIFT_BSP_APIC_ID is not set # CONFIG_WAIT_BEFORE_CPUS_INIT is not set # CONFIG_K8_REV_F_SUPPORT is not set CONFIG_BOARD_ROMSIZE_KB_512=y # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set CONFIG_COREBOOT_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set CONFIG_COREBOOT_ROMSIZE_KB=256 CONFIG_ROM_SIZE=0x40000 CONFIG_ARCH_X86=y # # Architecture (x86) # # CONFIG_AP_IN_SIPI_WAIT is not set CONFIG_ROMBASE=0xffff0000 CONFIG_MAX_REBOOT_CNT=3 CONFIG_X86_BOOTBLOCK_SIMPLE=y # CONFIG_X86_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_UPDATE_IMAGE is not set # CONFIG_ROMCC is not set CONFIG_PC80_SYSTEM=y # CONFIG_HAVE_CMOS_DEFAULT is not set # CONFIG_BIG_ENDIAN is not set CONFIG_LITTLE_ENDIAN=y # # Chipset # # # CPU # CONFIG_CPU_ADDR_BITS=36 CONFIG_XIP_ROM_SIZE=0x10000 CONFIG_DIMM_SUPPORT=0x0004 # CONFIG_UDELAY_IO is not set CONFIG_HAVE_INIT_TIMER=y CONFIG_CPU_INTEL_MODEL_68X=y CONFIG_CPU_INTEL_SOCKET_FC_PGA370=y # CONFIG_SSE2 is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_CALIBRATE_WITH_IO is not set CONFIG_CACHE_AS_RAM=y CONFIG_MMX=y CONFIG_SSE=y # # Northbridge # CONFIG_VIDEO_MB=1 # CONFIG_CONSOLE_VGA_MULTI is not set CONFIG_NORTHBRIDGE_INTEL_I82810=y # CONFIG_I810_VIDEO_MB_OFF is not set # CONFIG_I810_VIDEO_MB_512KB is not set CONFIG_I810_VIDEO_MB_1MB=y # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_I82801BX=y # # Super I/O # CONFIG_SUPERIO_SMSC_SMSCSUPERIO=y # # Devices # CONFIG_VGA_BRIDGE_SETUP=y CONFIG_VGA_ROM_RUN=y CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_AGP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # # Embedded Controllers # # # Generic Drivers # # CONFIG_DRIVERS_OXFORD_OXPCIE is not set # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_PCI_BUS_SEGN_BITS=0 # CONFIG_MMCONF_SUPPORT is not set # # Console # CONFIG_CONSOLE_SERIAL_COM1=y # CONFIG_CONSOLE_SERIAL_COM2 is not set # CONFIG_CONSOLE_SERIAL_COM3 is not set # CONFIG_CONSOLE_SERIAL_COM4 is not set CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_HAVE_USBDEBUG is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CONSOLE_LOGBUF is not set # CONFIG_NO_POST is not set CONFIG_POST_PORT=0x80 CONFIG_HAVE_UART_IO_MAPPED=y # CONFIG_HAVE_UART_MEMORY_MAPPED is not set # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_HAVE_ACPI_SLIC is not set CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_MAINBOARD_RESOURCES=y # CONFIG_HAVE_OPTION_TABLE is not set # CONFIG_PIRQ_ROUTE is not set # CONFIG_HAVE_SMI_HANDLER is not set # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_USE_WATCHDOG_ON_BOOT=y # CONFIG_VGA is not set CONFIG_GFXUMA=y CONFIG_HAVE_PIRQ_TABLE=y # CONFIG_GENERATE_ACPI_TABLES is not set # CONFIG_GENERATE_MP_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y # # System tables # CONFIG_WRITE_HIGH_TABLES=y CONFIG_MULTIBOOT=y # # Payload # CONFIG_PAYLOAD_NONE=y # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_SEABIOS is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set # # VGA BIOS # # # Display # # CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set # CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set # # Debugging # CONFIG_GDB_STUB=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_REALMODE_DEBUG is not set # CONFIG_LLSHELL is not set # CONFIG_TRACE is not set # CONFIG_AP_CODE_IN_CAR is not set # CONFIG_RAMINIT_SYSINFO is not set # CONFIG_ENABLE_APIC_EXT_ID is not set # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # # Deprecated # # CONFIG_BOARD_HAS_HARD_RESET is not set # CONFIG_BOARD_HAS_FADT is not set # CONFIG_HAVE_BUS_CONFIG is not set # CONFIG_PCIE_TUNING is not set CONFIG_ID_SECTION_OFFSET=0x80 and as an another test, I got the following messages with the .config file after that(this time the latest post code is 0x39): coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 17:57:43 IRST 2012 starting... Testing DRAM : 02000000 - 10000000 DRAM fill: 0x02000000-0x10000000 0ee00000 coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 17:57:43 IRST 2012 starting... Testing DRAM : 02000000 - 10000000 DRAM fill: 0x02000000-0x10000000 10000000 DRAM filled DRAM verify: 0x02000000-0x10000000 10000000 DRAM range verified. Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. /root/bios/coreboot> cat ./.config # # Automatically generated make config: don't edit # coreboot version: 4.0-1959-g950f20a-dirty # Tue Feb 7 17:57:37 2012 # # # General setup # # CONFIG_EXPERT is not set CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_SCANBUILD_ENABLE is not set # CONFIG_CCACHE is not set # CONFIG_USE_OPTION_TABLE is not set # CONFIG_COMPRESS_RAMSTAGE is not set # CONFIG_INCLUDE_CONFIG_FILE is not set # # Mainboard # # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_ADVANTECH is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARIMA is not set # CONFIG_VENDOR_ARTEC_GROUP is not set # CONFIG_VENDOR_ASI is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AXUS is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_DELL is not set # CONFIG_VENDOR_DIGITAL_LOGIC is not set # CONFIG_VENDOR_EAGLELION is not set # CONFIG_VENDOR_ECS is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IBM is not set # CONFIG_VENDOR_IEI is not set CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_IWAVE is not set # CONFIG_VENDOR_IWILL is not set # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LANNER is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set # CONFIG_VENDOR_NEWISYS is not set # CONFIG_VENDOR_NOKIA is not set # CONFIG_VENDOR_NVIDIA is not set # CONFIG_VENDOR_PC_ENGINES is not set # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TECHNEXION is not set # CONFIG_VENDOR_TECHNOLOGIC is not set # CONFIG_VENDOR_TELEVIDEO is not set # CONFIG_VENDOR_THOMSON is not set # CONFIG_VENDOR_TRAVERSE is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/d810e2cb" CONFIG_MAINBOARD_PART_NUMBER="D810E2CB" CONFIG_IRQ_SLOT_COUNT=7 CONFIG_MAINBOARD_VENDOR="Intel" CONFIG_MAX_CPUS=1 CONFIG_MAX_PHYSICAL_CPUS=1 CONFIG_RAMTOP=0x200000 CONFIG_HEAP_SIZE=0x4000 CONFIG_RAMBASE=0x100000 CONFIG_VGA_BIOS_ID="8086,7121" CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0 CONFIG_SERIAL_CPU_INIT=y CONFIG_ACPI_SSDTX_NUM=0 # CONFIG_VGA_BIOS is not set CONFIG_STACK_SIZE=0x8000 # CONFIG_DRIVERS_PS2_KEYBOARD is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_CONSOLE_POST is not set # CONFIG_PCI_64BIT_PREF_MEM is not set # CONFIG_MMCONF_SUPPORT_DEFAULT is not set CONFIG_BOARD_INTEL_D810E2CB=y # CONFIG_BOARD_INTEL_D945GCLF is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_JARRELL is not set # CONFIG_BOARD_INTEL_MTARVON is not set # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_XE7501DEVKIT is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_IOAPIC is not set CONFIG_SMP=y CONFIG_TTYS0_BAUD=115200 CONFIG_TTYS0_BASE=0x3f8 CONFIG_TTYS0_LCS=3 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 CONFIG_CONSOLE_SERIAL8250=y # CONFIG_PCI_ROM_RUN is not set # CONFIG_USBDEBUG is not set CONFIG_VAR_MTRR_HOLE=y # CONFIG_LIFT_BSP_APIC_ID is not set # CONFIG_WAIT_BEFORE_CPUS_INIT is not set # CONFIG_K8_REV_F_SUPPORT is not set CONFIG_BOARD_ROMSIZE_KB_512=y # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set CONFIG_COREBOOT_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set CONFIG_COREBOOT_ROMSIZE_KB=256 CONFIG_ROM_SIZE=0x40000 CONFIG_ARCH_X86=y # # Architecture (x86) # # CONFIG_AP_IN_SIPI_WAIT is not set CONFIG_ROMBASE=0xffff0000 CONFIG_MAX_REBOOT_CNT=3 CONFIG_X86_BOOTBLOCK_SIMPLE=y # CONFIG_X86_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_UPDATE_IMAGE is not set # CONFIG_ROMCC is not set CONFIG_PC80_SYSTEM=y # CONFIG_HAVE_CMOS_DEFAULT is not set # CONFIG_BIG_ENDIAN is not set CONFIG_LITTLE_ENDIAN=y # # Chipset # # # CPU # CONFIG_CPU_ADDR_BITS=36 CONFIG_XIP_ROM_SIZE=0x10000 CONFIG_DIMM_SUPPORT=0x0004 # CONFIG_UDELAY_IO is not set CONFIG_HAVE_INIT_TIMER=y CONFIG_CPU_INTEL_MODEL_68X=y CONFIG_CPU_INTEL_SOCKET_FC_PGA370=y # CONFIG_SSE2 is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_CALIBRATE_WITH_IO is not set CONFIG_CACHE_AS_RAM=y CONFIG_MMX=y CONFIG_SSE=y # # Northbridge # CONFIG_VIDEO_MB=1 # CONFIG_CONSOLE_VGA_MULTI is not set CONFIG_NORTHBRIDGE_INTEL_I82810=y # CONFIG_I810_VIDEO_MB_OFF is not set # CONFIG_I810_VIDEO_MB_512KB is not set CONFIG_I810_VIDEO_MB_1MB=y # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_I82801BX=y # # Super I/O # CONFIG_SUPERIO_SMSC_SMSCSUPERIO=y # # Devices # # CONFIG_VGA_BRIDGE_SETUP is not set # CONFIG_VGA_ROM_RUN is not set # CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set # CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_AGP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # # Embedded Controllers # # # Generic Drivers # # CONFIG_DRIVERS_OXFORD_OXPCIE is not set # CONFIG_DRIVERS_SIL_3114 is not set CONFIG_PCI_BUS_SEGN_BITS=0 # CONFIG_MMCONF_SUPPORT is not set # # Console # CONFIG_CONSOLE_SERIAL_COM1=y # CONFIG_CONSOLE_SERIAL_COM2 is not set # CONFIG_CONSOLE_SERIAL_COM3 is not set # CONFIG_CONSOLE_SERIAL_COM4 is not set CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_57600 is not set # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_HAVE_USBDEBUG is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set # CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CONSOLE_LOGBUF is not set # CONFIG_NO_POST is not set CONFIG_POST_PORT=0x80 CONFIG_HAVE_UART_IO_MAPPED=y # CONFIG_HAVE_UART_MEMORY_MAPPED is not set # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_HAVE_ACPI_SLIC is not set CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_MAINBOARD_RESOURCES=y # CONFIG_HAVE_OPTION_TABLE is not set # CONFIG_PIRQ_ROUTE is not set # CONFIG_HAVE_SMI_HANDLER is not set # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_USE_WATCHDOG_ON_BOOT=y # CONFIG_VGA is not set CONFIG_GFXUMA=y CONFIG_HAVE_PIRQ_TABLE=y # CONFIG_GENERATE_ACPI_TABLES is not set # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_SMBIOS_TABLES is not set # # System tables # # CONFIG_WRITE_HIGH_TABLES is not set # CONFIG_MULTIBOOT is not set # # Payload # CONFIG_PAYLOAD_NONE=y # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_SEABIOS is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set # # VGA BIOS # # # Debugging # # CONFIG_GDB_STUB is not set CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_LLSHELL is not set # CONFIG_TRACE is not set # CONFIG_AP_CODE_IN_CAR is not set # CONFIG_RAMINIT_SYSINFO is not set # CONFIG_ENABLE_APIC_EXT_ID is not set # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # # Deprecated # # CONFIG_BOARD_HAS_HARD_RESET is not set # CONFIG_BOARD_HAS_FADT is not set # CONFIG_HAVE_BUS_CONFIG is not set # CONFIG_PCIE_TUNING is not set CONFIG_ID_SECTION_OFFSET=0x80 On Mon, Feb 6, 2012 at 10:51 PM, Ky?sti M?lkki wrote: > On Mon, 2012-02-06 at 19:17 +0330, ali hagigat wrote: >> I can verify that by the assembly code i have. writing to any memory >> location and reading that. Also I tested it by ram_check() >> in Coreboot. Both are correct. >> >> The last post codes are 0x39, 0x80 and Coreboot seems to stop! >> > > Hi > > 0x80 seems like a reasonable POST from the very beginning of stage > coreboot_ram. Continue your work with src/boot/hardwaremain.c; figure > out whether you only lose serial communication or if the execution > actually halts. > > Seems there is a case or two of possible infinite while() loops within > the uart8250 serial console code. This is a wild guess, but the uart > could end up in a bad state if transmit buffers are non-empty while > divisors are programmed etc. Maybe raise the speed to more common and > tested 115200. > > Regards, > KM > > From kyosti.malkki at gmail.com Tue Feb 7 15:57:50 2012 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Tue, 07 Feb 2012 16:57:50 +0200 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> Message-ID: <1328626670.5785.138.camel@obelix> On Tue, 2012-02-07 at 18:08 +0330, ali hagigat wrote: > Thank you, Ky?sti, for the reply. I tested the modified Coreboot by > 115200 Buad rate, again the same message(latest post code seems to be > 0x11)(modified Coreboot contains sdram_enable() changed and some > fuction calls was commented out in romstage.c and i am using > build/coreboot.rom as the final image on ROM chip): > > coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 17:40:50 IRST 2012 starting... > Testing DRAM : 02000000 - 10000000 > DRAM fill: 0x02000000-0x10000000 > 10000000 > DRAM filled > DRAM verify: 0x02000000-0x10000000 > 10000000 > DRAM range verified. > Done. > Loading image. > Searching for fallback/coreboot_ram > Check fallback/romstage > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 > lzma: Decoding error = 1 > FATAL: Essential component is missing. Your ram_check() still does not cover 1M-3M range. Failure to decompress coreboot_ram (lzma decoding error) screams a problem with initialising RAM. KM From hagigatali at gmail.com Tue Feb 7 16:02:37 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 18:32:37 +0330 Subject: [coreboot] I can not add FILO as a payload In-Reply-To: <20120207141521.5164.qmail@stuge.se> References: <20120207141521.5164.qmail@stuge.se> Message-ID: Hello Peter. Thank you very much for the reply. I have just copied part of README file from the Coreboot project: /root> cat ~/bios/coreboot/payloads/filo/README BUG REPORTING If you have problem with FILO, set DEBUG_ALL in Config and send its console output to the coreboot mailinglist at . So i did: /root/bios/coreboot/payloads/filo> make Found Libpayload /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/ipchecksum.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'dump_super': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:404:33: error: 'struct ext2_super_block' has no member named 's_log_frag_size' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:406:26: error: 'struct ext2_super_block' has no member named 's_frags_per_group' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: At top level: /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:411:24: warning: 'struct ext2_group_desc' declared inside parameter list [enabled by default] /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:411:24: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'dump_group_desc': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:414:35: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:415:35: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:416:34: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:417:32: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:418:34: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:419:32: error: dereferencing pointer to incomplete type /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'ext4fs_block_map': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:640:18: error: conflicting types for 'i' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:637:7: note: previous declaration of 'i' was here /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c: In function 'ext2fs_dir': /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:861:23: warning: passing argument 1 of 'dump_group_desc' from incompatible pointer type [enabled by default] /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:411:1: note: expected 'struct ext2_group_desc *' but argument is of type 'struct ext2_group_desc *' /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:877:3: error: 'gdp' undeclared (first use in this function) /root/bios/coreboot/payloads/filo/fs/fsys_ext2fs.c:877:3: note: each undeclared identifier is reported only once for each function it appears in make: *** [/root/bios/coreboot/payloads/filo/build/fs/fsys_ext2fs.o] Error 1 I lack time but I will try to get it fixed. I hope so. Regards. On Tue, Feb 7, 2012 at 5:45 PM, Peter Stuge wrote: > ali hagigat wrote: >> cd payloads/libpayload/ >> /root/bios/coreboot/payloads/libpayload> make defconfig >> /root/bios/coreboot/payloads/libpayload> make >> /root/bios/coreboot/payloads/libpayload> make DESTDIR=../filo/build install >> /root/bios/coreboot/payloads/libpayload> cd ../filo >> /root/bios/coreboot/payloads/filo> make menuconfig > > So far so good. > > >> /root/bios/coreboot/payloads/filo> make > .. >> ? CC ? ? ?build/fs/cbfs.o >> /root/bios/coreboot/payloads/filo/fs/cbfs.c:113:20: error: conflicting types for 'cbfs_find_file' >> /root/bios/coreboot/payloads/filo/build/libpayload/include/cbfs_core.h:175:7: note: previous declaration of 'cbfs_find_file' was here >> make: *** [/root/bios/coreboot/payloads/filo/build/fs/cbfs.o] Error 1 > > .. >> What caused the problem then? > > Look more closely at the error message. It is actually a very clear > error message. Then you look at the source code pointed to by the > error message. > > This process is the *very first* problem resolution process that > *every* programmer in this world encounters. It is amazing that you > seem to not know it. :\ > > > FILO is probably not quite up to date with the latest libpayload API, > so you now have an opportunity to fix this and make FILO better for > everyone. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From hagigatali at gmail.com Tue Feb 7 16:21:08 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 18:51:08 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <1328626670.5785.138.camel@obelix> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <1328626670.5785.138.camel@obelix> Message-ID: I changed romstage .c as follows: void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); //enable_smbus(); //dump_spd_registers(); //sdram_set_registers(); //sdram_set_spd_registers(); sdram_enable(); ram_check(0x00100000, 0x00900000); } This time i do ram_check between 1M to 3M, here is the serial port output: coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 18:39:18 IRST 2012 starting... Testing DRAM : 00100000 - 00900000 DRAM fill: 0x00100000-0x00900000 00900000 DRAM filled DRAM verify: 0x00100000-0x00900000 00900000 DRAM range verified. Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. I only changed sdram_enable() and some commented function calls and there is no payload. How these changes can effect Coreboot? My guess is that the problem occurs inside this function: cbfs_and_run_core It is located in: ~/bios/coreboot/src/arch/x86/lib/cbfs_and_run.c When it wants to do a jump inside cbfs_and_run_core(), the processor halts some how. Regards On Tue, Feb 7, 2012 at 6:27 PM, Ky?sti M?lkki wrote: > On Tue, 2012-02-07 at 18:08 +0330, ali hagigat wrote: >> Thank you, Ky?sti, for the reply. I tested the modified Coreboot by >> 115200 Buad rate, again the same message(latest post code seems to be >> 0x11)(modified Coreboot contains sdram_enable() changed and some >> fuction calls was commented out in romstage.c ?and i am using >> build/coreboot.rom as the final image on ROM chip): >> >> coreboot-4.0-1959-g950f20a-dirty Tue Feb ?7 17:40:50 IRST 2012 starting... >> Testing DRAM : 02000000 - 10000000 >> DRAM fill: 0x02000000-0x10000000 >> 10000000 >> DRAM filled >> DRAM verify: 0x02000000-0x10000000 >> 10000000 >> DRAM range verified. >> Done. >> Loading image. >> Searching for fallback/coreboot_ram >> Check fallback/romstage >> Check fallback/coreboot_ram >> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 >> lzma: Decoding error = 1 >> FATAL: Essential component is missing. > > Your ram_check() still does not cover 1M-3M range. Failure to decompress > coreboot_ram (lzma decoding error) screams a problem with initialising > RAM. > > KM > From hagigatali at gmail.com Tue Feb 7 16:25:13 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 18:55:13 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <4F306454.6070405@assembler.cz> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <4F306454.6070405@assembler.cz> Message-ID: Thank you Rudolf for the reply. 1M to 3M is OK please look at the serial port output: coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 18:39:18 IRST 2012 starting... Testing DRAM : 00100000 - 00900000 DRAM fill: 0x00100000-0x00900000 00900000 DRAM filled DRAM verify: 0x00100000-0x00900000 00900000 DRAM range verified. Done. Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek wrote: >> Seems there is a case or two of possible infinite while() loops within >> the uart8250 serial console code. This is a wild guess, but the uart > > > Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is > always better to boot than to have perfect serial output ;) > > But in this case I would think memory is not 100% OK. Worth to check if > 1M->3M is OK (this is where coreboot ramstage goes) > > Thanks > Rudolf > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From peter at stuge.se Tue Feb 7 16:28:05 2012 From: peter at stuge.se (Peter Stuge) Date: Tue, 7 Feb 2012 16:28:05 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <1328626670.5785.138.camel@obelix> Message-ID: <20120207152805.11373.qmail@stuge.se> ali hagigat wrote: > Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 > Stage: done loading. > Jumping to image. .. > When it wants to do a jump inside cbfs_and_run_core(), the processor > halts some how. RAM is not initialized correctly. //Peter From r.marek at assembler.cz Tue Feb 7 16:36:28 2012 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 07 Feb 2012 16:36:28 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <4F306454.6070405@assembler.cz> Message-ID: <4F3144FC.3070004@assembler.cz> Hi, > DRAM range verified. Well the check is quite simple maybe it works for simple cases and fails for real usage. I guess you need to port something like http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. All it sounds like raminit problem. Also I don't like couple of things btw. You never showed any of your code. You only ask sometimes too simple question without bothering too much with them. Please try hard before asking and try to learn new stuff. You have chosen quite difficult area, maybe you should try some simpler stuff first to get in touch better with C and common toolchains and after that get back here in here. Thanks Rudolf > Done. > Loading image. > Searching for fallback/coreboot_ram > Check fallback/romstage > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 > Stage: done loading. > Jumping to image. > > > On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek wrote: >>> Seems there is a case or two of possible infinite while() loops within >>> the uart8250 serial console code. This is a wild guess, but the uart >> >> >> Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is >> always better to boot than to have perfect serial output ;) >> >> But in this case I would think memory is not 100% OK. Worth to check if >> 1M->3M is OK (this is where coreboot ramstage goes) >> >> Thanks >> Rudolf >> >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot From hagigatali at gmail.com Tue Feb 7 16:42:05 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 19:12:05 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <20120207152805.11373.qmail@stuge.se> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <1328626670.5785.138.camel@obelix> <20120207152805.11373.qmail@stuge.se> Message-ID: Peter, It is an easy answer to say that RAM is not initialized correctly! While I am pretty sure that RAM is OK, I have an assembly language which can verify that. Peter, you do not make the problem clear. The problem is that the registers of RAM controller are initialized with some correct values, but the Intel board had 82810 as its GMCH. My GMCH is 82815. I guess Coreboot at some point extracts some information from the config registers of GMCH and sets some variables and this is exactly the point which the problem occurs. I do not have enough information about the source code of Coreboot but logically where Coreboot is specifying the top of memory? Coreboot needs to know the size of memory, right? Where it is specified? Does my words make sense? Regards On Tue, Feb 7, 2012 at 6:58 PM, Peter Stuge wrote: > ali hagigat wrote: >> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 >> Stage: done loading. >> Jumping to image. > .. >> When it wants to do a jump inside cbfs_and_run_core(), the processor >> halts some how. > > RAM is not initialized correctly. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot From svens at stackframe.org Tue Feb 7 16:42:17 2012 From: svens at stackframe.org (Sven Schnelle) Date: Tue, 07 Feb 2012 16:42:17 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <1328626670.5785.138.camel@obelix> Message-ID: <4F314659.8030102@stackframe.org> On 02/07/2012 04:21 PM, ali hagigat wrote: > This time i do ram_check between 1M to 3M, here is the serial port output: > > coreboot-4.0-1959-g950f20a-dirty Tue Feb 7 18:39:18 IRST 2012 starting... > Testing DRAM : 00100000 - 00900000 > DRAM fill: 0x00100000-0x00900000 > 00900000 > DRAM filled > DRAM verify: 0x00100000-0x00900000 > 00900000 > DRAM range verified. > Done. > Loading image. > Searching for fallback/coreboot_ram > Check fallback/romstage > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 > Stage: done loading. > Jumping to image. > > I only changed sdram_enable() and some commented function calls and > there is no payload. How these changes can effect Coreboot? > > My guess is that the problem occurs inside this function: > cbfs_and_run_core > > It is located in: > ~/bios/coreboot/src/arch/x86/lib/cbfs_and_run.c > > When it wants to do a jump inside cbfs_and_run_core(), the processor > halts some how. I'd bet your RAM setup isn't working. In almost all cases i have seen coreboot hanging it was caused by non working RAM. You should test all available RAM, not only parts of it. And that ram_check() succeeds, doesn't mean that your RAM setup is working properly. It just means that nothing obvious is wrong. Regards Sven From hagigatali at gmail.com Tue Feb 7 16:59:40 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 7 Feb 2012 19:29:40 +0330 Subject: [coreboot] How to port core boot In-Reply-To: <4F3144FC.3070004@assembler.cz> References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <4F306454.6070405@assembler.cz> <4F3144FC.3070004@assembler.cz> Message-ID: Rudolf, When i started to study Coreboot and BIOS , people always made me confused by nonsense words. I asked some useful questions but interpreted as simple.(now I have developed a project which can drive RAM, serial port and hard disk) The managers of this project even do not accept their own mistakes. Now FILO can not be compiled and when i report it as the README of the filo is saying, the manager emails me and tells me that you are not a programmer!! I thought i would be encouraged for that by a thank you. When i ask a question nobody talks about the details of the logic behind that except one person, Ky?sti M?lkki. Hey folks, what is going on here? If you are a master of Coreboot why we have unrelated simple answers? On 2/7/12, Rudolf Marek wrote: > Hi, > >> DRAM range verified. > > Well the check is quite simple maybe it works for simple cases and fails for > real usage. I guess you need to port something like > http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. > All > it sounds like raminit problem. > > Also I don't like couple of things btw. You never showed any of your code. > You > only ask sometimes too simple question without bothering too much with them. > Please try hard before asking and try to learn new stuff. You have chosen > quite > difficult area, maybe you should try some simpler stuff first to get in > touch > better with C and common toolchains and after that get back here in here. > > Thanks > Rudolf > > >> Done. >> Loading image. >> Searching for fallback/coreboot_ram >> Check fallback/romstage >> Check fallback/coreboot_ram >> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ >> 0x100000 >> Stage: done loading. >> Jumping to image. >> >> >> On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek wrote: >>>> Seems there is a case or two of possible infinite while() loops within >>>> the uart8250 serial console code. This is a wild guess, but the uart >>> >>> >>> Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It >>> is >>> always better to boot than to have perfect serial output ;) >>> >>> But in this case I would think memory is not 100% OK. Worth to check if >>> 1M->3M is OK (this is where coreboot ramstage goes) >>> >>> Thanks >>> Rudolf >>> >>> >>> -- >>> coreboot mailing list: coreboot at coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot > From rminnich at gmail.com Tue Feb 7 17:15:40 2012 From: rminnich at gmail.com (ron minnich) Date: Tue, 7 Feb 2012 08:15:40 -0800 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <1328626670.5785.138.camel@obelix> Message-ID: Ali, you've changed ram setup code. Ram setup is probably the single hardest thing to get right. It can take a year. You need to let people see your code before any one can help you. It's very common for a new port to pass a ram test and fail in actual use. Just about everyone who has done a port has been in this situation. But, all that said, you need to let people see your ram code or we can not help you. ron From peter at stuge.se Tue Feb 7 17:21:45 2012 From: peter at stuge.se (Peter Stuge) Date: Tue, 7 Feb 2012 17:21:45 +0100 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <4F306454.6070405@assembler.cz> <4F3144FC.3070004@assembler.cz> Message-ID: <20120207162145.15422.qmail@stuge.se> ali hagigat wrote: > The managers of this project even do not accept their own mistakes. > Now FILO can not be compiled and when i report it as the README of the > filo is saying, the manager emails me and tells me that you are not a > programmer!! I'm not a manager. I'm a contributor in an open source project. I never said that you are not a programmer, but it does seem like very basic programming concepts and practises are foreign to you. You encountered a compile time error and reported a problem citing the instructions for run time errors. It is clear from the instructions that they apply only to run time errors. > I thought i would be encouraged for that by a thank you. Create a patch to fix the problem. You sent a compiler error message and and a very simple question "what is the problem" when the error message you sent already describes the problem perfectly. If you instead fix a problem that you discover, and push a perfect commit to Gerrit, you can be sure that you will improve your reputation, and quite likely also generate some gratitude. But ultimately, it is not the task of anyone in the coreboot community to encourage you to contribute. You need to be contributing because you want to, or everyone will just suffer. If you do not want to contribute that is perfectly fine too. It would be unfortunate that the project has to cope without your skills, but I guess it will work out somehow in the end. > When i ask a question nobody talks about the details of the logic > behind that except one person, Ky?sti M?lkki. The logic is obvious already from reading debug messages, and besides that you even have access to the source code. coreboot sets up RAM, decompresses ramstage into RAM, and jumps. As many have pointed out already, the jump does not fail if RAM is OK. > Hey folks, what is going on here? If you are a master of Coreboot > why we have unrelated simple answers? Because of too basic questions. //Peter From oneingray at gmail.com Tue Feb 7 17:27:49 2012 From: oneingray at gmail.com (Ivan Shmakov) Date: Tue, 07 Feb 2012 23:27:49 +0700 Subject: [coreboot] Coreboot + SeaBIOS on GA-M52S-S3P? References: <86ty33hnyk.fsf@gray.siamics.net> <86pqdrhmkj.fsf@gray.siamics.net> <864nv3gwe5.fsf@gray.siamics.net> <861uq7eztt.fsf@gray.siamics.net> <86wr7zdk0t.fsf_-_@gray.siamics.net> Message-ID: <86ty32d2wq.fsf@gray.siamics.net> I wonder, did anyone try Coreboot and SeaBIOS on Gigabyte's GA-M52S-S3P? I'm mainly interested in booting Linux 2.6-based GNU system via GRUB 2 from a SATA HDD (with GPT), but I'd like to have other boot devices (floppy and DVD drives, USB Flash) and systems supported as well. One more issue is that the BIOS IC (labelled MX 25L4005AM2C) is soldered to the board. I wonder, what'd be the recovery procedure should the newly uploaded firmware fail to boot? TIA. The backstory is as follows. Suddenly, the vendor's BIOS has decided that it needs a backup. Without hesitation, it choose one of the HDD's attached, and wrote its copy there, reserving some 2113 sectors at its tail as a ?Host Protected Area? (HPA.) Effectively, this has invalidated the drive's GPT, rendering the system unbootable. Seemingly, no data (apart from the backup GPT) was lost, but I'd like to avoid the surprises like this in the future. As I was unable to find the relevant BIOS configuration software for AwardBIOS, I'm now looking if I should abandon such a misbehaved variety of proprietary firmware completely for something free. -- FSF associate member #7257 From gerrit at coreboot.org Tue Feb 7 18:30:36 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 18:30:36 +0100 Subject: [coreboot] Patch merged into coreboot/master: 595df77 libpayload: Force checking all EHCI ports on power-on References: Message-ID: the following patch was just integrated into master: commit 595df777bfaf2fc07a394233a6e770737b78806e Author: Patrick Georgi Date: Tue Jan 31 14:42:47 2012 +0100 libpayload: Force checking all EHCI ports on power-on EHCI port status reporting isn't very consistent on power-on, so just looking for devices on all ports is the safest way to find everything. Change-Id: I26b4305016f0bed1d2c1b5cffc59d5813fa1cbbb Signed-off-by: Patrick Georgi See http://review.coreboot.org/594 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 18:30:46 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 18:30:46 +0100 Subject: [coreboot] Patch merged into coreboot/master: aa4428b libpayload: Remove workaround for bitfield management in EHCI driver References: Message-ID: the following patch was just integrated into master: commit aa4428b722849dc772004d4d0ab10c035b00cf3c Author: Patrick Georgi Date: Tue Jan 31 14:48:05 2012 +0100 libpayload: Remove workaround for bitfield management in EHCI driver We don't use bitfields anymore. Change-Id: I25ceec2024f659612871bcfe5f98df3a10789055 Signed-off-by: Patrick Georgi See http://review.coreboot.org/595 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 19:42:44 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 19:42:44 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3b31dca Delete hard-coded driver includes References: Message-ID: the following patch was just integrated into master: commit 3b31dcaa10f1db54a1a2b15728011a47e789353f Author: Ky?sti M?lkki Date: Tue Feb 7 14:59:07 2012 +0200 Delete hard-coded driver includes Driver components are conditionally included in the build using the Kconfig options. Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Tue Feb 7 16:23:38 2012, giving +1 Reviewed-By: Stefan Reinauer at Tue Feb 7 19:42:41 2012, giving +2 See http://review.coreboot.org/610 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 20:04:33 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Feb 2012 20:04:33 +0100 Subject: [coreboot] New patch to review for coreboot: 7ef5336 Don't loop infinitely long on serial comm failures References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/611 -gerrit commit 7ef53364ae202363e4260ffc8e306a0ae10db0c6 Author: Ky?sti M?lkki Date: Tue Feb 7 20:50:22 2012 +0200 Don't loop infinitely long on serial comm failures If serial uart (8250/16x50) takes abnormally long to respond, give up on logging to serial console and instead let the system boot. Also reference bit in LSR register with correct name. Change-Id: I3796efc3e8690425f04a130af4bc99541b64d335 Signed-off-by: Ky?sti M?lkki --- src/lib/uart8250.c | 31 ++++++++++++++++++++++--------- 1 files changed, 22 insertions(+), 9 deletions(-) diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index b224671..fe8ed70 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -29,21 +29,30 @@ /* Should support 8250, 16450, 16550, 16550A type UARTs */ +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + static inline int uart8250_can_tx_byte(unsigned base_port) { - return inb(base_port + UART_LSR) & UART_MSR_DSR; + return inb(base_port + UART_LSR) & UART_LSR_THRE; } static inline void uart8250_wait_to_tx_byte(unsigned base_port) { - while(!uart8250_can_tx_byte(base_port)) - ; + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_tx_byte(base_port)); } static inline void uart8250_wait_until_sent(unsigned base_port) { - while(!(inb(base_port + UART_LSR) & UART_LSR_TEMT)) - ; + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); } void uart8250_tx_byte(unsigned base_port, unsigned char data) @@ -64,9 +73,13 @@ int uart8250_can_rx_byte(unsigned base_port) unsigned char uart8250_rx_byte(unsigned base_port) { - while(!uart8250_can_rx_byte(base_port)) - ; - return inb(base_port + UART_RBR); + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_rx_byte(base_port)); + + if (i) + return inb(base_port + UART_RBR); + else + return 0x0; } void uart8250_init(unsigned base_port, unsigned divisor) @@ -83,7 +96,7 @@ void uart8250_init(unsigned base_port, unsigned divisor) /* DLAB on */ outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); - /* Set Baud Rate Divisor. 12 ==> 115200 Baud */ + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ outb(divisor & 0xFF, base_port + UART_DLL); outb((divisor >> 8) & 0xFF, base_port + UART_DLM); From gerrit at coreboot.org Tue Feb 7 20:37:22 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 20:37:22 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7ef5336 Don't loop infinitely long on serial comm failures References: Message-ID: the following patch was just integrated into master: commit 7ef53364ae202363e4260ffc8e306a0ae10db0c6 Author: Ky?sti M?lkki Date: Tue Feb 7 20:50:22 2012 +0200 Don't loop infinitely long on serial comm failures If serial uart (8250/16x50) takes abnormally long to respond, give up on logging to serial console and instead let the system boot. Also reference bit in LSR register with correct name. Change-Id: I3796efc3e8690425f04a130af4bc99541b64d335 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Tue Feb 7 20:27:45 2012, giving +1 Reviewed-By: Peter Stuge at Tue Feb 7 20:37:20 2012, giving +2 See http://review.coreboot.org/611 for details. -gerrit From marcj303 at gmail.com Tue Feb 7 21:18:11 2012 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 7 Feb 2012 13:18:11 -0700 Subject: [coreboot] Coreboot + SeaBIOS on GA-M52S-S3P? In-Reply-To: <86ty32d2wq.fsf@gray.siamics.net> References: <86ty33hnyk.fsf@gray.siamics.net> <86pqdrhmkj.fsf@gray.siamics.net> <864nv3gwe5.fsf@gray.siamics.net> <861uq7eztt.fsf@gray.siamics.net> <86wr7zdk0t.fsf_-_@gray.siamics.net> <86ty32d2wq.fsf@gray.siamics.net> Message-ID: On Tue, Feb 7, 2012 at 9:27 AM, Ivan Shmakov wrote: > ? ? ? ?I wonder, did anyone try Coreboot and SeaBIOS on Gigabyte's > ? ? ? ?GA-M52S-S3P? > The nvidia chipset is the biggest challenge. I don't know how close it is to the nvida support in coreboot. > ? ? ? ?I'm mainly interested in booting Linux 2.6-based GNU system via > ? ? ? ?GRUB 2 from a SATA HDD (with GPT), but I'd like to have other > ? ? ? ?boot devices (floppy and DVD drives, USB Flash) and systems > ? ? ? ?supported as well. This is a typical coreboot + seabios solution. > > ? ? ? ?One more issue is that the BIOS IC (labelled MX 25L4005AM2C) is > ? ? ? ?soldered to the board. ?I wonder, what'd be the recovery > ? ? ? ?procedure should the newly uploaded firmware fail to boot? There are a number of ways to handle recovery. Please see this page for more info: http://www.coreboot.org/Developer_Manual/Tools#External_EPROM.2FFlash_programmer_that_can_program_the_flash_chip_on_your_motherboard Marc > > ? ? ? ?TIA. > > ? ?The backstory is as follows. ?Suddenly, the vendor's BIOS has > ? ?decided that it needs a backup. ?Without hesitation, it choose one > ? ?of the HDD's attached, and wrote its copy there, reserving some 2113 > ? ?sectors at its tail as a ?Host Protected Area? (HPA.) ?Effectively, > ? ?this has invalidated the drive's GPT, rendering the system > ? ?unbootable. ?Seemingly, no data (apart from the backup GPT) was > ? ?lost, but I'd like to avoid the surprises like this in the future. > > ? ?As I was unable to find the relevant BIOS configuration software for > ? ?AwardBIOS, I'm now looking if I should abandon such a misbehaved > ? ?variety of proprietary firmware completely for something free. > > -- > FSF associate member #7257 > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com From gerrit at coreboot.org Tue Feb 7 22:34:44 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Tue, 7 Feb 2012 22:34:44 +0100 Subject: [coreboot] Patch merged into coreboot/master: 6ec51f8 romcc: kill gcc warnings and .gitignore generated files References: Message-ID: the following patch was just integrated into master: commit 6ec51f82110a88ffd5443c5fa6b8aa9ebad357b9 Author: Bernhard Urban Date: Wed Feb 1 16:30:30 2012 +0100 romcc: kill gcc warnings and .gitignore generated files don't remove calls to `flatten()' and `correct_coalesce_conflicts()', since they (probably) have side effects. Change-Id: I78fc4163b3f5f1f5f3c5153f9559c22e11e8344d Signed-off-by: Bernhard Urban Build-Tested: build bot (Jenkins) at Wed Feb 1 16:50:03 2012, giving +1 Reviewed-By: Stefan Reinauer at Tue Feb 7 22:34:41 2012, giving +2 See http://review.coreboot.org/605 for details. -gerrit From gerrit at coreboot.org Tue Feb 7 22:59:32 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 7 Feb 2012 22:59:32 +0100 Subject: [coreboot] New patch to review for coreboot: 384c255 Remove no-op Makefiles under mainboard directory References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/612 -gerrit commit 384c255400a042a075692c71e33e3de5718ec6c0 Author: Ky?sti M?lkki Date: Tue Feb 7 23:50:17 2012 +0200 Remove no-op Makefiles under mainboard directory Patch removes following files: src/mainboard/amd/serengeti_cheetah/Makefile.inc src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc src/mainboard/broadcom/blast/Makefile.inc src/mainboard/hp/dl145_g1/Makefile.inc src/mainboard/msi/ms9282/Makefile.inc src/mainboard/supermicro/h8dme/Makefile.inc src/mainboard/tyan/s2881/Makefile.inc src/mainboard/tyan/s2892/Makefile.inc src/mainboard/via/epia-m700/Makefile.inc Change-Id: I020776313abff1772be38afc896af51ca5ab6453 Signed-off-by: Ky?sti M?lkki --- src/mainboard/amd/serengeti_cheetah/Makefile.inc | 19 -------------- .../amd/serengeti_cheetah_fam10/Makefile.inc | 19 -------------- src/mainboard/broadcom/blast/Makefile.inc | 3 -- src/mainboard/msi/ms9282/Makefile.inc | 19 -------------- src/mainboard/supermicro/h8dme/Makefile.inc | 20 --------------- src/mainboard/via/epia-m700/Makefile.inc | 26 -------------------- 6 files changed, 0 insertions(+), 106 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc deleted file mode 100644 index 1ba662e..0000000 --- a/src/mainboard/amd/serengeti_cheetah/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc deleted file mode 100644 index 1ba662e..0000000 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - diff --git a/src/mainboard/broadcom/blast/Makefile.inc b/src/mainboard/broadcom/blast/Makefile.inc deleted file mode 100644 index 77fa6eb..0000000 --- a/src/mainboard/broadcom/blast/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ - -# Needed by irq_tables and mptable and acpi_tables. - diff --git a/src/mainboard/hp/dl145_g1/Makefile.inc b/src/mainboard/hp/dl145_g1/Makefile.inc deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/msi/ms9282/Makefile.inc b/src/mainboard/msi/ms9282/Makefile.inc deleted file mode 100644 index 1ba662e..0000000 --- a/src/mainboard/msi/ms9282/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - diff --git a/src/mainboard/supermicro/h8dme/Makefile.inc b/src/mainboard/supermicro/h8dme/Makefile.inc deleted file mode 100644 index 71baa03..0000000 --- a/src/mainboard/supermicro/h8dme/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# Needed by irq_tables and mptable and acpi_tables. diff --git a/src/mainboard/tyan/s2881/Makefile.inc b/src/mainboard/tyan/s2881/Makefile.inc deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/tyan/s2892/Makefile.inc b/src/mainboard/tyan/s2892/Makefile.inc deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/via/epia-m700/Makefile.inc b/src/mainboard/via/epia-m700/Makefile.inc deleted file mode 100644 index 0308491..0000000 --- a/src/mainboard/via/epia-m700/Makefile.inc +++ /dev/null @@ -1,26 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 VIA Technologies, Inc. -## (Written by Aaron Lwe for VIA) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# This code is unused and should be replaced by the generic resume code -# completely. If anyone works on wakeup for this chipset/board, delete -# wakeup.c when you are done. -# ramstage-y += wakeup.c - From bari at onelabs.com Tue Feb 7 17:53:21 2012 From: bari at onelabs.com (Bari Ari) Date: Tue, 07 Feb 2012 10:53:21 -0600 Subject: [coreboot] How to port core boot In-Reply-To: References: <4F2FBB5F.6070503@georgi-clan.de> <20120206144507.22074.qmail@stuge.se> <1328556068.5785.66.camel@obelix> <4F306454.6070405@assembler.cz> <4F3144FC.3070004@assembler.cz> Message-ID: <4F315701.4000805@onelabs.com> Ali, Here is what is going on here. Unless I missed a memo, coreboot is not a no cost course on learning how to program with 24hr free tech support. Initially I was under the impression that there might be a language barrier here. But after reading your attack on the developers in order to gain some negative attention I see that it's a personality issue. Most of the developers here have families, full time jobs and also work on several open source projects and might even sleep and eat meals as required. Several have spent decades working and studying to gain the experience that they now have but also see the value in sharing some of this for the common good of mankind. If somebody is replying to your novice level questions on how coreboot, C, gcc, memory controllers or x86 architecture works, be happy that somebody has decided to volunteer a small portion of their lifetime to this effort. Most of the answers to your questions are obvious to the experienced developers and most of the replies have hinted at *your need to gain more experience and knowledge* on all the topics I have mentioned earlier. The devs don't really have the time or desire to write lengthy tutorials on the subjects. You might be able to find a mentor though if you ask nicely. It also helps if you fund their time. Have you followed their advice? Have you gone back and worked with some much more simple programming projects to gain the experience necessary? Have you even shared your source code for review? -Bari On 02/07/2012 09:59 AM, ali hagigat wrote: > Rudolf, When i started to study Coreboot and BIOS , people always made > me confused by nonsense words. I asked some useful questions but > interpreted as simple.(now I have developed a project which can drive > RAM, serial port and hard disk) > > The managers of this project even do not accept their own mistakes. > Now FILO can not be compiled and when i report it as the README of the > filo is saying, the manager emails me and tells me that you are not a > programmer!! > > I thought i would be encouraged for that by a thank you. When i ask a > question nobody talks about the details of the logic behind that > except one person, Ky?sti M?lkki. > > Hey folks, what is going on here? If you are a master of Coreboot why > we have unrelated simple answers? > > > On 2/7/12, Rudolf Marek wrote: >> Hi, >> >>> DRAM range verified. >> Well the check is quite simple maybe it works for simple cases and fails for >> real usage. I guess you need to port something like >> http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. >> All >> it sounds like raminit problem. >> >> Also I don't like couple of things btw. You never showed any of your code. >> You >> only ask sometimes too simple question without bothering too much with them. >> Please try hard before asking and try to learn new stuff. You have chosen >> quite >> difficult area, maybe you should try some simpler stuff first to get in >> touch >> better with C and common toolchains and after that get back here in here. >> >> Thanks >> Rudolf >> >> >>> Done. >>> Loading image. >>> Searching for fallback/coreboot_ram >>> Check fallback/romstage >>> Check fallback/coreboot_ram >>> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ >>> 0x100000 >>> Stage: done loading. >>> Jumping to image. >>> >>> >>> On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek wrote: >>>>> Seems there is a case or two of possible infinite while() loops within >>>>> the uart8250 serial console code. This is a wild guess, but the uart >>>> >>>> Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It >>>> is >>>> always better to boot than to have perfect serial output ;) >>>> >>>> But in this case I would think memory is not 100% OK. Worth to check if >>>> 1M->3M is OK (this is where coreboot ramstage goes) >>>> >>>> Thanks >>>> Rudolf >>>> >>>> >>>> -- >>>> coreboot mailing list: coreboot at coreboot.org >>>> http://www.coreboot.org/mailman/listinfo/coreboot From oneingray at gmail.com Wed Feb 8 06:31:25 2012 From: oneingray at gmail.com (Ivan Shmakov) Date: Wed, 08 Feb 2012 12:31:25 +0700 Subject: [coreboot] Coreboot + SeaBIOS on GA-M52S-S3P? References: <86ty33hnyk.fsf@gray.siamics.net> <86pqdrhmkj.fsf@gray.siamics.net> <864nv3gwe5.fsf@gray.siamics.net> <861uq7eztt.fsf@gray.siamics.net> <86wr7zdk0t.fsf_-_@gray.siamics.net> <86ty32d2wq.fsf@gray.siamics.net> Message-ID: <86d39pdh76.fsf@gray.siamics.net> >>>>> Marc Jones writes: >>>>> On Tue, Feb 7, 2012 at 9:27 AM, Ivan Shmakov wrote: >> I wonder, did anyone try Coreboot and SeaBIOS on Gigabyte's >> GA-M52S-S3P? > The nvidia chipset is the biggest challenge. I don't know how close > it is to the nvida support in coreboot. I seem to be quite lucky in this respect, as I've just found that I have at least two systems based on nVidia chipsets. But I'm still interested in running Coreboot there. As per [1], the ?chipset north bridge? is ?GeForce 6100 / nForce 430?, but I don't seem to find those listed in [2]? [1] http://ee.gigabyte.com/products/page/mb/ga-m52s-s3p_10/ [2] http://www.coreboot.org/Supported_Chipsets_and_Devices >> I'm mainly interested in booting Linux 2.6-based GNU system via GRUB >> 2 from a SATA HDD (with GPT), but I'd like to have other boot >> devices (floppy and DVD drives, USB Flash) and systems supported as >> well. > This is a typical coreboot + seabios solution. ACK, thanks. >> One more issue is that the BIOS IC (labelled MX 25L4005AM2C) ? Which may be documented in [3] or [4]. [3] http://semiconductorstore.com/pdf/Macronix/SerialProductBrief.pdf [4] http://www.mct.net/download/macronix/mx25l8005.pdf >> is soldered to the board. I wonder, what'd be the recovery >> procedure should the newly uploaded firmware fail to boot? > There are a number of ways to handle recovery. Please see this page > for more info: > http://www.coreboot.org/Developer_Manual/Tools#External_EPROM.2FFlash_programmer_that_can_program_the_flash_chip_on_your_motherboard This section is mainly concerned with the use of computer's motherboard (with replaceable flash) instead of a ?real? programmer. In my case, the section below is more applicable: --cut: http://www.coreboot.org/Developer_Manual/Tools#In_Circuit_chip_programmer -- In Circuit chip programmer Should allow you to program your BIOS even if it is soldered to the motherboard. ? http://www.xeltek.com/pages.php?pageid=8 --cut: http://www.coreboot.org/Developer_Manual/Tools#In_Circuit_chip_programmer -- Perhaps I'd even be able to build an in-system programmer myself (especially if something like Avrdude [5] supports, or could be tweaked to support, the protocol itself), but I'm not entirely sure that the motherboard in question has all the relevant circuitry to allow for in-system programming. [5] http://www.nongnu.org/avrdude/ [?] -- FSF associate member #7257 From peter at stuge.se Wed Feb 8 12:27:47 2012 From: peter at stuge.se (Peter Stuge) Date: Wed, 8 Feb 2012 12:27:47 +0100 Subject: [coreboot] Coreboot + SeaBIOS on GA-M52S-S3P? In-Reply-To: <86d39pdh76.fsf@gray.siamics.net> References: <86ty33hnyk.fsf@gray.siamics.net> <86pqdrhmkj.fsf@gray.siamics.net> <864nv3gwe5.fsf@gray.siamics.net> <861uq7eztt.fsf@gray.siamics.net> <86wr7zdk0t.fsf_-_@gray.siamics.net> <86ty32d2wq.fsf@gray.siamics.net> <86d39pdh76.fsf@gray.siamics.net> Message-ID: <20120208112747.5648.qmail@stuge.se> Ivan Shmakov wrote: > >> I wonder, did anyone try Coreboot and SeaBIOS on Gigabyte's > >> GA-M52S-S3P? > > > The nvidia chipset is the biggest challenge. I don't know how close > > it is to the nvida support in coreboot. > > I seem to be quite lucky in this respect, as I've just found > that I have at least two systems based on nVidia chipsets. > > But I'm still interested in running Coreboot there. > > As per [1], the ?chipset north bridge? is ?GeForce 6100 / nForce > 430?, but I don't seem to find those listed in [2]? No documentation whatsoever is available. If you want to make coreboot run on such unsupported chipsets you should plan for one or two years of reverse engineering the factory BIOS. Just buy some supported hardware instead. //Peter From oneingray at gmail.com Wed Feb 8 13:58:38 2012 From: oneingray at gmail.com (Ivan Shmakov) Date: Wed, 08 Feb 2012 19:58:38 +0700 Subject: [coreboot] Coreboot + SeaBIOS on GA-M52S-S3P? References: <86ty33hnyk.fsf@gray.siamics.net> <86pqdrhmkj.fsf@gray.siamics.net> <864nv3gwe5.fsf@gray.siamics.net> <861uq7eztt.fsf@gray.siamics.net> <86wr7zdk0t.fsf_-_@gray.siamics.net> <86ty32d2wq.fsf@gray.siamics.net> <86d39pdh76.fsf@gray.siamics.net> <20120208112747.5648.qmail@stuge.se> Message-ID: <864nv1cwht.fsf@gray.siamics.net> >>>>> Peter Stuge writes: >>>>> Ivan Shmakov wrote: >>>> I wonder, did anyone try Coreboot and SeaBIOS on Gigabyte's >>>> GA-M52S-S3P? >>> The nvidia chipset is the biggest challenge. I don't know how >>> close it is to the nvida support in coreboot. >> I seem to be quite lucky in this respect, as I've just found that I >> have at least two systems based on nVidia chipsets. >> But I'm still interested in running Coreboot there. >> As per [1], the ?chipset north bridge? is ?GeForce 6100 / nForce >> 430?, but I don't seem to find those listed in [2]? > No documentation whatsoever is available. Yes, I know that nVidia is evil. Sorry for the buzz. > If you want to make coreboot run on such unsupported chipsets you > should plan for one or two years of reverse engineering the factory > BIOS. > Just buy some supported hardware instead. I'm sure that I will /not/ consider nVidia for any of my future upgrades, thanks. (I've never bought any of their video cards for the very same reason, but apparently hasn't paid the necessary attention to the choice of other hardware.) For now, I'll hopefully be able to work around the original problem without changing BIOS. (But I still have an Intel mainboard to try Coreboot on.) -- FSF associate member #7257 From teg at jklm.no Wed Feb 8 18:28:04 2012 From: teg at jklm.no (Tom Gundersen) Date: Wed, 8 Feb 2012 18:28:04 +0100 Subject: [coreboot] ASUSTeK P5K support Message-ID: Hi guys, My apologies if this has already been discussed, but I could not find any previous mentions on the ml. I'd like to know if my motherboard is supported, or alternatively if there is anything I could do to help it become supported. This is my system (following the FAQ): Board vendor: ASUSTeK Board name: P5K CPU: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz (Type 0, Family 6, Model 15, Stepping 11) Chipset: Intel P35 / ICH9 Specs: # lspci -tvnn -[0000:00]-+-00.0 Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller [8086:29c0] +-01.0-[01]--+-00.0 Advanced Micro Devices [AMD] nee ATI RV630 [Radeon HD 2600XT] [1002:9588] | \-00.1 Advanced Micro Devices [AMD] nee ATI RV630 audio device [Radeon HD 2600 Series] [1002:aa08] +-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] +-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] +-1a.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] +-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] +-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] +-1c.0-[04]-- +-1c.4-[03]--+-00.0 JMicron Technology Corp. JMB363 SATA/IDE Controller [197b:2363] | \-00.1 JMicron Technology Corp. JMB363 SATA/IDE Controller [197b:2363] +-1c.5-[02]----00.0 Atheros Communications Inc. Attansic L1 Gigabit Ethernet [1969:1048] +-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] +-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] +-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] +-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] +-1e.0-[05]----02.0 Ralink corp. RT2600 802.11 MIMO [1814:0401] +-1f.0 Intel Corporation 82801IB (ICH9) LPC Interface Controller [8086:2918] +-1f.2 Intel Corporation 82801IB (ICH9) 2 port SATA Controller [IDE mode] [8086:2921] +-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930] \-1f.5 Intel Corporation 82801I (ICH9 Family) 2 port SATA Controller [IDE mode] [8086:2926] # ./superiotool superiotool r Found Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e # ./superiotool -dV superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x4400, id=0x23a0 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xa023, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xa023 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xa023, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val ff a0 23 ff 00 44 00 00 ff 50 02 00 00 1a 21 00 ff def 00 a0 NA ff 00 MM 00 MM RR 50 00 00 RR e2 21 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 03 78 07 04 3f def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 00 02 f8 03 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 83 def 01 00 60 00 64 01 0c 83 LDN 0x06 (Serial peripheral interface) idx 30 62 63 val 00 ff ff def 00 00 00 LDN 0x07 (GPIO 6) idx 30 f4 f5 f6 f7 val 06 ff ff ff ff def 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED) idx 30 f5 f6 f7 val 00 ff 00 ff def 00 00 00 00 LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe val 0f ff 21 00 f1 0f 00 00 00 00 00 e0 03 00 09 0f f4 00 00 00 def 00 ff 00 00 ff 00 00 00 00 00 00 ff 00 00 00 ff 00 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f6 f7 fe val 01 00 00 00 34 00 00 02 0c 10 09 00 7d 00 00 00 00 00 def 00 00 01 00 ff 08 00 RR 1c 00 RR RR 7c 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 f2 val 01 02 90 00 81 08 80 def 00 00 00 00 81 00 00 LDN 0x0c (PECI, SST) idx e0 e1 e2 e3 e4 e5 e8 f1 fe ff val 10 52 48 48 48 00 01 48 f0 40 def 00 48 48 48 48 00 00 48 00 00 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff # flashrom -V flashrom v0.9.4-r1395 on Linux 3.3.0-rc2-ARCH-00172-g23783f8 (x86_64), built with libpci 3.1.8, GCC 4.6.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2405M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10018 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "P5K" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5K" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "Desktop" Found chipset "Intel ICH9" with PCI ID 8086:2918. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x1464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x2008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=0, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000202 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x02, BRRA 0x02 0x54: 0x00001fff (FREG0: Flash Descriptor) Flash Descriptor region is unused. 0x58: 0x00001fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x00001fff (FREG2: Management Engine) Management Engine region is unused. 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x004140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x0000 (PREOP) 0x96: 0x543b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0x0006019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x91, id2 0x26, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x91, id2 0x26, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x91, id2 0x26, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x91, id2 0x26, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x41, id2 0x53, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xf6, id2 0xc7, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified. Restoring MMIO space at 0x7f9003f1b8a0 Restoring MMIO space at 0x7f9003f1b89c Restoring MMIO space at 0x7f9003f1b898 Restoring MMIO space at 0x7f9003f1b896 Restoring MMIO space at 0x7f9003f1b894 Restoring PCI config space for 00:1f:0 reg 0xdc From peter at stuge.se Wed Feb 8 18:55:13 2012 From: peter at stuge.se (Peter Stuge) Date: Wed, 8 Feb 2012 18:55:13 +0100 Subject: [coreboot] ASUSTeK P5K support In-Reply-To: References: Message-ID: <20120208175513.4438.qmail@stuge.se> Hi Tom, Tom Gundersen wrote: > I'd like to know if my motherboard is supported, or alternatively if > there is anything I could do to help it become supported. .. > CPU: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz (Type 0, Family 6, > Model 15, Stepping 11) This is fine. > Chipset: Intel P35 / ICH9 This is not. Expect to spend perhaps a year on reverse engineering the factory BIOS and porting coreboot to the board. //Peter From teg at jklm.no Wed Feb 8 21:56:14 2012 From: teg at jklm.no (Tom Gundersen) Date: Wed, 8 Feb 2012 21:56:14 +0100 Subject: [coreboot] ASUSTeK P5K support In-Reply-To: <20120208175513.4438.qmail@stuge.se> References: <20120208175513.4438.qmail@stuge.se> Message-ID: Hi Peter, On Wed, Feb 8, 2012 at 6:55 PM, Peter Stuge wrote: > Expect to spend perhaps a year on reverse engineering the factory BIOS > and porting coreboot to the board. Thanks for the info. I guess that's a bit more than what I would be able to do :-) Cheers, Tom From kyosti.malkki at gmail.com Wed Feb 8 22:36:18 2012 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Wed, 08 Feb 2012 23:36:18 +0200 Subject: [coreboot] A decent paper from Intel to study Message-ID: <1328736978.5785.183.camel@obelix> I don't recall the following Intel document being advertised on the list, at least recently. http://download.intel.com/design/intarch/papers/323246.pdf > Minimal Intel Architecture Boot Loader > > Bare Bones Functionality Required for Booting an > Intel Architecture Platform > > If a developer wants to write their own BIOS on IA architecture, then > they have to gather the appropriate documents (which aren?t always > known) and guess the order that the items listed must be done in. > > There currently isn?t one document that describes all the items that > need to be done in one place, nor is the order of initialization > described anywhere. > > There are also many legacy devices that must be initialized and > finding documentation on them is challenging. > > This document is an attempt to document the order, the minimum steps > required, and generate a central repository of the various documents > that contain the technical details of each technology / component of a > typical platform. From peter at stuge.se Wed Feb 8 23:05:23 2012 From: peter at stuge.se (Peter Stuge) Date: Wed, 8 Feb 2012 23:05:23 +0100 Subject: [coreboot] ASUSTeK P5K support In-Reply-To: References: <20120208175513.4438.qmail@stuge.se> Message-ID: <20120208220523.23800.qmail@stuge.se> Hi, Tom Gundersen wrote: > On Wed, Feb 8, 2012 at 6:55 PM, Peter Stuge wrote: > > Expect to spend perhaps a year on reverse engineering the factory BIOS > > and porting coreboot to the board. > > Thanks for the info. I guess that's a bit more than what I would be > able to do :-) It has been done (several times) before, but it's a lot of work. If you would like to run coreboot then by far the best way is to buy hardware which is known to already work well or at least partially. //Peter From peter at stuge.se Wed Feb 8 23:23:47 2012 From: peter at stuge.se (Peter Stuge) Date: Wed, 8 Feb 2012 23:23:47 +0100 Subject: [coreboot] A decent paper from Intel to study In-Reply-To: <1328736978.5785.183.camel@obelix> References: <1328736978.5785.183.camel@obelix> Message-ID: <20120208222347.25258.qmail@stuge.se> Ky?sti M?lkki wrote: > I don't recall the following Intel document being advertised on the > list, at least recently. > > http://download.intel.com/design/intarch/papers/323246.pdf Thanks for the link! Svante's thesis has a bit more detail, and the Intel doc has references to BWG and MRC which as we know aren't so easy to come by, but it's still a nice overview. //Peter From brencelj at gmail.com Wed Feb 8 13:07:06 2012 From: brencelj at gmail.com (Jan Berce) Date: Wed, 8 Feb 2012 13:07:06 +0100 Subject: [coreboot] sony vaio (VPCS12X9E) In-Reply-To: References: Message-ID: Hi I have seen your tutorial for gethering information and I have gether all I can except "*lspnp -vv > lspnp.log*" because I coundt find package for lspnp for my distro and "*msrtool > msrtool.log*" this one gives this "*Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreboot at coreboot.org. Thanks for your help!*" and even with "*-t*" it still gives the same problem. I have attached all other files and I hope they will be some help to you in your progress. If you need any more informations pleas tell me. Best Regards, Jan -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- # biosdecode 2.11 ACPI 2.0 present. OEM Identifier: Sony RSD Table 32-bit Address: 0xB37FE0AC XSD Table 64-bit Address: 0x00000000B37FE120 PNP BIOS 1.0 present. Event Notification: Not Supported Real Mode 16-bit Code Address: F000:B9A6 Real Mode 16-bit Data Address: 0040:0000 16-bit Protected Mode Code Address: 0x000FB9B1 16-bit Protected Mode Data Address: 0x00000400 OEM Device Identifier: SST2400 SMBIOS 2.6 present. Structure Table Length: 723 bytes Structure Table Address: 0x000E90A0 Number Of Structures: 18 Maximum Structure Size: 113 bytes PCI Interrupt Routing 1.0 present. Router ID: 00:1f.0 Exclusive IRQs: None Compatible Router: 8086:122e Slot Entry 1: ID 02:00, on-board Slot Entry 2: ID 03:00, on-board Slot Entry 3: ID 0a:00, on-board Slot Entry 4: ID 0b:00, on-board Slot Entry 5: ID 00:01, on-board Slot Entry 6: ID 00:02, on-board Slot Entry 7: ID 00:03, on-board Slot Entry 8: ID 00:04, on-board Slot Entry 9: ID 00:05, on-board Slot Entry 10: ID 00:06, on-board Slot Entry 11: ID 02:00, on-board Slot Entry 12: ID 03:00, on-board Slot Entry 13: ID 04:00, on-board Slot Entry 14: ID 05:00, on-board Slot Entry 15: ID 06:00, on-board Slot Entry 16: ID 0c:00, on-board Slot Entry 17: ID 0d:00, on-board Slot Entry 18: ID 0e:00, on-board Slot Entry 19: ID 00:16, on-board Slot Entry 20: ID 00:19, on-board Slot Entry 21: ID 00:1a, on-board Slot Entry 22: ID 00:1b, on-board Slot Entry 23: ID 00:1c, on-board Slot Entry 24: ID 00:1d, on-board Slot Entry 25: ID 00:1f, on-board Slot Entry 26: ID 10:00, slot number 1 Slot Entry 27: ID 10:00, slot number 2 Slot Entry 28: ID 10:05, slot number 3 -------------- next part -------------- [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 3.2.2-1-ARCH (tobias at T-POWA-LX) (gcc version 4.6.2 20120120 (prerelease) (GCC) ) #1 SMP PREEMPT Thu Jan 26 08:40:20 CET 2012 [ 0.000000] Command line: root=/dev/sda2 ro elevator=noop acpi_enforce_resources=lax pcie_aspm=force fastboot logo.nologo quiet [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009cc00 (usable) [ 0.000000] BIOS-e820: 000000000009cc00 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000e0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 00000000b3681000 (usable) [ 0.000000] BIOS-e820: 00000000b3681000 - 00000000b36bf000 (reserved) [ 0.000000] BIOS-e820: 00000000b36bf000 - 00000000b375d000 (usable) [ 0.000000] BIOS-e820: 00000000b375d000 - 00000000b37bf000 (ACPI NVS) [ 0.000000] BIOS-e820: 00000000b37bf000 - 00000000b37e6000 (usable) [ 0.000000] BIOS-e820: 00000000b37e6000 - 00000000b37ff000 (ACPI data) [ 0.000000] BIOS-e820: 00000000b37ff000 - 00000000b3800000 (usable) [ 0.000000] BIOS-e820: 00000000b3800000 - 00000000c0000000 (reserved) [ 0.000000] BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved) [ 0.000000] BIOS-e820: 00000000feb00000 - 00000000feb04000 (reserved) [ 0.000000] BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved) [ 0.000000] BIOS-e820: 00000000fed10000 - 00000000fed14000 (reserved) [ 0.000000] BIOS-e820: 00000000fed18000 - 00000000fed1a000 (reserved) [ 0.000000] BIOS-e820: 00000000fed1c000 - 00000000fed20000 (reserved) [ 0.000000] BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved) [ 0.000000] BIOS-e820: 00000000ffe00000 - 0000000100000000 (reserved) [ 0.000000] BIOS-e820: 0000000100000000 - 00000001fc000000 (usable) [ 0.000000] BIOS-e820: 00000001fc000000 - 0000000200000000 (reserved) [ 0.000000] BIOS-e820: 0000000200000000 - 000000023c000000 (usable) [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] DMI 2.6 present. [ 0.000000] DMI: Sony Corporation VPCS11X9E/VAIO, BIOS R1160Q3 09/30/2010 [ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved) [ 0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable) [ 0.000000] No AGP bridge found [ 0.000000] last_pfn = 0x23c000 max_arch_pfn = 0x400000000 [ 0.000000] MTRR default type: uncachable [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-EFFFF write-through [ 0.000000] F0000-FFFFF write-combining [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 000000000 mask F80000000 write-back [ 0.000000] 1 base 0FFE00000 mask FFFE00000 write-protect [ 0.000000] 2 base 080000000 mask FC0000000 write-back [ 0.000000] 3 base 0B8000000 mask FF8000000 uncachable [ 0.000000] 4 base 0B4000000 mask FFC000000 uncachable [ 0.000000] 5 base 0B3800000 mask FFF800000 uncachable [ 0.000000] 6 base 100000000 mask F00000000 write-back [ 0.000000] 7 base 200000000 mask FC0000000 write-back [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 [ 0.000000] last_pfn = 0xb3800 max_arch_pfn = 0x400000000 [ 0.000000] initial memory mapped : 0 - 20000000 [ 0.000000] Base memory trampoline at [ffff880000097000] 97000 size 20480 [ 0.000000] init_memory_mapping: 0000000000000000-00000000b3800000 [ 0.000000] 0000000000 - 00b3800000 page 2M [ 0.000000] kernel direct mapping tables up to b3800000 @ 1fffc000-20000000 [ 0.000000] init_memory_mapping: 0000000100000000-000000023c000000 [ 0.000000] 0100000000 - 023c000000 page 2M [ 0.000000] kernel direct mapping tables up to 23c000000 @ b37dc000-b37e6000 [ 0.000000] RAMDISK: 3798d000 - 37ff0000 [ 0.000000] ACPI: RSDP 00000000000fe020 00024 (v02 Sony) [ 0.000000] ACPI: XSDT 00000000b37fe120 00074 (v01 Sony VAIO 20100930 01000013) [ 0.000000] ACPI: FACP 00000000b37fc000 000F4 (v04 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: DSDT 00000000b37ed000 0BA60 (v02 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: FACS 00000000b376f000 00040 [ 0.000000] ACPI: ASF! 00000000b37fd000 000A5 (v32 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: HPET 00000000b37fb000 00038 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: APIC 00000000b37fa000 0008C (v02 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: MCFG 00000000b37f9000 0003C (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: SLIC 00000000b37ec000 00176 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: SSDT 00000000b37eb000 00172 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: BOOT 00000000b37ea000 00028 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: SSDT 00000000b37e9000 0008E (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: SSDT 00000000b37e6000 009F1 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] No NUMA configuration found [ 0.000000] Faking a node at 0000000000000000-000000023c000000 [ 0.000000] Initmem setup node 0 0000000000000000-000000023c000000 [ 0.000000] NODE_DATA [000000023bffb000 - 000000023bffffff] [ 0.000000] [ffffea0000000000-ffffea0008ffffff] PMD -> [ffff880233800000-ffff88023b5fffff] on node 0 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000010 -> 0x00001000 [ 0.000000] DMA32 0x00001000 -> 0x00100000 [ 0.000000] Normal 0x00100000 -> 0x0023c000 [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[7] active PFN ranges [ 0.000000] 0: 0x00000010 -> 0x0000009c [ 0.000000] 0: 0x00000100 -> 0x000b3681 [ 0.000000] 0: 0x000b36bf -> 0x000b375d [ 0.000000] 0: 0x000b37bf -> 0x000b37e6 [ 0.000000] 0: 0x000b37ff -> 0x000b3800 [ 0.000000] 0: 0x00100000 -> 0x001fc000 [ 0.000000] 0: 0x00200000 -> 0x0023c000 [ 0.000000] On node 0 totalpages: 2012883 [ 0.000000] DMA zone: 64 pages used for memmap [ 0.000000] DMA zone: 5 pages reserved [ 0.000000] DMA zone: 3911 pages, LIFO batch:0 [ 0.000000] DMA32 zone: 16320 pages used for memmap [ 0.000000] DMA32 zone: 714631 pages, LIFO batch:31 [ 0.000000] Normal zone: 20224 pages used for memmap [ 0.000000] Normal zone: 1257728 pages, LIFO batch:31 [ 0.000000] ACPI: PM-Timer IO Port: 0x408 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x01] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x05] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x00] disabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x00] disabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x00] disabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x00] disabled) [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) [ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ2 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 [ 0.000000] SMP: Allowing 8 CPUs, 4 hotplug CPUs [ 0.000000] nr_irqs_gsi: 40 [ 0.000000] PM: Registered nosave memory: 000000000009c000 - 000000000009d000 [ 0.000000] PM: Registered nosave memory: 000000000009d000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000e0000 [ 0.000000] PM: Registered nosave memory: 00000000000e0000 - 0000000000100000 [ 0.000000] PM: Registered nosave memory: 00000000b3681000 - 00000000b36bf000 [ 0.000000] PM: Registered nosave memory: 00000000b375d000 - 00000000b37bf000 [ 0.000000] PM: Registered nosave memory: 00000000b37e6000 - 00000000b37ff000 [ 0.000000] PM: Registered nosave memory: 00000000b3800000 - 00000000c0000000 [ 0.000000] PM: Registered nosave memory: 00000000c0000000 - 00000000e0000000 [ 0.000000] PM: Registered nosave memory: 00000000e0000000 - 00000000f0000000 [ 0.000000] PM: Registered nosave memory: 00000000f0000000 - 00000000feb00000 [ 0.000000] PM: Registered nosave memory: 00000000feb00000 - 00000000feb04000 [ 0.000000] PM: Registered nosave memory: 00000000feb04000 - 00000000fec00000 [ 0.000000] PM: Registered nosave memory: 00000000fec00000 - 00000000fec01000 [ 0.000000] PM: Registered nosave memory: 00000000fec01000 - 00000000fed10000 [ 0.000000] PM: Registered nosave memory: 00000000fed10000 - 00000000fed14000 [ 0.000000] PM: Registered nosave memory: 00000000fed14000 - 00000000fed18000 [ 0.000000] PM: Registered nosave memory: 00000000fed18000 - 00000000fed1a000 [ 0.000000] PM: Registered nosave memory: 00000000fed1a000 - 00000000fed1c000 [ 0.000000] PM: Registered nosave memory: 00000000fed1c000 - 00000000fed20000 [ 0.000000] PM: Registered nosave memory: 00000000fed20000 - 00000000fee00000 [ 0.000000] PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000 [ 0.000000] PM: Registered nosave memory: 00000000fee01000 - 00000000ffe00000 [ 0.000000] PM: Registered nosave memory: 00000000ffe00000 - 0000000100000000 [ 0.000000] PM: Registered nosave memory: 00000001fc000000 - 0000000200000000 [ 0.000000] Allocating PCI resources starting at c0000000 (gap: c0000000:20000000) [ 0.000000] Booting paravirtualized kernel on bare hardware [ 0.000000] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:8 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 28 pages/cpu @ffff88023bc00000 s82048 r8192 d24448 u262144 [ 0.000000] pcpu-alloc: s82048 r8192 d24448 u262144 alloc=1*2097152 [ 0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1976270 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: root=/dev/sda2 ro elevator=noop acpi_enforce_resources=lax pcie_aspm=force fastboot logo.nologo quiet [ 0.000000] PCIe ASPM is forcibly enabled [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) [ 0.000000] Checking aperture... [ 0.000000] No AGP bridge found [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! [ 0.000000] Memory: 7837832k/9371648k available (4281k kernel code, 1320116k absent, 213700k reserved, 4599k data, 728k init) [ 0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 [ 0.000000] Preemptible hierarchical RCU implementation. [ 0.000000] Verbose stalled-CPUs detection is disabled. [ 0.000000] NR_IRQS:4352 nr_irqs:744 16 [ 0.000000] Extended CMOS year: 2000 [ 0.000000] Console: colour VGA+ 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] allocated 66060288 bytes of page_cgroup [ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups [ 0.000000] hpet clockevent registered [ 0.000000] Fast TSC calibration using PIT [ 0.003333] Detected 2260.719 MHz processor. [ 0.000003] Calibrating delay loop (skipped), value calculated using timer frequency.. 4523.83 BogoMIPS (lpj=7535730) [ 0.000008] pid_max: default: 32768 minimum: 301 [ 0.000034] Security Framework initialized [ 0.000039] AppArmor: AppArmor disabled by boot time parameter [ 0.000738] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes) [ 0.002755] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.003588] Mount-cache hash table entries: 256 [ 0.003727] Initializing cgroup subsys cpuacct [ 0.003733] Initializing cgroup subsys memory [ 0.003741] Initializing cgroup subsys devices [ 0.003744] Initializing cgroup subsys freezer [ 0.003746] Initializing cgroup subsys net_cls [ 0.003748] Initializing cgroup subsys blkio [ 0.003778] CPU: Physical Processor ID: 0 [ 0.003780] CPU: Processor Core ID: 0 [ 0.003785] mce: CPU supports 9 MCE banks [ 0.003796] CPU0: Thermal monitoring handled by SMI [ 0.003804] using mwait in idle threads. [ 0.004917] ACPI: Core revision 20110623 [ 0.028669] ftrace: allocating 16779 entries in 66 pages [ 0.034546] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.067486] CPU0: Intel(R) Core(TM) i3 CPU M 350 @ 2.27GHz stepping 02 [ 0.170941] Performance Events: PEBS fmt1+, Westmere events, Intel PMU driver. [ 0.170948] ... version: 3 [ 0.170949] ... bit width: 48 [ 0.170950] ... generic registers: 4 [ 0.170952] ... value mask: 0000ffffffffffff [ 0.170953] ... max period: 000000007fffffff [ 0.170954] ... fixed-purpose events: 3 [ 0.170956] ... event mask: 000000070000000f [ 0.191055] NMI watchdog enabled, takes one hw-pmu counter. [ 0.217539] Booting Node 0, Processors #1 [ 0.217545] smpboot cpu 1: start_ip = 97000 [ 0.310687] CPU1: Thermal monitoring handled by SMI [ 0.330757] NMI watchdog enabled, takes one hw-pmu counter. [ 0.350630] #2 [ 0.350633] smpboot cpu 2: start_ip = 97000 [ 0.443754] CPU2: Thermal monitoring handled by SMI [ 0.463848] NMI watchdog enabled, takes one hw-pmu counter. [ 0.483692] #3 [ 0.483695] smpboot cpu 3: start_ip = 97000 [ 0.576821] CPU3: Thermal monitoring handled by SMI [ 0.596866] NMI watchdog enabled, takes one hw-pmu counter. [ 0.603421] Brought up 4 CPUs [ 0.603427] Total of 4 processors activated (18094.01 BogoMIPS). [ 0.606161] devtmpfs: initialized [ 0.607337] PM: Registering ACPI NVS region at b375d000 (401408 bytes) [ 0.608204] print_constraints: dummy: [ 0.608252] NET: Registered protocol family 16 [ 0.608356] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it [ 0.608359] ACPI: bus type pci registered [ 0.608444] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.608447] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 [ 0.654099] PCI: Using configuration type 1 for base access [ 0.654646] bio: create slab at 0 [ 0.654705] ACPI: Added _OSI(Module Device) [ 0.654707] ACPI: Added _OSI(Processor Device) [ 0.654709] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.654711] ACPI: Added _OSI(Processor Aggregator Device) [ 0.656453] ACPI: EC: Look up EC in DSDT [ 0.658147] ACPI: Executed 1 blocks of module-level executable AML code [ 0.676676] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored [ 0.677177] ACPI: SSDT 00000000b3691918 003E2 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.677629] ACPI: Dynamic OEM Table Load: [ 0.677632] ACPI: SSDT (null) 003E2 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.677795] ACPI: SSDT 00000000b368f798 006F8 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.678234] ACPI: Dynamic OEM Table Load: [ 0.678236] ACPI: SSDT (null) 006F8 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.696877] ACPI: SSDT 00000000b3690a98 00303 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.697374] ACPI: Dynamic OEM Table Load: [ 0.697377] ACPI: SSDT (null) 00303 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.706715] ACPI: SSDT 00000000b368ed98 00119 (v01 Sony VAIO 20100930 INTL 20061109) [ 0.707180] ACPI: Dynamic OEM Table Load: [ 0.707182] ACPI: SSDT (null) 00119 (v01 Sony VAIO 20100930 INTL 20061109) [ 1.017020] ACPI: Interpreter enabled [ 1.017026] ACPI: (supports S0 S3 S4 S5) [ 1.017071] ACPI: Using IOAPIC for interrupt routing [ 1.018136] [Firmware Bug]: ACPI: No _BQC method, cannot determine initial brightness [ 1.022466] ACPI: EC: GPE = 0x16, I/O: command/status = 0x66, data = 0x62 [ 1.023802] ACPI: ACPI Dock Station Driver: 1 docks/bays found [ 1.023805] HEST: Table not found. [ 1.023809] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 1.024203] \_SB_.PCI0:_OSC invalid UUID [ 1.024205] _OSC request data:1 8 1f [ 1.024212] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe]) [ 1.024833] pci_root PNP0A08:00: host bridge window [io 0x0000-0x0cf7] [ 1.024837] pci_root PNP0A08:00: host bridge window [io 0x0d00-0xffff] [ 1.024840] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff] [ 1.024845] pci_root PNP0A08:00: host bridge window [mem 0xc0000000-0xfeafffff] [ 1.024859] pci 0000:00:00.0: [8086:0044] type 0 class 0x000600 [ 1.024879] DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics [ 1.024901] pci 0000:00:02.0: [8086:0046] type 0 class 0x000300 [ 1.024913] pci 0000:00:02.0: reg 10: [mem 0xd0000000-0xd03fffff 64bit] [ 1.024919] pci 0000:00:02.0: reg 18: [mem 0xc0000000-0xcfffffff 64bit pref] [ 1.024924] pci 0000:00:02.0: reg 20: [io 0x7050-0x7057] [ 1.024987] pci 0000:00:16.0: [8086:3b64] type 0 class 0x000780 [ 1.025015] pci 0000:00:16.0: reg 10: [mem 0xdb406100-0xdb40610f 64bit] [ 1.025106] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold [ 1.025111] pci 0000:00:16.0: PME# disabled [ 1.025146] pci 0000:00:1a.0: [8086:3b3c] type 0 class 0x000c03 [ 1.025431] pci 0000:00:1a.0: reg 10: [mem 0xdb405c00-0xdb405fff] [ 1.027045] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold [ 1.027050] pci 0000:00:1a.0: PME# disabled [ 1.027074] pci 0000:00:1b.0: [8086:3b56] type 0 class 0x000403 [ 1.027089] pci 0000:00:1b.0: reg 10: [mem 0xdb400000-0xdb403fff 64bit] [ 1.027152] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold [ 1.027156] pci 0000:00:1b.0: PME# disabled [ 1.027175] pci 0000:00:1c.0: [8086:3b42] type 1 class 0x000604 [ 1.027239] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold [ 1.027243] pci 0000:00:1c.0: PME# disabled [ 1.027263] pci 0000:00:1c.1: [8086:3b44] type 1 class 0x000604 [ 1.027329] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold [ 1.027332] pci 0000:00:1c.1: PME# disabled [ 1.027352] pci 0000:00:1c.2: [8086:3b46] type 1 class 0x000604 [ 1.027418] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold [ 1.027422] pci 0000:00:1c.2: PME# disabled [ 1.027444] pci 0000:00:1c.3: [8086:3b48] type 1 class 0x000604 [ 1.027511] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold [ 1.027515] pci 0000:00:1c.3: PME# disabled [ 1.027534] pci 0000:00:1c.4: [8086:3b4a] type 1 class 0x000604 [ 1.027600] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold [ 1.027604] pci 0000:00:1c.4: PME# disabled [ 1.027632] pci 0000:00:1d.0: [8086:3b34] type 0 class 0x000c03 [ 1.027903] pci 0000:00:1d.0: reg 10: [mem 0xdb405800-0xdb405bff] [ 1.029513] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold [ 1.029517] pci 0000:00:1d.0: PME# disabled [ 1.029536] pci 0000:00:1e.0: [8086:2448] type 1 class 0x000604 [ 1.029596] pci 0000:00:1f.0: [8086:3b09] type 0 class 0x000601 [ 1.029717] pci 0000:00:1f.2: [8086:3b29] type 0 class 0x000106 [ 1.029741] pci 0000:00:1f.2: reg 10: [io 0x7048-0x704f] [ 1.029751] pci 0000:00:1f.2: reg 14: [io 0x705c-0x705f] [ 1.029760] pci 0000:00:1f.2: reg 18: [io 0x7040-0x7047] [ 1.029770] pci 0000:00:1f.2: reg 1c: [io 0x7058-0x705b] [ 1.029780] pci 0000:00:1f.2: reg 20: [io 0x7020-0x703f] [ 1.029790] pci 0000:00:1f.2: reg 24: [mem 0xdb405000-0xdb4057ff] [ 1.029849] pci 0000:00:1f.2: PME# supported from D3hot [ 1.029853] pci 0000:00:1f.2: PME# disabled [ 1.029872] pci 0000:00:1f.3: [8086:3b30] type 0 class 0x000c05 [ 1.029887] pci 0000:00:1f.3: reg 10: [mem 0xdb406000-0xdb4060ff 64bit] [ 1.029907] pci 0000:00:1f.3: reg 20: [io 0x7000-0x701f] [ 1.029943] pci 0000:00:1f.6: [8086:3b32] type 0 class 0x001180 [ 1.029964] pci 0000:00:1f.6: reg 10: [mem 0xdb404000-0xdb404fff 64bit] [ 1.030153] pci 0000:02:00.0: [8086:422c] type 0 class 0x000280 [ 1.030205] pci 0000:02:00.0: reg 10: [mem 0xda400000-0xda401fff 64bit] [ 1.030387] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold [ 1.030413] pci 0000:02:00.0: PME# disabled [ 1.036079] pci 0000:00:1c.0: PCI bridge to [bus 02-02] [ 1.036087] pci 0000:00:1c.0: bridge window [io 0x6000-0x6fff] [ 1.036099] pci 0000:00:1c.0: bridge window [mem 0xda400000-0xdb3fffff] [ 1.036104] pci 0000:00:1c.0: bridge window [mem 0xd0400000-0xd13fffff 64bit pref] [ 1.036193] pci 0000:03:00.0: [1180:e822] type 0 class 0x000805 [ 1.036211] pci 0000:03:00.0: reg 10: [mem 0xd9400a00-0xd9400aff] [ 1.036334] pci 0000:03:00.0: supports D1 D2 [ 1.036335] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 1.036341] pci 0000:03:00.0: PME# disabled [ 1.036382] pci 0000:03:00.1: [1180:e230] type 0 class 0x000880 [ 1.036400] pci 0000:03:00.1: reg 10: [mem 0xd9400900-0xd94009ff] [ 1.036521] pci 0000:03:00.1: supports D1 D2 [ 1.036523] pci 0000:03:00.1: PME# supported from D0 D1 D2 D3hot D3cold [ 1.036528] pci 0000:03:00.1: PME# disabled [ 1.036566] pci 0000:03:00.3: [1180:e832] type 0 class 0x000c00 [ 1.036584] pci 0000:03:00.3: reg 10: [mem 0xd9400000-0xd94007ff] [ 1.036707] pci 0000:03:00.3: supports D1 D2 [ 1.036709] pci 0000:03:00.3: PME# supported from D0 D1 D2 D3hot D3cold [ 1.036714] pci 0000:03:00.3: PME# disabled [ 1.036751] pci 0000:03:00.4: [1180:e822] type 0 class 0x000805 [ 1.036768] pci 0000:03:00.4: reg 10: [mem 0xd9400800-0xd94008ff] [ 1.036890] pci 0000:03:00.4: supports D1 D2 [ 1.036892] pci 0000:03:00.4: PME# supported from D0 D1 D2 D3hot D3cold [ 1.036897] pci 0000:03:00.4: PME# disabled [ 1.042734] pci 0000:00:1c.1: PCI bridge to [bus 03-03] [ 1.042742] pci 0000:00:1c.1: bridge window [io 0x5000-0x5fff] [ 1.042752] pci 0000:00:1c.1: bridge window [mem 0xd9400000-0xda3fffff] [ 1.042757] pci 0000:00:1c.1: bridge window [mem 0xd1400000-0xd23fffff 64bit pref] [ 1.042812] pci 0000:04:00.0: [1969:1063] type 0 class 0x000200 [ 1.042835] pci 0000:04:00.0: reg 10: [mem 0xd8400000-0xd843ffff 64bit] [ 1.042848] pci 0000:04:00.0: reg 18: [io 0x4000-0x407f] [ 1.042949] pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 1.042954] pci 0000:04:00.0: PME# disabled [ 1.049335] pci 0000:00:1c.2: PCI bridge to [bus 04-04] [ 1.049343] pci 0000:00:1c.2: bridge window [io 0x4000-0x4fff] [ 1.049350] pci 0000:00:1c.2: bridge window [mem 0xd8400000-0xd93fffff] [ 1.049361] pci 0000:00:1c.2: bridge window [mem 0xd2400000-0xd33fffff 64bit pref] [ 1.049421] pci 0000:00:1c.3: PCI bridge to [bus 05-05] [ 1.049425] pci 0000:00:1c.3: bridge window [io 0x3000-0x3fff] [ 1.049429] pci 0000:00:1c.3: bridge window [mem 0xd7400000-0xd83fffff] [ 1.049434] pci 0000:00:1c.3: bridge window [mem 0xd3400000-0xd43fffff 64bit pref] [ 1.049472] pci 0000:00:1c.4: PCI bridge to [bus 06-0d] [ 1.049476] pci 0000:00:1c.4: bridge window [io 0x2000-0x2fff] [ 1.049480] pci 0000:00:1c.4: bridge window [mem 0xd5400000-0xd73fffff] [ 1.049485] pci 0000:00:1c.4: bridge window [mem 0xd4400000-0xd53fffff 64bit pref] [ 1.049541] pci 0000:00:1e.0: PCI bridge to [bus 10-10] (subtractive decode) [ 1.049551] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) [ 1.049553] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) [ 1.049556] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) [ 1.049558] pci 0000:00:1e.0: bridge window [mem 0xc0000000-0xfeafffff] (subtractive decode) [ 1.049583] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 1.049721] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P1._PRT] [ 1.049793] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP01._PRT] [ 1.049826] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP02._PRT] [ 1.049862] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP03._PRT] [ 1.049894] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP04._PRT] [ 1.049925] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.RP05._PRT] [ 1.050003] \_SB_.PCI0:_OSC invalid UUID [ 1.050004] _OSC request data:1 1f 1f [ 1.050009] pci0000:00: Requesting ACPI _OSC control (0x1d) [ 1.050040] \_SB_.PCI0:_OSC invalid UUID [ 1.050041] _OSC request data:1 0 1d [ 1.050045] pci0000:00: ACPI _OSC request failed (AE_ERROR), returned control mask: 0x1d [ 1.050047] ACPI _OSC control for PCIe not granted, disabling ASPM [ 1.059544] ACPI: PCI Root Bridge [CPBG] (domain 0000 [bus ff]) [ 1.059616] pci 0000:ff:00.0: [8086:2c62] type 0 class 0x000600 [ 1.059637] pci 0000:ff:00.1: [8086:2d01] type 0 class 0x000600 [ 1.059658] pci 0000:ff:02.0: [8086:2d10] type 0 class 0x000600 [ 1.059676] pci 0000:ff:02.1: [8086:2d11] type 0 class 0x000600 [ 1.059694] pci 0000:ff:02.2: [8086:2d12] type 0 class 0x000600 [ 1.059712] pci 0000:ff:02.3: [8086:2d13] type 0 class 0x000600 [ 1.059745] pci0000:ff: Requesting ACPI _OSC control (0x1d) [ 1.059748] pci0000:ff: ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 1.059750] ACPI _OSC control for PCIe not granted, disabling ASPM [ 1.059990] ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 *7 10 12 14 15) [ 1.060033] ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 11 12 14 15) *10 [ 1.060075] ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 [ 1.060116] ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 *7 11 12 14 15) [ 1.060156] ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *0, disabled. [ 1.060198] ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 *11 12 14 15) [ 1.060239] ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 [ 1.060280] ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 11 12 14 15) *10 [ 1.060377] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none [ 1.060387] vgaarb: loaded [ 1.060388] vgaarb: bridge control possible 0000:00:02.0 [ 1.060450] PCI: Using ACPI for IRQ routing [ 1.068870] PCI: pci_cache_line_size set to 64 bytes [ 1.069066] reserve RAM buffer: 000000000009cc00 - 000000000009ffff [ 1.069068] reserve RAM buffer: 00000000b3681000 - 00000000b3ffffff [ 1.069071] reserve RAM buffer: 00000000b375d000 - 00000000b3ffffff [ 1.069073] reserve RAM buffer: 00000000b37e6000 - 00000000b3ffffff [ 1.069075] reserve RAM buffer: 00000000b3800000 - 00000000b3ffffff [ 1.069178] NetLabel: Initializing [ 1.069180] NetLabel: domain hash size = 128 [ 1.069181] NetLabel: protocols = UNLABELED CIPSOv4 [ 1.069194] NetLabel: unlabeled traffic allowed by default [ 1.069211] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 1.069217] hpet0: 8 comparators, 64-bit 14.318180 MHz counter [ 1.071234] Switching to clocksource hpet [ 1.076894] pnp: PnP ACPI init [ 1.076916] ACPI: bus type pnp registered [ 1.077255] pnp 00:00: [bus 00-fe] [ 1.077258] pnp 00:00: [io 0x0000-0x0cf7 window] [ 1.077260] pnp 00:00: [io 0x0cf8-0x0cff] [ 1.077262] pnp 00:00: [io 0x0d00-0xffff window] [ 1.077264] pnp 00:00: [mem 0x000a0000-0x000bffff window] [ 1.077266] pnp 00:00: [mem 0x000c0000-0x000c3fff window] [ 1.077268] pnp 00:00: [mem 0x000c4000-0x000c7fff window] [ 1.077270] pnp 00:00: [mem 0x000c8000-0x000cbfff window] [ 1.077272] pnp 00:00: [mem 0x000cc000-0x000cffff window] [ 1.077274] pnp 00:00: [mem 0x000d0000-0x000d3fff window] [ 1.077276] pnp 00:00: [mem 0x000d4000-0x000d7fff window] [ 1.077278] pnp 00:00: [mem 0x000d8000-0x000dbfff window] [ 1.077281] pnp 00:00: [mem 0x000dc000-0x000dffff window] [ 1.077283] pnp 00:00: [mem 0x000e0000-0x000e3fff window] [ 1.077285] pnp 00:00: [mem 0x000e4000-0x000e7fff window] [ 1.077287] pnp 00:00: [mem 0x000e8000-0x000ebfff window] [ 1.077289] pnp 00:00: [mem 0x000ec000-0x000effff window] [ 1.077290] pnp 00:00: [mem 0x000f0000-0x000fffff window] [ 1.077292] pnp 00:00: [mem 0xc0000000-0xfeafffff window] [ 1.077294] pnp 00:00: [mem 0xfed40000-0xfed44fff window] [ 1.077391] pnp 00:00: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active) [ 1.077674] pnp 00:01: [io 0x0000-0x001f] [ 1.077677] pnp 00:01: [io 0x0081-0x0091] [ 1.077678] pnp 00:01: [io 0x0093-0x009f] [ 1.077680] pnp 00:01: [io 0x00c0-0x00df] [ 1.077682] pnp 00:01: [dma 4] [ 1.077717] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active) [ 1.077725] pnp 00:02: [mem 0xff000000-0xffffffff] [ 1.077752] pnp 00:02: Plug and Play ACPI device, IDs INT0800 (active) [ 1.077852] pnp 00:03: [mem 0xfed00000-0xfed003ff] [ 1.077881] pnp 00:03: Plug and Play ACPI device, IDs PNP0103 (active) [ 1.077891] pnp 00:04: [io 0x00f0] [ 1.077903] pnp 00:04: [irq 13] [ 1.077929] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active) [ 1.077939] pnp 00:05: [io 0x002e-0x002f] [ 1.077941] pnp 00:05: [io 0x004e-0x004f] [ 1.077942] pnp 00:05: [io 0x0061] [ 1.077944] pnp 00:05: [io 0x0063] [ 1.077945] pnp 00:05: [io 0x0065] [ 1.077947] pnp 00:05: [io 0x0067] [ 1.077948] pnp 00:05: [io 0x0070] [ 1.077950] pnp 00:05: [io 0x0080] [ 1.077951] pnp 00:05: [io 0x0092] [ 1.077953] pnp 00:05: [io 0x00b2-0x00b3] [ 1.077954] pnp 00:05: [io 0x0680-0x069f] [ 1.077956] pnp 00:05: [io 0x0800-0x080f] [ 1.077970] pnp 00:05: [io 0x0810-0x0813] [ 1.077972] pnp 00:05: [io 0xffff] [ 1.077974] pnp 00:05: [io 0x0400-0x047f] [ 1.077976] pnp 00:05: [io 0x0500-0x057f] [ 1.077978] pnp 00:05: [io 0x164e-0x164f] [ 1.078048] system 00:05: [io 0x0680-0x069f] has been reserved [ 1.078051] system 00:05: [io 0x0800-0x080f] has been reserved [ 1.078053] system 00:05: [io 0x0810-0x0813] has been reserved [ 1.078056] system 00:05: [io 0xffff] has been reserved [ 1.078058] system 00:05: [io 0x0400-0x047f] has been reserved [ 1.078060] system 00:05: [io 0x0500-0x057f] has been reserved [ 1.078063] system 00:05: [io 0x164e-0x164f] has been reserved [ 1.078066] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active) [ 1.078075] pnp 00:06: [io 0x0070-0x0077] [ 1.078081] pnp 00:06: [irq 8] [ 1.078109] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) [ 1.078118] pnp 00:07: [io 0x0060] [ 1.078120] pnp 00:07: [io 0x0064] [ 1.078125] pnp 00:07: [irq 1] [ 1.078153] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active) [ 1.078172] pnp 00:08: [irq 12] [ 1.078219] pnp 00:08: Plug and Play ACPI device, IDs PNP0f13 (active) [ 1.078496] pnp 00:09: [mem 0xfed1c000-0xfed1ffff] [ 1.078498] pnp 00:09: [mem 0xfed10000-0xfed13fff] [ 1.078500] pnp 00:09: [mem 0xfed18000-0xfed18fff] [ 1.078502] pnp 00:09: [mem 0xfed19000-0xfed19fff] [ 1.078503] pnp 00:09: [mem 0xe0000000-0xefffffff] [ 1.078505] pnp 00:09: [mem 0xfed20000-0xfed3ffff] [ 1.078507] pnp 00:09: [mem 0xfed90000-0xfed8ffff disabled] [ 1.078511] pnp 00:09: [mem 0xfed45000-0xfed8ffff] [ 1.078513] pnp 00:09: [mem 0xff000000-0xffffffff] [ 1.078515] pnp 00:09: [mem 0xfee00000-0xfeefffff] [ 1.078516] pnp 00:09: [mem 0xdb500000-0xdb500fff] [ 1.078584] system 00:09: [mem 0xfed1c000-0xfed1ffff] has been reserved [ 1.078587] system 00:09: [mem 0xfed10000-0xfed13fff] has been reserved [ 1.078590] system 00:09: [mem 0xfed18000-0xfed18fff] has been reserved [ 1.078592] system 00:09: [mem 0xfed19000-0xfed19fff] has been reserved [ 1.078595] system 00:09: [mem 0xe0000000-0xefffffff] has been reserved [ 1.078597] system 00:09: [mem 0xfed20000-0xfed3ffff] has been reserved [ 1.078600] system 00:09: [mem 0xfed45000-0xfed8ffff] has been reserved [ 1.078602] system 00:09: [mem 0xff000000-0xffffffff] could not be reserved [ 1.078605] system 00:09: [mem 0xfee00000-0xfeefffff] could not be reserved [ 1.078607] system 00:09: [mem 0xdb500000-0xdb500fff] has been reserved [ 1.078610] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active) [ 1.078769] pnp 00:0a: [bus ff] [ 1.078818] pnp 00:0a: Plug and Play ACPI device, IDs PNP0a03 (active) [ 1.078833] pnp: PnP ACPI: found 11 devices [ 1.078835] ACPI: ACPI bus type pnp unregistered [ 1.085906] PCI: max bus depth: 1 pci_try_num: 2 [ 1.085947] pci 0000:00:1c.0: PCI bridge to [bus 02-02] [ 1.085951] pci 0000:00:1c.0: bridge window [io 0x6000-0x6fff] [ 1.085956] pci 0000:00:1c.0: bridge window [mem 0xda400000-0xdb3fffff] [ 1.085960] pci 0000:00:1c.0: bridge window [mem 0xd0400000-0xd13fffff 64bit pref] [ 1.085967] pci 0000:00:1c.1: PCI bridge to [bus 03-03] [ 1.085970] pci 0000:00:1c.1: bridge window [io 0x5000-0x5fff] [ 1.085974] pci 0000:00:1c.1: bridge window [mem 0xd9400000-0xda3fffff] [ 1.085978] pci 0000:00:1c.1: bridge window [mem 0xd1400000-0xd23fffff 64bit pref] [ 1.085984] pci 0000:00:1c.2: PCI bridge to [bus 04-04] [ 1.085987] pci 0000:00:1c.2: bridge window [io 0x4000-0x4fff] [ 1.085992] pci 0000:00:1c.2: bridge window [mem 0xd8400000-0xd93fffff] [ 1.085996] pci 0000:00:1c.2: bridge window [mem 0xd2400000-0xd33fffff 64bit pref] [ 1.086002] pci 0000:00:1c.3: PCI bridge to [bus 05-05] [ 1.086005] pci 0000:00:1c.3: bridge window [io 0x3000-0x3fff] [ 1.086011] pci 0000:00:1c.3: bridge window [mem 0xd7400000-0xd83fffff] [ 1.086015] pci 0000:00:1c.3: bridge window [mem 0xd3400000-0xd43fffff 64bit pref] [ 1.086021] pci 0000:00:1c.4: PCI bridge to [bus 06-0d] [ 1.086024] pci 0000:00:1c.4: bridge window [io 0x2000-0x2fff] [ 1.086028] pci 0000:00:1c.4: bridge window [mem 0xd5400000-0xd73fffff] [ 1.086032] pci 0000:00:1c.4: bridge window [mem 0xd4400000-0xd53fffff 64bit pref] [ 1.086039] pci 0000:00:1e.0: PCI bridge to [bus 10-10] [ 1.086064] pci 0000:00:1c.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 [ 1.086069] pci 0000:00:1c.0: setting latency timer to 64 [ 1.086079] pci 0000:00:1c.1: PCI INT B -> GSI 16 (level, low) -> IRQ 16 [ 1.086083] pci 0000:00:1c.1: setting latency timer to 64 [ 1.086093] pci 0000:00:1c.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18 [ 1.086097] pci 0000:00:1c.2: setting latency timer to 64 [ 1.086107] pci 0000:00:1c.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19 [ 1.086110] pci 0000:00:1c.3: setting latency timer to 64 [ 1.086116] pci 0000:00:1c.4: PCI INT A -> GSI 17 (level, low) -> IRQ 17 [ 1.086120] pci 0000:00:1c.4: setting latency timer to 64 [ 1.086126] pci 0000:00:1e.0: setting latency timer to 64 [ 1.086130] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] [ 1.086132] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] [ 1.086134] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] [ 1.086136] pci_bus 0000:00: resource 7 [mem 0xc0000000-0xfeafffff] [ 1.086139] pci_bus 0000:02: resource 0 [io 0x6000-0x6fff] [ 1.086141] pci_bus 0000:02: resource 1 [mem 0xda400000-0xdb3fffff] [ 1.086143] pci_bus 0000:02: resource 2 [mem 0xd0400000-0xd13fffff 64bit pref] [ 1.086145] pci_bus 0000:03: resource 0 [io 0x5000-0x5fff] [ 1.086147] pci_bus 0000:03: resource 1 [mem 0xd9400000-0xda3fffff] [ 1.086149] pci_bus 0000:03: resource 2 [mem 0xd1400000-0xd23fffff 64bit pref] [ 1.086151] pci_bus 0000:04: resource 0 [io 0x4000-0x4fff] [ 1.086153] pci_bus 0000:04: resource 1 [mem 0xd8400000-0xd93fffff] [ 1.086155] pci_bus 0000:04: resource 2 [mem 0xd2400000-0xd33fffff 64bit pref] [ 1.086158] pci_bus 0000:05: resource 0 [io 0x3000-0x3fff] [ 1.086160] pci_bus 0000:05: resource 1 [mem 0xd7400000-0xd83fffff] [ 1.086162] pci_bus 0000:05: resource 2 [mem 0xd3400000-0xd43fffff 64bit pref] [ 1.086164] pci_bus 0000:06: resource 0 [io 0x2000-0x2fff] [ 1.086166] pci_bus 0000:06: resource 1 [mem 0xd5400000-0xd73fffff] [ 1.086168] pci_bus 0000:06: resource 2 [mem 0xd4400000-0xd53fffff 64bit pref] [ 1.086170] pci_bus 0000:10: resource 4 [io 0x0000-0x0cf7] [ 1.086172] pci_bus 0000:10: resource 5 [io 0x0d00-0xffff] [ 1.086174] pci_bus 0000:10: resource 6 [mem 0x000a0000-0x000bffff] [ 1.086176] pci_bus 0000:10: resource 7 [mem 0xc0000000-0xfeafffff] [ 1.086212] NET: Registered protocol family 2 [ 1.086429] IP route cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 1.087504] TCP established hash table entries: 524288 (order: 11, 8388608 bytes) [ 1.090286] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes) [ 1.090619] TCP: Hash tables configured (established 524288 bind 65536) [ 1.090621] TCP reno registered [ 1.090637] UDP hash table entries: 4096 (order: 5, 131072 bytes) [ 1.090708] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes) [ 1.090863] NET: Registered protocol family 1 [ 1.090880] pci 0000:00:02.0: Boot video device [ 1.114680] PCI: CLS 64 bytes, default 64 [ 1.114736] Unpacking initramfs... [ 1.169811] Freeing initrd memory: 6540k freed [ 1.171241] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 1.171247] Placing 64MB software IO TLB between ffff8800af681000 - ffff8800b3681000 [ 1.171249] software IO TLB at phys 0xaf681000 - 0xb3681000 [ 1.171266] Simple Boot Flag at 0x44 set to 0x1 [ 1.171755] audit: initializing netlink socket (disabled) [ 1.171770] type=2000 audit(1328642600.006:1): initialized [ 1.189419] HugeTLB registered 2 MB page size, pre-allocated 0 pages [ 1.225603] VFS: Disk quotas dquot_6.5.2 [ 1.225663] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 1.225760] msgmni has been set to 15321 [ 1.225936] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 1.225965] io scheduler noop registered (default) [ 1.225968] io scheduler deadline registered [ 1.226000] io scheduler cfq registered [ 1.226398] intel_idle: MWAIT substates: 0x1120 [ 1.226400] intel_idle: v0.4 model 0x25 [ 1.226401] intel_idle: lapic_timer_reliable_states 0xffffffff [ 1.226470] ERST: Table is not found! [ 1.226471] GHES: HEST is not enabled! [ 1.226542] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 1.437583] Linux agpgart interface v0.103 [ 1.437663] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:MOUE] at 0x60,0x64 irq 1,12 [ 1.438993] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.439007] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.439083] mousedev: PS/2 mouse device common for all mice [ 1.439117] rtc_cmos 00:06: RTC can wake from S4 [ 1.439228] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 [ 1.439256] rtc0: alarms up to one year, y3k, 242 bytes nvram, hpet irqs [ 1.439358] cpuidle: using governor ladder [ 1.439509] cpuidle: using governor menu [ 1.439719] TCP cubic registered [ 1.439722] NET: Registered protocol family 17 [ 1.439731] Registering the dns_resolver key type [ 1.439859] PM: Hibernation image not present or could not be loaded. [ 1.439864] registered taskstats version 1 [ 1.457818] rtc_cmos 00:06: setting system clock to 2012-02-07 19:23:21 UTC (1328642601) [ 1.457888] Initializing network drop monitor service [ 1.459306] Freeing unused kernel memory: 728k freed [ 1.459415] Write protecting the kernel read-only data: 8192k [ 1.465428] Freeing unused kernel memory: 1844k freed [ 1.468005] Freeing unused kernel memory: 692k freed [ 1.475453] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0 [ 1.478601] udevd[46]: starting version 179 [ 1.480967] agpgart-intel 0000:00:00.0: Intel HD Graphics Chipset [ 1.481114] agpgart-intel 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable [ 1.482052] agpgart-intel 0000:00:00.0: detected 131072K stolen memory [ 1.482363] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xc0000000 [ 1.488025] [drm] Initialized drm 1.1.0 20060810 [ 1.489558] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input1 [ 1.489566] ACPI: Power Button [PWRB] [ 1.489614] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input2 [ 1.489655] ACPI: Lid Switch [LID0] [ 1.489703] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3 [ 1.489707] ACPI: Power Button [PWRF] [ 1.498861] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.498866] i915 0000:00:02.0: setting latency timer to 64 [ 1.554986] mtrr: no more MTRRs available [ 1.554989] [drm] MTRR allocation failed. Graphics performance may suffer. [ 1.555727] i915 0000:00:02.0: irq 40 for MSI/MSI-X [ 1.555732] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010). [ 1.555733] [drm] Driver supports precise vblank timestamp query. [ 1.555766] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 2.021479] fbcon: inteldrmfb (fb0) is primary device [ 2.172553] Refined TSC clocksource calibration: 2260.999 MHz. [ 2.172559] Switching to clocksource tsc [ 2.281950] Console: switching to colour frame buffer device 170x48 [ 2.284866] fb0: inteldrmfb frame buffer device [ 2.284867] drm: registered panic notifier [ 2.288152] acpi device:02: registered as cooling_device0 [ 2.288421] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input4 [ 2.288431] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 2.288503] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 [ 2.292565] SCSI subsystem initialized [ 2.296658] libata version 3.00 loaded. [ 2.297972] ahci 0000:00:1f.2: version 3.0 [ 2.297987] ahci 0000:00:1f.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19 [ 2.298057] ahci 0000:00:1f.2: irq 41 for MSI/MSI-X [ 2.298084] ahci: SSS flag set, parallel bus scan disabled [ 2.298107] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 4 ports 3 Gbps 0x3 impl SATA mode [ 2.298110] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part apst [ 2.298115] ahci 0000:00:1f.2: setting latency timer to 64 [ 2.298982] scsi0 : ahci [ 2.300110] scsi1 : ahci [ 2.300437] scsi2 : ahci [ 2.300568] scsi3 : ahci [ 2.300769] ata1: SATA max UDMA/133 abar m2048 at 0xdb405000 port 0xdb405100 irq 41 [ 2.300774] ata2: SATA max UDMA/133 abar m2048 at 0xdb405000 port 0xdb405180 irq 41 [ 2.300777] ata3: DUMMY [ 2.300779] ata4: DUMMY [ 2.618333] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 2.618670] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out [ 2.618759] ata1.00: ATA-7: INTEL SSDSA2M120G2GC, 2CV102HD, max UDMA/133 [ 2.618765] ata1.00: 234441648 sectors, multi 1: LBA48 NCQ (depth 31/32) [ 2.619167] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out [ 2.619260] ata1.00: configured for UDMA/133 [ 2.619575] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSA2M120 2CV1 PQ: 0 ANSI: 5 [ 2.621321] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/111 GiB) [ 2.621414] sd 0:0:0:0: [sda] Write Protect is off [ 2.621417] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 2.621443] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 2.621938] sda: sda1 sda2 sda3 [ 2.622852] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.937693] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [ 2.939515] ata2.00: ATAPI: Optiarc DVD RW AD-7930H, 1.V0, max UDMA/100 [ 2.946310] ata2.00: configured for UDMA/100 [ 2.962346] scsi 1:0:0:0: CD-ROM Optiarc DVD RW AD-7930H 1.V0 PQ: 0 ANSI: 5 [ 3.383399] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null) [ 3.751425] udevd[140]: starting version 180 [ 3.790350] Disabling lock debugging due to kernel taint [ 3.794655] vboxdrv: Found 4 processor cores. [ 3.794777] VBoxDrv: dbg - g_abExecMemory=ffffffffa020bbe0 [ 3.794820] vboxdrv: fAsync=0 offMin=0xfc offMax=0x125c [ 3.794893] vboxdrv: TSC mode is 'synchronous', kernel timer mode is 'normal'. [ 3.794895] vboxdrv: Successfully loaded version 4.1.8_OSE (interface 0x00190000). [ 3.798116] fuse init (API version 7.17) [ 3.798197] ACPI: AC Adapter [AC] (on-line) [ 3.799220] ACPI: Battery Slot [BAT1] (battery absent) [ 3.807770] cfg80211: Calling CRDA to update world regulatory domain [ 3.813730] wmi: Mapper loaded [ 3.816958] sony_laptop: Sony Notebook Control Driver v0.6 [ 3.822227] Intel(R) Wireless WiFi Link AGN driver for Linux, in-tree: [ 3.822231] Copyright(c) 2003-2011 Intel Corporation [ 3.822329] iwlwifi 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 3.822339] iwlwifi 0000:02:00.0: setting latency timer to 64 [ 3.822402] iwlwifi 0000:02:00.0: pci_resource_len = 0x00002000 [ 3.822405] iwlwifi 0000:02:00.0: pci_resource_base = ffffc900118bc000 [ 3.822408] iwlwifi 0000:02:00.0: HW Revision ID = 0x35 [ 3.822486] iwlwifi 0000:02:00.0: irq 42 for MSI/MSI-X [ 3.822542] iwlwifi 0000:02:00.0: Detected Intel(R) Centrino(R) Advanced-N 6200 AGN, REV=0x74 [ 3.822664] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [ 3.837256] mei: module is from the staging directory, the quality is unknown, you have been warned. [ 3.837596] mei 0000:00:16.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 3.837605] mei 0000:00:16.0: setting latency timer to 64 [ 3.837745] mei 0000:00:16.0: irq 43 for MSI/MSI-X [ 3.837849] iwlwifi 0000:02:00.0: device EEPROM VER=0x436, CALIB=0x6 [ 3.837853] iwlwifi 0000:02:00.0: Device SKU: 0X1f0 [ 3.837875] iwlwifi 0000:02:00.0: Tunable channels: 13 802.11bg, 24 802.11a channels [ 3.842230] usbcore: registered new interface driver usbfs [ 3.842254] usbcore: registered new interface driver hub [ 3.842308] usbcore: registered new device driver usb [ 3.844027] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 3.844059] ehci_hcd 0000:00:1a.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 3.844098] ehci_hcd 0000:00:1a.0: setting latency timer to 64 [ 3.844102] ehci_hcd 0000:00:1a.0: EHCI Host Controller [ 3.844143] ehci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 1 [ 3.844171] ehci_hcd 0000:00:1a.0: debug port 2 [ 3.848082] ehci_hcd 0000:00:1a.0: cache line size of 64 is not supported [ 3.848102] ehci_hcd 0000:00:1a.0: irq 16, io mem 0xdb405c00 [ 3.856532] atl1c 0000:04:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 3.856546] atl1c 0000:04:00.0: setting latency timer to 64 [ 3.859236] ehci_hcd 0000:00:1a.0: USB 2.0 started, EHCI 1.00 [ 3.859978] hub 1-0:1.0: USB hub found [ 3.859985] hub 1-0:1.0: 3 ports detected [ 3.860133] ehci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23 [ 3.860172] ehci_hcd 0000:00:1d.0: setting latency timer to 64 [ 3.860177] ehci_hcd 0000:00:1d.0: EHCI Host Controller [ 3.860191] ehci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2 [ 3.860228] ehci_hcd 0000:00:1d.0: debug port 2 [ 3.864148] ehci_hcd 0000:00:1d.0: cache line size of 64 is not supported [ 3.864172] ehci_hcd 0000:00:1d.0: irq 23, io mem 0xdb405800 [ 3.868463] sdhci: Secure Digital Host Controller Interface driver [ 3.868465] sdhci: Copyright(c) Pierre Ossman [ 3.870026] sdhci-pci 0000:03:00.0: SDHCI controller found [1180:e822] (rev 0) [ 3.870076] sdhci-pci 0000:03:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 [ 3.870143] sdhci-pci 0000:03:00.0: Will use DMA mode even though HW doesn't fully claim to support it. [ 3.870151] sdhci-pci 0000:03:00.0: setting latency timer to 64 [ 3.870173] _regulator_get: 0000:03:00.0 supply vmmc not found, using dummy regulator [ 3.870836] Registered led device: mmc0:: [ 3.871928] mmc0: SDHCI controller on PCI [0000:03:00.0] using DMA [ 3.871979] sdhci-pci 0000:03:00.4: SDHCI controller found [1180:e822] (rev 0) [ 3.872025] sdhci-pci 0000:03:00.4: PCI INT C -> GSI 19 (level, low) -> IRQ 19 [ 3.872088] sdhci-pci 0000:03:00.4: Will use DMA mode even though HW doesn't fully claim to support it. [ 3.872096] sdhci-pci 0000:03:00.4: setting latency timer to 64 [ 3.872118] _regulator_get: 0000:03:00.4 supply vmmc not found, using dummy regulator [ 3.872122] iTCO_vendor_support: vendor-support=0 [ 3.872990] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.07 [ 3.873102] iTCO_wdt: Found a HM55 TCO device (Version=2, TCOBASE=0x0460) [ 3.873254] Registered led device: mmc1:: [ 3.873483] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0) [ 3.875459] mmc1: SDHCI controller on PCI [0000:03:00.4] using DMA [ 3.875553] firewire_ohci 0000:03:00.3: PCI INT D -> GSI 16 (level, low) -> IRQ 16 [ 3.875590] firewire_ohci 0000:03:00.3: setting latency timer to 64 [ 3.876218] ehci_hcd 0000:00:1d.0: USB 2.0 started, EHCI 1.00 [ 3.876458] hub 2-0:1.0: USB hub found [ 3.876464] hub 2-0:1.0: 3 ports detected [ 3.876815] snd_hda_intel 0000:00:1b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22 [ 3.876819] hda_intel: position_fix set to 1 for device 104d:9069 [ 3.876877] snd_hda_intel 0000:00:1b.0: irq 44 for MSI/MSI-X [ 3.876901] snd_hda_intel 0000:00:1b.0: setting latency timer to 64 [ 3.877839] thermal LNXTHERM:00: registered as thermal_zone0 [ 3.877842] ACPI: Thermal Zone [THRM] (51 C) [ 3.883989] input: PC Speaker as /devices/platform/pcspkr/input/input5 [ 3.898109] sr0: scsi3-mmc drive: 24x/24x writer dvd-ram cd/rw xa/form2 cdda tray [ 3.898115] cdrom: Uniform CD-ROM driver Revision: 3.20 [ 3.898356] sr 1:0:0:0: Attached scsi CD-ROM sr0 [ 3.913940] iwlwifi 0000:02:00.0: loaded firmware version 9.221.4.1 build 25532 [ 3.914237] Registered led device: phy0-led [ 3.919184] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1b.0/input/input6 [ 3.920250] ieee80211 phy0: Selected rate control algorithm 'iwl-agn-rs' [ 3.929915] HDMI status: Codec=3 Pin=4 Presence_Detect=0 ELD_Valid=0 [ 3.930259] input: HDA Intel HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input7 [ 3.931027] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8 [ 3.931118] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 [ 3.931349] intel ips 0000:00:1f.6: CPU TDP doesn't match expected value (found 25, expected 29) [ 3.931381] intel ips 0000:00:1f.6: PCI INT A -> GSI 21 (level, low) -> IRQ 21 [ 3.932276] intel ips 0000:00:1f.6: IPS driver initialized, MCP temp limit 90 [ 3.932323] i801_smbus 0000:00:1f.3: PCI INT C -> GSI 19 (level, low) -> IRQ 19 [ 3.932330] ACPI: resource 0000:00:1f.3 [io 0x7000-0x701f] conflicts with ACPI region SMBI [io 0x7000-0x700f] [ 3.932333] ACPI: This conflict may cause random problems and system instability [ 3.932336] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 3.935704] firewire_ohci 0000:03:00.3: irq 45 for MSI/MSI-X [ 3.935769] firewire_ohci: Added fw-ohci device 0000:03:00.3, OHCI v1.0, 4 IR + 4 IT contexts, quirks 0x1 [ 3.962783] atl1c 0000:04:00.0: version 1.0.1.0-NAPI [ 3.989774] input: Sony Vaio Keys as /devices/LNXSYSTM:00/device:00/PNP0A08:00/device:10/SNY5001:00/input/input10 [ 3.989912] input: Sony Vaio Jogdial as /devices/virtual/input/input11 [ 3.990011] sony_laptop: brightness ignored, must be controlled by ACPI video driver [ 4.165267] usb 1-1: new high-speed USB device number 2 using ehci_hcd [ 4.291451] EXT4-fs (sda2): re-mounted. Opts: discard [ 4.292535] hub 1-1:1.0: USB hub found [ 4.292682] hub 1-1:1.0: 6 ports detected [ 4.295824] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: discard [ 4.299006] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: discard [ 4.398061] usb 2-1: new high-speed USB device number 2 using ehci_hcd [ 4.434933] firewire_core: created device fw0: GUID 0800460304fddfd4, S400 [ 4.522006] hub 2-1:1.0: USB hub found [ 4.522130] hub 2-1:1.0: 8 ports detected [ 4.594497] usb 1-1.1: new full-speed USB device number 3 using ehci_hcd [ 4.625040] psmouse serio1: synaptics: Touchpad model: 1, fw: 7.4, id: 0x1c0b1, caps: 0xd04773/0xa40000/0xa0400 [ 4.660295] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input12 [ 4.744200] usb 1-1.2: new high-speed USB device number 4 using ehci_hcd [ 4.900518] usb 1-1.6: new full-speed USB device number 5 using ehci_hcd [ 5.007918] Bluetooth: Core ver 2.16 [ 5.007946] NET: Registered protocol family 31 [ 5.007949] Bluetooth: HCI device and connection manager initialized [ 5.007953] Bluetooth: HCI socket layer initialized [ 5.007955] Bluetooth: L2CAP socket layer initialized [ 5.007964] Bluetooth: SCO socket layer initialized [ 5.009133] Bluetooth: Generic Bluetooth USB driver ver 0.6 [ 5.009394] usbcore: registered new interface driver btusb [ 5.053657] usb 2-1.1: new full-speed USB device number 3 using ehci_hcd [ 5.173361] Linux media interface: v0.10 [ 5.173397] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [ 5.184342] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [ 5.191968] Linux video capture interface: v2.00 [ 5.198591] uvcvideo: Found UVC 1.00 device (05ca:18b7) [ 5.198977] input: Logitech Logitech Z305 as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.1/2-1.1:1.2/input/input13 [ 5.199882] generic-usb 0003:046D:0A23.0001: input,hidraw0: USB HID v1.00 Device [ Logitech Logitech Z305 ] on usb-0000:00:1d.0-1.1/input2 [ 5.200159] usbcore: registered new interface driver usbhid [ 5.200163] usbhid: USB HID core driver [ 5.201777] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 5.203372] input: UVC Camera (05ca:18b7) as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/input/input14 [ 5.203603] usbcore: registered new interface driver uvcvideo [ 5.203606] USB Video Class driver (1.1.1) [ 5.211908] usbcore: registered new interface driver snd-usb-audio [ 5.219771] Bluetooth: RFCOMM TTY layer initialized [ 5.219785] Bluetooth: RFCOMM socket layer initialized [ 5.219787] Bluetooth: RFCOMM ver 1.11 [ 5.293813] NET: Registered protocol family 10 [ 5.426930] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [ 5.433849] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [ 5.522465] ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 6.516694] hda-intel: IRQ timing workaround is activated for card #0. Suggest a bigger bdl_pos_adj. [ 10.178053] atl1c 0000:04:00.0: irq 46 for MSI/MSI-X [ 10.234616] ADDRCONF(NETDEV_UP): eth0: link is not ready [ 15.835500] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [ 15.842470] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [ 15.949160] ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 16.009773] atl1c 0000:04:00.0: irq 46 for MSI/MSI-X [ 16.066935] ADDRCONF(NETDEV_UP): eth0: link is not ready [ 16.123033] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [ 16.131491] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [ 16.132247] delay: estimated 266, actual 1 [ 16.231469] ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 21.609091] wlan0: authenticate with c0:c1:c0:43:94:ec (try 1) [ 21.611264] wlan0: authenticated [ 21.611422] wlan0: associate with c0:c1:c0:43:94:ec (try 1) [ 21.614846] wlan0: RX AssocResp from c0:c1:c0:43:94:ec (capab=0x411 status=0 aid=1) [ 21.614850] wlan0: associated [ 21.618891] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready [ 23.790329] process `skype' is using obsolete setsockopt SO_BSDCOMPAT [ 24.017850] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [ 31.866858] wlan0: no IPv6 routers present [ 69.151594] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [ 89.033933] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [ 131.517037] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 [ 131.518300] input: Bluetooth Laser Travel Mouse as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.6/1-1.6:1.0/bluetooth/hci0/hci0:11/input15 [ 131.519177] generic-bluetooth 0005:046D:B008.0002: input,hidraw1: BLUETOOTH HID v3.18 Mouse [Bluetooth Laser Travel Mouse] on F0:7B:CB:EE:7D:B8 [ 135.605828] warning: `VirtualBox' uses 32-bit capabilities (legacy support in use) [ 149.249330] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [ 155.817715] usb 2-1.5: new high-speed USB device number 4 using ehci_hcd [ 155.980306] usbcore: registered new interface driver uas [ 155.986351] Initializing USB Mass Storage driver... [ 155.986638] scsi4 : usb-storage 2-1.5:1.0 [ 155.986917] usbcore: registered new interface driver usb-storage [ 155.986924] USB Mass Storage support registered. [ 158.283482] scsi 4:0:0:0: Direct-Access ST 8GB 0000 PQ: 0 ANSI: 0 CCS [ 158.285792] sd 4:0:0:0: [sdb] 15663104 512-byte logical blocks: (8.01 GB/7.46 GiB) [ 158.286780] sd 4:0:0:0: [sdb] Write Protect is off [ 158.286790] sd 4:0:0:0: [sdb] Mode Sense: 43 00 00 00 [ 158.287647] sd 4:0:0:0: [sdb] No Caching mode page present [ 158.287654] sd 4:0:0:0: [sdb] Assuming drive cache: write through [ 158.291216] sd 4:0:0:0: [sdb] No Caching mode page present [ 158.291223] sd 4:0:0:0: [sdb] Assuming drive cache: write through [ 158.292047] sdb: sdb1 [ 158.294416] sd 4:0:0:0: [sdb] No Caching mode page present [ 158.294423] sd 4:0:0:0: [sdb] Assuming drive cache: write through [ 158.294429] sd 4:0:0:0: [sdb] Attached SCSI removable disk [ 180.137997] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [ 187.059054] usb 2-1.1: USB disconnect, device number 3 [ 191.330437] usb 2-1.1: new full-speed USB device number 5 using ehci_hcd [ 191.418344] input: Logitech Logitech Z305 as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1.1/2-1.1:1.2/input/input16 [ 191.418682] generic-usb 0003:046D:0A23.0003: input,hidraw0: USB HID v1.00 Device [ Logitech Logitech Z305 ] on usb-0000:00:1d.0-1.1/input2 [ 276.481628] usb 2-1.5: USB disconnect, device number 4 [ 300.171288] usb 2-1.5: new high-speed USB device number 6 using ehci_hcd [ 300.260316] scsi5 : usb-storage 2-1.5:1.0 [ 301.349124] scsi 5:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 301.704352] sd 5:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 301.704963] sd 5:0:0:0: [sdb] Write Protect is off [ 301.704972] sd 5:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 301.705586] sd 5:0:0:0: [sdb] No Caching mode page present [ 301.705595] sd 5:0:0:0: [sdb] Assuming drive cache: write through [ 301.709482] sd 5:0:0:0: [sdb] No Caching mode page present [ 301.709489] sd 5:0:0:0: [sdb] Assuming drive cache: write through [ 301.723138] sdb: sdb1 [ 301.725826] sd 5:0:0:0: [sdb] No Caching mode page present [ 301.725833] sd 5:0:0:0: [sdb] Assuming drive cache: write through [ 301.725839] sd 5:0:0:0: [sdb] Attached SCSI removable disk [ 310.462200] usb 2-1.5: USB disconnect, device number 6 [ 460.622615] usb 2-1.5: new high-speed USB device number 7 using ehci_hcd [ 460.709771] scsi6 : usb-storage 2-1.5:1.0 [ 462.409060] usb 2-1.2: new high-speed USB device number 8 using ehci_hcd [ 462.498218] scsi7 : usb-storage 2-1.2:1.0 [ 463.006894] scsi 6:0:0:0: Direct-Access ST 8GB 0000 PQ: 0 ANSI: 0 CCS [ 463.009292] sd 6:0:0:0: [sdb] 15663104 512-byte logical blocks: (8.01 GB/7.46 GiB) [ 463.010230] sd 6:0:0:0: [sdb] Write Protect is off [ 463.010240] sd 6:0:0:0: [sdb] Mode Sense: 43 00 00 00 [ 463.011093] sd 6:0:0:0: [sdb] No Caching mode page present [ 463.011101] sd 6:0:0:0: [sdb] Assuming drive cache: write through [ 463.015512] sd 6:0:0:0: [sdb] No Caching mode page present [ 463.015519] sd 6:0:0:0: [sdb] Assuming drive cache: write through [ 463.016516] sdb: sdb1 [ 463.019096] sd 6:0:0:0: [sdb] No Caching mode page present [ 463.019103] sd 6:0:0:0: [sdb] Assuming drive cache: write through [ 463.019109] sd 6:0:0:0: [sdb] Attached SCSI removable disk [ 463.586928] scsi 7:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 463.943034] sd 7:0:0:0: [sdc] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 463.943662] sd 7:0:0:0: [sdc] Write Protect is off [ 463.943670] sd 7:0:0:0: [sdc] Mode Sense: 23 00 00 00 [ 463.944278] sd 7:0:0:0: [sdc] No Caching mode page present [ 463.944289] sd 7:0:0:0: [sdc] Assuming drive cache: write through [ 463.948124] sd 7:0:0:0: [sdc] No Caching mode page present [ 463.948131] sd 7:0:0:0: [sdc] Assuming drive cache: write through [ 463.961809] sdc: sdc1 [ 463.964423] sd 7:0:0:0: [sdc] No Caching mode page present [ 463.964427] sd 7:0:0:0: [sdc] Assuming drive cache: write through [ 463.964431] sd 7:0:0:0: [sdc] Attached SCSI removable disk [ 901.452783] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [ 1358.238853] usb 2-1.5: USB disconnect, device number 7 [ 1675.657415] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 1675.742366] scsi8 : usb-storage 2-1.2:1.0 [ 1676.743462] scsi 8:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 1676.744537] sd 8:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 1676.745044] sd 8:0:0:0: [sdb] Write Protect is off [ 1676.745051] sd 8:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 1676.745566] sd 8:0:0:0: [sdb] No Caching mode page present [ 1676.745574] sd 8:0:0:0: [sdb] Assuming drive cache: write through [ 1676.748806] sd 8:0:0:0: [sdb] No Caching mode page present [ 1676.748811] sd 8:0:0:0: [sdb] Assuming drive cache: write through [ 1676.749801] sdb: sdb1 [ 1676.754141] sd 8:0:0:0: [sdb] No Caching mode page present [ 1676.754146] sd 8:0:0:0: [sdb] Assuming drive cache: write through [ 1676.754149] sd 8:0:0:0: [sdb] Attached SCSI removable disk [ 1771.567098] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 1771.652053] scsi9 : usb-storage 2-1.2:1.0 [ 1772.649932] scsi 9:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 1772.651345] sd 9:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 1772.651874] sd 9:0:0:0: [sdb] Write Protect is off [ 1772.651884] sd 9:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 1772.652486] sd 9:0:0:0: [sdb] No Caching mode page present [ 1772.652495] sd 9:0:0:0: [sdb] Assuming drive cache: write through [ 1772.655485] sd 9:0:0:0: [sdb] No Caching mode page present [ 1772.655492] sd 9:0:0:0: [sdb] Assuming drive cache: write through [ 1772.656518] sdb: sdb1 [ 1772.659362] sd 9:0:0:0: [sdb] No Caching mode page present [ 1772.659370] sd 9:0:0:0: [sdb] Assuming drive cache: write through [ 1772.659376] sd 9:0:0:0: [sdb] Attached SCSI removable disk [ 2443.652998] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 2443.737800] scsi10 : usb-storage 2-1.2:1.0 [ 2444.735622] scsi 10:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 2444.737515] sd 10:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 2444.738063] sd 10:0:0:0: [sdb] Write Protect is off [ 2444.738073] sd 10:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 2444.738692] sd 10:0:0:0: [sdb] No Caching mode page present [ 2444.738700] sd 10:0:0:0: [sdb] Assuming drive cache: write through [ 2444.742429] sd 10:0:0:0: [sdb] No Caching mode page present [ 2444.742432] sd 10:0:0:0: [sdb] Assuming drive cache: write through [ 2444.743271] sdb: sdb1 [ 2444.745785] sd 10:0:0:0: [sdb] No Caching mode page present [ 2444.745790] sd 10:0:0:0: [sdb] Assuming drive cache: write through [ 2444.745793] sd 10:0:0:0: [sdb] Attached SCSI removable disk [ 2630.442050] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 2630.527108] scsi11 : usb-storage 2-1.2:1.0 [ 2631.525093] scsi 11:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 2631.526487] sd 11:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 2631.527016] sd 11:0:0:0: [sdb] Write Protect is off [ 2631.527026] sd 11:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 2631.527668] sd 11:0:0:0: [sdb] No Caching mode page present [ 2631.527678] sd 11:0:0:0: [sdb] Assuming drive cache: write through [ 2631.531535] sd 11:0:0:0: [sdb] No Caching mode page present [ 2631.531543] sd 11:0:0:0: [sdb] Assuming drive cache: write through [ 2631.532547] sdb: sdb1 [ 2631.535021] sd 11:0:0:0: [sdb] No Caching mode page present [ 2631.535030] sd 11:0:0:0: [sdb] Assuming drive cache: write through [ 2631.535037] sd 11:0:0:0: [sdb] Attached SCSI removable disk [ 2808.495370] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 2808.580351] scsi12 : usb-storage 2-1.2:1.0 [ 2809.578271] scsi 12:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 2809.579624] sd 12:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 2809.580194] sd 12:0:0:0: [sdb] Write Protect is off [ 2809.580203] sd 12:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 2809.580868] sd 12:0:0:0: [sdb] No Caching mode page present [ 2809.580877] sd 12:0:0:0: [sdb] Assuming drive cache: write through [ 2809.584494] sd 12:0:0:0: [sdb] No Caching mode page present [ 2809.584502] sd 12:0:0:0: [sdb] Assuming drive cache: write through [ 2809.585490] sdb: sdb1 [ 2809.588299] sd 12:0:0:0: [sdb] No Caching mode page present [ 2809.588306] sd 12:0:0:0: [sdb] Assuming drive cache: write through [ 2809.588313] sd 12:0:0:0: [sdb] Attached SCSI removable disk [ 2964.642089] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 2964.727181] scsi13 : usb-storage 2-1.2:1.0 [ 2965.728165] scsi 13:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 2965.729474] sd 13:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 2965.730225] sd 13:0:0:0: [sdb] Write Protect is off [ 2965.730236] sd 13:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 2965.730822] sd 13:0:0:0: [sdb] No Caching mode page present [ 2965.730832] sd 13:0:0:0: [sdb] Assuming drive cache: write through [ 2965.734488] sd 13:0:0:0: [sdb] No Caching mode page present [ 2965.734496] sd 13:0:0:0: [sdb] Assuming drive cache: write through [ 2965.735484] sdb: sdb1 [ 2965.737918] sd 13:0:0:0: [sdb] No Caching mode page present [ 2965.737927] sd 13:0:0:0: [sdb] Assuming drive cache: write through [ 2965.737936] sd 13:0:0:0: [sdb] Attached SCSI removable disk [ 3113.749549] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 3113.834420] scsi14 : usb-storage 2-1.2:1.0 [ 3114.835205] scsi 14:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 3114.836359] sd 14:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 3114.837061] sd 14:0:0:0: [sdb] Write Protect is off [ 3114.837081] sd 14:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 3114.837691] sd 14:0:0:0: [sdb] No Caching mode page present [ 3114.837701] sd 14:0:0:0: [sdb] Assuming drive cache: write through [ 3114.841202] sd 14:0:0:0: [sdb] No Caching mode page present [ 3114.841206] sd 14:0:0:0: [sdb] Assuming drive cache: write through [ 3114.842183] sdb: sdb1 [ 3114.844773] sd 14:0:0:0: [sdb] No Caching mode page present [ 3114.844778] sd 14:0:0:0: [sdb] Assuming drive cache: write through [ 3114.844782] sd 14:0:0:0: [sdb] Attached SCSI removable disk [ 3531.936085] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 3532.020781] scsi15 : usb-storage 2-1.2:1.0 [ 3533.025414] scsi 15:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 3533.027216] sd 15:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 3533.028208] sd 15:0:0:0: [sdb] Write Protect is off [ 3533.028218] sd 15:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 3533.028822] sd 15:0:0:0: [sdb] No Caching mode page present [ 3533.028832] sd 15:0:0:0: [sdb] Assuming drive cache: write through [ 3533.031951] sd 15:0:0:0: [sdb] No Caching mode page present [ 3533.031959] sd 15:0:0:0: [sdb] Assuming drive cache: write through [ 3533.032990] sdb: sdb1 [ 3533.035558] sd 15:0:0:0: [sdb] No Caching mode page present [ 3533.035566] sd 15:0:0:0: [sdb] Assuming drive cache: write through [ 3533.035573] sd 15:0:0:0: [sdb] Attached SCSI removable disk [ 3742.754957] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 3742.839239] scsi16 : usb-storage 2-1.2:1.0 [ 3743.837214] scsi 16:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 3743.838725] sd 16:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 3743.839622] sd 16:0:0:0: [sdb] Write Protect is off [ 3743.839633] sd 16:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 3743.840731] sd 16:0:0:0: [sdb] No Caching mode page present [ 3743.840738] sd 16:0:0:0: [sdb] Assuming drive cache: write through [ 3743.843746] sd 16:0:0:0: [sdb] No Caching mode page present [ 3743.843754] sd 16:0:0:0: [sdb] Assuming drive cache: write through [ 3743.844750] sdb: sdb1 [ 3743.847457] sd 16:0:0:0: [sdb] No Caching mode page present [ 3743.847465] sd 16:0:0:0: [sdb] Assuming drive cache: write through [ 3743.847471] sd 16:0:0:0: [sdb] Attached SCSI removable disk [ 4313.714053] usb 2-1.5: new high-speed USB device number 9 using ehci_hcd [ 4313.808199] scsi17 : usb-storage 2-1.5:1.0 [ 4314.810458] scsi 17:0:0:0: Direct-Access luxmedia 12-Z5 1.00 PQ: 0 ANSI: 4 [ 4314.811521] sd 17:0:0:0: [sdb] 7744512 512-byte logical blocks: (3.96 GB/3.69 GiB) [ 4314.813031] sd 17:0:0:0: [sdb] Write Protect is off [ 4314.813042] sd 17:0:0:0: [sdb] Mode Sense: 00 0b 00 00 [ 4314.813738] sd 17:0:0:0: [sdb] No Caching mode page present [ 4314.813746] sd 17:0:0:0: [sdb] Assuming drive cache: write through [ 4314.816829] sd 17:0:0:0: [sdb] No Caching mode page present [ 4314.816836] sd 17:0:0:0: [sdb] Assuming drive cache: write through [ 4314.820117] sdb: sdb1 [ 4314.822969] sd 17:0:0:0: [sdb] No Caching mode page present [ 4314.822976] sd 17:0:0:0: [sdb] Assuming drive cache: write through [ 4314.822982] sd 17:0:0:0: [sdb] Attached SCSI removable disk [ 4649.807030] usb 2-1.5: reset high-speed USB device number 9 using ehci_hcd [ 4649.899337] scsi18 : usb-storage 2-1.5:1.0 [ 4650.900087] scsi 18:0:0:0: Direct-Access luxmedia 12-Z5 1.00 PQ: 0 ANSI: 4 [ 4650.901639] sd 18:0:0:0: [sdb] 7744512 512-byte logical blocks: (3.96 GB/3.69 GiB) [ 4650.902118] sd 18:0:0:0: [sdb] Write Protect is off [ 4650.902123] sd 18:0:0:0: [sdb] Mode Sense: 00 0b 00 00 [ 4650.902643] sd 18:0:0:0: [sdb] No Caching mode page present [ 4650.902647] sd 18:0:0:0: [sdb] Assuming drive cache: write through [ 4650.905232] sd 18:0:0:0: [sdb] No Caching mode page present [ 4650.905236] sd 18:0:0:0: [sdb] Assuming drive cache: write through [ 4650.907242] sdb: sdb1 [ 4650.909725] sd 18:0:0:0: [sdb] No Caching mode page present [ 4650.909729] sd 18:0:0:0: [sdb] Assuming drive cache: write through [ 4650.909732] sd 18:0:0:0: [sdb] Attached SCSI removable disk [ 4656.653473] usb 2-1.5: USB disconnect, device number 9 [ 5347.864442] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [ 5352.939234] scsi19 : usb-storage 2-1.2:1.0 [ 5353.937159] scsi 19:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [ 5353.938167] sd 19:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [ 5353.938918] sd 19:0:0:0: [sdb] Write Protect is off [ 5353.938924] sd 19:0:0:0: [sdb] Mode Sense: 23 00 00 00 [ 5353.939385] sd 19:0:0:0: [sdb] No Caching mode page present [ 5353.939390] sd 19:0:0:0: [sdb] Assuming drive cache: write through [ 5353.942274] sd 19:0:0:0: [sdb] No Caching mode page present [ 5353.942281] sd 19:0:0:0: [sdb] Assuming drive cache: write through [ 5353.943315] sdb: sdb1 [ 5353.947182] sd 19:0:0:0: [sdb] No Caching mode page present [ 5353.947190] sd 19:0:0:0: [sdb] Assuming drive cache: write through [ 5353.947196] sd 19:0:0:0: [sdb] Attached SCSI removable disk [ 8401.165474] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [11394.132474] usb 2-1.2: reset high-speed USB device number 8 using ehci_hcd [11399.207472] scsi20 : usb-storage 2-1.2:1.0 [11400.205586] scsi 20:0:0:0: Direct-Access USB FLASH DRIVE PMAP PQ: 0 ANSI: 0 CCS [11400.207206] sd 20:0:0:0: [sdb] 7834944 512-byte logical blocks: (4.01 GB/3.73 GiB) [11400.208364] sd 20:0:0:0: [sdb] Write Protect is off [11400.208374] sd 20:0:0:0: [sdb] Mode Sense: 23 00 00 00 [11400.208970] sd 20:0:0:0: [sdb] No Caching mode page present [11400.208977] sd 20:0:0:0: [sdb] Assuming drive cache: write through [11400.212495] sd 20:0:0:0: [sdb] No Caching mode page present [11400.212502] sd 20:0:0:0: [sdb] Assuming drive cache: write through [11400.213479] sdb: sdb1 [11400.215955] sd 20:0:0:0: [sdb] No Caching mode page present [11400.215962] sd 20:0:0:0: [sdb] Assuming drive cache: write through [11400.215968] sd 20:0:0:0: [sdb] Attached SCSI removable disk [11439.447658] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [11575.148588] usb 2-1.2: USB disconnect, device number 8 [12736.100943] EXT4-fs (sda2): re-mounted. Opts: discard,commit=0 [12736.105193] EXT4-fs (sda1): re-mounted. Opts: discard,commit=0 [12736.117416] EXT4-fs (sda3): re-mounted. Opts: discard,commit=0 [12736.555998] wlan0: deauthenticating from c0:c1:c0:43:94:ec by local choice (reason=3) [12736.737116] cfg80211: Calling CRDA for country: SI [12736.824283] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [12736.831261] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [12736.935030] ADDRCONF(NETDEV_UP): wlan0: link is not ready [12737.014610] atl1c 0000:04:00.0: irq 46 for MSI/MSI-X [12737.071035] ADDRCONF(NETDEV_UP): eth0: link is not ready [12737.084744] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [12737.091692] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [12737.204802] ADDRCONF(NETDEV_UP): wlan0: link is not ready [12737.260334] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [12737.267261] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [12737.368736] ADDRCONF(NETDEV_UP): wlan0: link is not ready [12737.425330] atl1c 0000:04:00.0: irq 46 for MSI/MSI-X [12737.480774] ADDRCONF(NETDEV_UP): eth0: link is not ready [12737.624475] PM: Syncing filesystems ... done. [12737.627731] PM: Preparing system for mem sleep [12738.340572] Freezing user space processes ... (elapsed 0.01 seconds) done. [12738.353840] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [12738.367139] PM: Entering mem sleep [12738.367210] Suspending console(s) (use no_console_suspend to debug) [12738.386893] sd 0:0:0:0: [sda] Synchronizing SCSI cache [12738.387014] sd 0:0:0:0: [sda] Stopping disk [12738.425751] ehci_hcd 0000:00:1d.0: PCI INT A disabled [12738.425811] ehci_hcd 0000:00:1a.0: PCI INT A disabled [12738.426756] sdhci-pci 0000:03:00.0: PCI INT A disabled [12738.427721] sdhci-pci 0000:03:00.4: PCI INT C disabled [12738.430426] ACPI handle has no context! [12738.633622] snd_hda_intel 0000:00:1b.0: PCI INT A disabled [12738.673179] PM: suspend of devices complete after 306.196 msecs [12738.699895] ehci_hcd 0000:00:1d.0: PME# enabled [12738.699940] ehci_hcd 0000:00:1d.0: wake-up capability enabled by ACPI [12738.713109] ehci_hcd 0000:00:1a.0: PME# enabled [12738.713135] ehci_hcd 0000:00:1a.0: wake-up capability enabled by ACPI [12738.739756] PM: late suspend of devices complete after 66.704 msecs [12738.739931] ACPI: Preparing to enter system sleep state S3 [12738.740140] PM: Saving platform NVS memory [12738.741864] Disabling non-boot CPUs ... [12738.743604] CPU 1 is now offline [12738.849470] CPU 2 is now offline [12738.876040] intel ips 0000:00:1f.6: MCP limit exceeded: Avg power 57882, limit 35000 [12738.955872] CPU 3 is now offline [12738.956363] Extended CMOS year: 2000 [12738.956575] ACPI: Low-level resume complete [12738.956628] PM: Restoring platform NVS memory [12738.956969] CPU0: Thermal monitoring handled by SMI [12738.957026] Extended CMOS year: 2000 [12738.957067] Enabling non-boot CPUs ... [12738.980263] Booting Node 0 Processor 1 APIC 0x1 [12738.980265] smpboot cpu 1: start_ip = 97000 [12739.016208] Calibrating delay loop (skipped) already calibrated this CPU [12739.016236] CPU1: Thermal monitoring handled by SMI [12739.124309] NMI watchdog enabled, takes one hw-pmu counter. [12739.124713] CPU1 is up [12739.125887] Booting Node 0 Processor 2 APIC 0x4 [12739.125889] smpboot cpu 2: start_ip = 97000 [12739.140854] Calibrating delay loop (skipped) already calibrated this CPU [12739.140880] CPU2: Thermal monitoring handled by SMI [12739.161449] NMI watchdog enabled, takes one hw-pmu counter. [12739.161837] CPU2 is up [12739.161899] Booting Node 0 Processor 3 APIC 0x5 [12739.161900] smpboot cpu 3: start_ip = 97000 [12739.172999] Calibrating delay loop (skipped) already calibrated this CPU [12739.173027] CPU3: Thermal monitoring handled by SMI [12739.193505] NMI watchdog enabled, takes one hw-pmu counter. [12739.193855] CPU3 is up [12739.196431] ACPI: Waking up from system sleep state S3 [12739.203017] i915 0000:00:02.0: restoring config space at offset 0x1 (was 0x900007, writing 0x900407) [12739.203094] ehci_hcd 0000:00:1a.0: restoring config space at offset 0x1 (was 0x2900006, writing 0x2900002) [12739.203134] ehci_hcd 0000:00:1a.0: wake-up capability disabled by ACPI [12739.203142] ehci_hcd 0000:00:1a.0: PME# disabled [12739.203172] snd_hda_intel 0000:00:1b.0: restoring config space at offset 0x1 (was 0x100006, writing 0x100002) [12739.203208] pcieport 0000:00:1c.0: restoring config space at offset 0x7 (was 0x20006060, writing 0x6060) [12739.203253] pcieport 0000:00:1c.1: restoring config space at offset 0x7 (was 0x20005050, writing 0x5050) [12739.203338] pcieport 0000:00:1c.3: restoring config space at offset 0x7 (was 0x20003030, writing 0x3030) [12739.203383] pcieport 0000:00:1c.4: restoring config space at offset 0x7 (was 0x20002020, writing 0x2020) [12739.203436] ehci_hcd 0000:00:1d.0: restoring config space at offset 0x1 (was 0x2900006, writing 0x2900002) [12739.203472] ehci_hcd 0000:00:1d.0: wake-up capability disabled by ACPI [12739.203478] ehci_hcd 0000:00:1d.0: PME# disabled [12739.203495] pci 0000:00:1e.0: restoring config space at offset 0xa (was 0xffffffff, writing 0x0) [12739.203588] ahci 0000:00:1f.2: restoring config space at offset 0x1 (was 0x2b00007, writing 0x2b00407) [12739.204430] PM: early resume of devices complete after 1.523 msecs [12739.204580] i915 0000:00:02.0: setting latency timer to 64 [12739.204614] mei 0000:00:16.0: irq 43 for MSI/MSI-X [12739.204644] ehci_hcd 0000:00:1a.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [12739.204649] snd_hda_intel 0000:00:1b.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22 [12739.204653] ehci_hcd 0000:00:1a.0: setting latency timer to 64 [12739.204656] snd_hda_intel 0000:00:1b.0: setting latency timer to 64 [12739.204693] ehci_hcd 0000:00:1d.0: PCI INT A -> GSI 23 (level, low) -> IRQ 23 [12739.204698] snd_hda_intel 0000:00:1b.0: irq 44 for MSI/MSI-X [12739.204701] ehci_hcd 0000:00:1d.0: setting latency timer to 64 [12739.204724] pci 0000:00:1e.0: setting latency timer to 64 [12739.204739] ahci 0000:00:1f.2: setting latency timer to 64 [12739.204761] iwlwifi 0000:02:00.0: RF_KILL bit toggled to disable radio. [12739.204811] sdhci-pci 0000:03:00.0: PCI INT A -> GSI 17 (level, low) -> IRQ 17 [12739.204853] sdhci-pci 0000:03:00.4: PCI INT C -> GSI 19 (level, low) -> IRQ 19 [12739.204906] sd 0:0:0:0: [sda] Starting disk [12739.208974] legacy_resume(): pnp_bus_resume+0x0/0x70 returns -19 [12739.208976] PM: Device 00:08 failed to resume: error -19 [12739.219383] ------------[ cut here ]------------ [12739.219405] WARNING: at drivers/net/wireless/iwlwifi/iwl-core.c:1330 iwlagn_mac_remove_interface+0x98/0x120 [iwlwifi]() [12739.219407] Hardware name: VPCS11X9E [12739.219408] Modules linked in: nls_cp437 vfat fat usb_storage uas hidp aes_generic ipv6 rfcomm cuse snd_usb_audio bnep snd_usbmidi_lib uvcvideo snd_rawmidi usbhid snd_seq_device hid videodev v4l2_compat_ioctl32 media btusb bluetooth joydev snd_hda_codec_hdmi snd_hda_codec_realtek arc4 mxm_wmi psmouse pcspkr serio_raw sr_mod cdrom i2c_i801 intel_ips snd_hda_intel snd_hda_codec iTCO_wdt iTCO_vendor_support snd_hwdep firewire_ohci sdhci_pci snd_pcm sdhci firewire_core mmc_core crc_itu_t atl1c snd_page_alloc snd_timer ehci_hcd snd usbcore soundcore thermal mei(C) usb_common iwlwifi sony_laptop wmi mac80211 cfg80211 rfkill evdev coretemp battery ac fuse vboxdrv(O) cpufreq_ondemand acpi_cpufreq mperf processor freq_table ext4 jbd2 crc16 mbcache sd_mod ahci libahci libata scsi_mod i915 video button i2c_algo_bit drm_kms_helper drm i2c_core intel_agp intel_gtt [12739.219452] Pid: 9808, comm: kworker/0:0 Tainted: G C O 3.2.2-1-ARCH #1 [12739.219454] Call Trace: [12739.219462] [] warn_slowpath_common+0x7f/0xc0 [12739.219466] [] warn_slowpath_null+0x1a/0x20 [12739.219473] [] iwlagn_mac_remove_interface+0x98/0x120 [iwlwifi] [12739.219482] [] ieee80211_do_stop+0x4eb/0x550 [mac80211] [12739.219490] [] ? cfg80211_rfkill_set_block+0xa0/0xa0 [cfg80211] [12739.219498] [] ieee80211_stop+0x1a/0x20 [mac80211] [12739.219504] [] __dev_close_many+0x86/0xe0 [12739.219506] [] dev_close_many+0xa0/0x110 [12739.219510] [] dev_close+0x3f/0x60 [12739.219516] [] cfg80211_rfkill_set_block+0x71/0xa0 [cfg80211] [12739.219521] [] cfg80211_rfkill_sync_work+0x26/0x30 [cfg80211] [12739.219526] [] process_one_work+0x116/0x4d0 [12739.219529] [] worker_thread+0x15e/0x350 [12739.219532] [] ? manage_workers.isra.29+0x230/0x230 [12739.219535] [] kthread+0x8c/0xa0 [12739.219540] [] kernel_thread_helper+0x4/0x10 [12739.219542] [] ? kthread_worker_fn+0x190/0x190 [12739.219544] [] ? gs_change+0x13/0x13 [12739.219546] ---[ end trace 6d484af963388e3a ]--- [12739.219548] iwlwifi 0000:02:00.0: ctx->vif = (null), vif = ffff88022bed1e10 [12739.219551] iwlwifi 0000:02:00.0: ID = 0: ctx = ffff88022d24b540 ctx->vif = (null) [12739.259419] firewire_ohci 0000:03:00.3: irq 45 for MSI/MSI-X [12739.259549] firewire_core: skipped bus generations, destroying all nodes [12739.286245] atl1c 0000:04:00.0: irq 46 for MSI/MSI-X [12739.525503] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [12739.525596] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [12739.525847] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out [12739.526361] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out [12739.526423] ata1.00: configured for UDMA/133 [12739.583604] ata2.00: configured for UDMA/100 [12739.705124] sdhci-pci 0000:03:00.4: Will use DMA mode even though HW doesn't fully claim to support it. [12739.705146] sdhci-pci 0000:03:00.0: Will use DMA mode even though HW doesn't fully claim to support it. [12739.705171] sdhci-pci 0000:03:00.4: setting latency timer to 64 [12739.705180] sdhci-pci 0000:03:00.0: setting latency timer to 64 [12739.722696] PM: resume of devices complete after 519.213 msecs [12739.723008] PM: Finishing wakeup. [12739.723009] Restarting tasks ... [12739.728856] usb 1-1.6: USB disconnect, device number 5 [12739.733055] done. [12739.733063] video LNXVIDEO:00: Restoring backlight state [12739.758383] firewire_core: rediscovered device fw0 [12743.190704] EXT4-fs (sda2): re-mounted. Opts: discard,commit=0 [12743.194821] EXT4-fs (sda1): re-mounted. Opts: discard,commit=0 [12743.224291] EXT4-fs (sda3): re-mounted. Opts: discard,commit=0 [12745.706513] iwlwifi 0000:02:00.0: RF_KILL bit toggled to enable radio. [12746.288967] usb 1-1.6: new full-speed USB device number 6 using ehci_hcd [12746.897276] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [12746.904161] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [12747.009974] ADDRCONF(NETDEV_UP): wlan0: link is not ready [12750.620283] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [12750.627208] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [12750.729687] ADDRCONF(NETDEV_UP): wlan0: link is not ready [12750.787848] atl1c 0000:04:00.0: irq 46 for MSI/MSI-X [12750.844380] ADDRCONF(NETDEV_UP): eth0: link is not ready [12750.905832] iwlwifi 0000:02:00.0: L1 Disabled; Enabling L0S [12750.912713] iwlwifi 0000:02:00.0: Radio type=0x1-0x3-0x1 [12751.026644] ADDRCONF(NETDEV_UP): wlan0: link is not ready [12753.217427] wlan0: authenticate with c0:c1:c0:43:94:ec (try 1) [12753.219610] wlan0: authenticated [12753.219768] wlan0: associate with c0:c1:c0:43:94:ec (try 1) [12753.223200] wlan0: RX AssocResp from c0:c1:c0:43:94:ec (capab=0x411 status=0 aid=2) [12753.223206] wlan0: associated [12753.227778] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready [12756.813226] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [12764.073381] wlan0: no IPv6 routers present [12877.526935] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [12920.082803] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [12933.973858] input: Bluetooth Laser Travel Mouse as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.6/1-1.6:1.0/bluetooth/hci0/hci0:11/input17 [12933.974237] generic-bluetooth 0005:046D:B008.0004: input,hidraw1: BLUETOOTH HID v3.18 Mouse [Bluetooth Laser Travel Mouse] on F0:7B:CB:EE:7D:B8 [13005.100319] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13025.809221] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13099.479757] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13144.653753] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13169.603837] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13219.870625] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13271.940706] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13309.412936] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13319.640364] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13365.695754] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13379.902967] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13429.867060] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13573.566713] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13637.238919] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13736.368758] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13757.280663] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13790.358595] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13846.866564] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13897.196185] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13939.195761] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [13970.620483] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14012.826573] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14063.166656] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14233.708174] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14250.208842] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14268.971930] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14304.341232] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14341.830252] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14368.450605] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14426.828431] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14457.806653] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14473.768272] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14490.647983] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14505.618407] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14535.472621] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14629.771883] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14651.455528] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14686.196694] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14711.180400] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14775.426099] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14834.715080] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14912.713786] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [14950.808081] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15010.566027] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15070.454628] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15125.519700] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15155.431971] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15181.982348] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15289.918082] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15321.196078] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15373.689425] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15403.680922] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15429.896977] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15474.209836] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15648.000376] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15674.255644] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15707.482623] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15794.333570] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [15905.141120] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16066.696304] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16207.215657] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16451.615429] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16496.662619] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16528.832141] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16565.396324] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16586.218255] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16632.260189] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16650.738116] atl1c 0000:04:00.0: vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update. [16654.522845] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16662.348422] atl1c 0000:04:00.0: vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update. [16673.017225] atl1c 0000:04:00.0: vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update. [16681.169790] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16713.156337] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16831.132056] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16854.555563] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16879.402929] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16907.394053] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 [16967.099208] iwlwifi 0000:02:00.0: Tx aggregation enabled on ra = c0:c1:c0:43:94:ec tid = 0 -------------- next part -------------- # dmidecode 2.11 SMBIOS 2.6 present. 18 structures occupying 723 bytes. Table at 0x000E90A0. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: INSYDE Version: R1160Q3 Release Date: 09/30/2010 ROM Size: 2048 kB Characteristics: PCI is supported PNP is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported EDD is supported 8042 keyboard services are supported (int 9h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported Smart battery is supported BIOS boot specification is supported Function key-initiated network boot is supported Targeted content distribution is supported BIOS Revision: 11.60 Firmware Revision: 11.60 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Sony Corporation Product Name: VPCS11X9E Version: C104F18B Serial Number: 27516361-5000043 UUID: 10F69160-DDC1-11DE-8A3D-0024BEEAB1CD Wake-up Type: Power Switch SKU Number: N/A Family: VAIO Handle 0x0002, DMI type 2, 10 bytes Base Board Information Manufacturer: Sony Corporation Product Name: VAIO Version: N/A Serial Number: C104F18B Asset Tag: N/A Features: Board is a hosting board Handle 0x0003, DMI type 3, 17 bytes Chassis Information Manufacturer: Sony Corporation Type: Notebook Lock: Not Present Version: N/A Serial Number: N/A Asset Tag: N/A Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Handle 0x0004, DMI type 11, 5 bytes OEM Strings String 1: 0000061578B String 2: FNC-EXTB String 3: 969H3ERrMDzVPlLOsDzczNLOpsRczKXFNNQmhzNzZVPlLrMDzc String 4: Reserved String 5: 6.0.31.1208 Handle 0x0005, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x0006, DMI type 136, 6 bytes OEM-specific Type Header and Data: 88 06 06 00 06 12 Handle 0x0007, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: Unknown Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x0008, DMI type 17, 21 bytes Memory Device Array Handle: 0x0007 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: SODIMM1 Bank Locator: Bank 0 Type: DDR3 Type Detail: Unknown Handle 0x0009, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0008 Memory Array Mapped Address Handle: 0x000C Partition Row Position: Unknown Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x000A, DMI type 17, 21 bytes Memory Device Array Handle: 0x0007 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: SODIMM2 Bank Locator: Bank 1 Type: DDR3 Type Detail: Unknown Handle 0x000B, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00100000000 Ending Address: 0x001FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x000A Memory Array Mapped Address Handle: 0x000C Partition Row Position: Unknown Interleave Position: Unknown Interleaved Data Depth: Unknown Handle 0x000C, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001FFFFFFFF Range Size: 8 GB Physical Array Handle: 0x0007 Partition Width: 2 Handle 0x000D, DMI type 4, 35 bytes Processor Information Socket Designation: N/A Type: Central Processor Family: Core 2 Duo Manufacturer: GenuineIntel ID: 52 06 02 00 FF FB EB BF Signature: Type 0, Family 6, Model 37, Stepping 2 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) DS (Debug store) ACPI (ACPI supported) MMX (MMX technology supported) FXSR (FXSAVE and FXSTOR instructions supported) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) SS (Self-snoop) HTT (Multi-threading) TM (Thermal monitor supported) PBE (Pending break enabled) Version: Intel(R) Core(TM) i3 CPU M 350 @ 2.27GHz Voltage: 1.5 V External Clock: 133 MHz Max Speed: 2266 MHz Current Speed: 2266 MHz Status: Populated, Enabled Upgrade: None L1 Cache Handle: 0x0010 L2 Cache Handle: 0x000F L3 Cache Handle: 0x000E Serial Number: N/A Asset Tag: N/A Part Number: N/A Handle 0x000E, DMI type 7, 19 bytes Cache Information Socket Designation: L3 Cache Configuration: Enabled, Socketed, Level 3 Operational Mode: Write Through Location: Internal Installed Size: 3072 kB Maximum Size: 3072 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 12-way Set-associative Handle 0x000F, DMI type 7, 19 bytes Cache Information Socket Designation: L2 Cache Configuration: Enabled, Socketed, Level 2 Operational Mode: Write Through Location: Internal Installed Size: 512 kB Maximum Size: 512 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 8-way Set-associative Handle 0x0010, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Socketed, Level 1 Operational Mode: Write Through Location: Internal Installed Size: 128 kB Maximum Size: 128 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Other Associativity: Other Handle 0x0011, DMI type 127, 4 bytes End Of Table -------------- next part -------------- EC RAM: 00: 20 80 05 00 00 00 00 00 00 00 00 00 00 00 00 00 10: 00 00 11 03 11 03 d0 00 00 00 16 1c a5 04 50 2d 20: 42 50 53 32 31 41 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 02 14 f0 00 40: a3 03 24 75 81 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 2d 01 2d ff 00 00 5c 00 60: 00 c2 08 f0 00 32 00 00 01 00 f0 00 00 00 00 80 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 99 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 02 00 00 00 05 00 03 14 a0: ff ff ff ff 55 00 55 00 00 00 01 00 50 00 0f ff b0: 00 00 00 00 80 00 00 00 00 03 00 00 00 01 00 00 c0: 00 00 00 00 00 00 84 0a 00 22 00 07 18 00 00 00 d0: 0c 50 00 00 03 00 83 00 00 06 00 06 00 63 0f 68 e0: 00 00 00 00 00 00 00 00 00 02 20 00 01 01 00 00 f0: 00 00 18 99 58 0e 00 00 00 00 00 20 00 00 00 02 Not dumping EC IDX RAM. -------------- next part -------------- flashrom v0.9.4-r1488 on Linux 3.2.2-1-ARCH (x86_64), built with libpci 3.1.8, GCC 4.6.2 20120120 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1107M loops per second, 10 myus = 12 us, 100 myus = 119 us, 1000 myus = 992 us, 10000 myus = 11195 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Sony Corporation" DMI string system-product-name: "VPCS11X9E" DMI string system-version: "C104F18B" DMI string baseboard-manufacturer: "Sony Corporation" DMI string baseboard-product-name: "VAIO" DMI string baseboard-version: "N/A" DMI string chassis-type: "Notebook" Laptop detected via DMI. Found chipset "Intel HM55" with PCI ID 8086:3b09. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom at flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x0 0xffe00000/0xffa00000 FWH IDSEL: 0x0 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x200000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0x61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00001000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x00000fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x03ff0001 (FREG2: Management Engine) 0x00001000-0x003fffff is locked 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf80000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q32" (4096 kB, SPI). No operations were specified. Restoring MMIO space at 0x7f433b2628a0 Restoring MMIO space at 0x7f433b26289c Restoring MMIO space at 0x7f433b262898 Restoring MMIO space at 0x7f433b262896 Restoring MMIO space at 0x7f433b262894 Restoring PCI config space for 00:1f:0 reg 0xdc -------------- next part -------------- flashrom v0.9.4-r1488 on Linux 3.2.2-1-ARCH (x86_64), built with libpci 3.1.8, GCC 4.6.2 20120120 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1103M loops per second, 10 myus = 10 us, 100 myus = 97 us, 1000 myus = 975 us, 10000 myus = 10118 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Sony Corporation" DMI string system-product-name: "VPCS11X9E" DMI string system-version: "C104F18B" DMI string baseboard-manufacturer: "Sony Corporation" DMI string baseboard-product-name: "VAIO" DMI string baseboard-version: "N/A" DMI string chassis-type: "Notebook" Laptop detected via DMI. Found chipset "Intel HM55" with PCI ID 8086:3b09. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom at flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x0 0xffe00000/0xffa00000 FWH IDSEL: 0x0 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x200000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0x61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x00000fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x03ff0001 (FREG2: Management Engine) 0x00001000-0x003fffff is locked 0x60: 0x00000fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25LF040A, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x15, id2 0x15 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Chip status register is 00 Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x15 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x6a, id2 0x08, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q32" (4096 kB, SPI). Reading flash... SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). FAILED. Restoring MMIO space at 0x7f37808e08a0 Restoring MMIO space at 0x7f37808e089c Restoring MMIO space at 0x7f37808e0898 Restoring MMIO space at 0x7f37808e0896 Restoring MMIO space at 0x7f37808e0894 Restoring PCI config space for 00:1f:0 reg 0xdc -------------- next part -------------- Intel CPU: Processor Type: 0, Family 6, Model 25, Stepping 2 Intel Northbridge: 8086:0044 (unknown) Intel Southbridge: 8086:3b09 (unknown) ============= GPIOS ============= Error: Dumping GPIOs on this southbridge is not (yet) supported. ============= RCBA ============== Error: Dumping RCBA on this southbridge is not (yet) supported. ============= PMBASE ============ Error: Dumping PMBASE on this southbridge is not (yet) supported. ============= MCHBAR ============ Error: Dumping MCHBAR on this northbridge is not (yet) supported. ============= EPBAR ============= Error: Dumping EPBAR on this northbridge is not (yet) supported. ============= DMIBAR ============ Error: Dumping DMIBAR on this northbridge is not (yet) supported. ========= PCIEXBAR ======== Error: Dumping PCIEXBAR on this northbridge is not (yet) supported. Error: Dumping MSRs on this CPU (0x020650) is not (yet) supported. -------------- next part -------------- 00:00.0 Host bridge [0600]: Intel Corporation Core Processor DRAM Controller [8086:0044] (rev 02) Subsystem: Sony Corporation Device [104d:9069] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- Kernel driver in use: agpgart-intel 00: 86 80 44 00 06 00 90 20 02 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4d 10 69 90 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 50: 00 00 80 03 09 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 80 d1 fe 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 7f 00 8e 00 00 00 00 00 a0: 80 00 c0 23 00 00 00 b8 00 00 e0 b7 00 00 80 b3 b0: 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 03 03 00 00 00 00 00 00 00 00 00 ff e0: 09 00 0c 01 26 61 b1 00 88 00 40 01 00 00 00 00 f0: 00 00 00 00 0d 00 00 00 ab 0f 14 00 00 00 00 00 100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1d0: 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 VGA compatible controller [0300]: Intel Corporation Core Processor Integrated Graphics Controller [8086:0046] (rev 02) (prog-if 00 [VGA controller]) Subsystem: Sony Corporation Device [104d:9069] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0f00c Data: 4159 Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: i915 00: 86 80 46 00 07 04 90 00 02 00 00 03 00 00 00 00 10: 04 00 00 d0 00 00 00 00 0c 00 00 c0 00 00 00 00 20: 51 70 00 00 00 00 00 00 00 00 00 00 4d 10 69 90 30: 00 00 00 00 90 00 00 00 00 00 00 00 07 01 00 00 40: 09 00 0c 01 26 61 b1 00 88 00 40 01 0f 17 14 17 50: 00 00 80 03 09 00 00 00 00 00 00 00 00 00 00 b8 60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 05 d0 01 00 0c f0 e0 fe 59 41 00 00 00 00 00 00 a0: 11 11 11 00 13 00 06 03 00 00 14 60 25 04 3a 30 b0: 00 00 00 00 00 00 00 00 00 02 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 a4 22 00 00 00 00 00 00 00 00 00 00 01 02 00 e0: 00 00 00 00 01 00 00 00 00 80 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 ab 0f 14 00 18 90 76 b3 00:16.0 Communication controller [0780]: Intel Corporation 5 Series/3400 Series Chipset HECI Controller [8086:3b64] (rev 06) Subsystem: Sony Corporation Device [104d:9069] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #0, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BC, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: Sony Corporation Device [104d:9069] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pcieport 00: 86 80 42 3b 07 00 10 00 05 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 60 60 00 20 20: 40 da 30 db 41 d0 31 d1 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 11 2c 11 01 50: 42 00 11 30 60 b2 04 00 08 00 40 00 00 00 00 00 60: 00 00 00 00 16 00 00 00 10 00 00 00 00 00 00 00 70: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 0d a0 00 00 4d 10 69 90 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 10 00 00 01 00 00 00 00 00 11 c0 00 00 00 00 e0: 00 0f 00 00 06 07 08 00 31 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 87 0f 06 08 00 00 00 00 100: 00 00 00 00 00 00 00 00 00 40 00 00 11 00 06 00 110: 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 00 120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 300: 80 08 e3 06 70 00 00 00 00 40 00 00 00 00 00 00 310: 01 15 00 00 00 00 00 36 07 01 01 00 00 00 16 00 320: 5b 60 c9 c0 40 70 26 76 30 13 b8 04 2f 03 00 0b 330: 16 00 00 14 b5 bc 4a bc 13 2a 00 00 00 00 00 00 340: cc 08 cc 00 dc 08 ce 00 11 08 a2 00 8e 00 bc 00 350: 90 00 be 00 01 00 ac 00 0f 0c a8 00 00 00 00 00 360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 400: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 410: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 470: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 490: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 510: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 530: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 570: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 580: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 590: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5f0: 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 730: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 740: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 750: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 760: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 770: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 780: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 790: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 800: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 810: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 820: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 830: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 890: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 8f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 900: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 910: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 920: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 930: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 940: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 950: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 960: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 970: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 980: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 990: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 aa0: 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 be0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bf0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ca0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ce0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cf0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 da0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 db0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 de0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 df0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1c.1 PCI bridge [0604]: Intel Corporation 5 Series/3400 Series Chipset PCI Express Root Port 2 [8086:3b44] (rev 05) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #1, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BC, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: Sony Corporation Device [104d:9069] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pcieport 00: 86 80 44 3b 07 00 10 00 05 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 50 50 00 20 20: 40 d9 30 da 41 d1 31 d2 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1c.2 PCI bridge [0604]: Intel Corporation 5 Series/3400 Series Chipset PCI Express Root Port 3 [8086:3b46] (rev 05) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #2, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BC, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: Sony Corporation Device [104d:9069] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pcieport 00: 86 80 46 3b 07 00 10 00 05 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 40 40 00 00 20: 40 d8 30 d9 41 d2 31 d3 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 03 00 00 40: 10 80 42 01 00 80 00 00 00 00 11 00 11 2c 11 03 50: 42 00 11 30 60 b2 14 00 00 00 40 00 00 00 00 00 60: 00 00 00 00 16 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1c.3 PCI bridge [0604]: Intel Corporation 5 Series/3400 Series Chipset PCI Express Root Port 4 [8086:3b48] (rev 05) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #3, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BC, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: Sony Corporation Device [104d:9069] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pcieport 00: 86 80 48 3b 07 00 10 00 05 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 30 30 00 20 20: 40 d7 30 d8 41 d3 31 d4 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 04 00 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 11 4c 11 04 50: 02 00 01 10 60 b2 1c 00 08 00 00 00 00 00 00 00 60: 00 00 00 00 16 00 00 00 10 00 00 00 00 00 00 00 70: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 0d a0 00 00 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00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1c.4 PCI bridge [0604]: Intel Corporation 5 Series/3400 Series Chipset PCI Express Root Port 5 [8086:3b4a] (rev 05) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #4, PowerLimit 10.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BC, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [90] Subsystem: Sony Corporation Device [104d:9069] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pcieport 00: 86 80 4a 3b 07 00 10 00 05 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 06 0d 00 20 20 00 20 20: 40 d5 30 d7 41 d4 31 d5 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 11 4c 11 05 50: 00 00 01 10 60 b2 24 00 08 00 00 00 00 00 00 00 60: 00 00 00 00 16 00 00 00 10 00 00 00 00 00 00 00 70: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 0d a0 00 00 4d 10 69 90 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 de0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 df0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1d.0 USB controller [0c03]: Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b34] (rev 05) (prog-if 20 [EHCI]) Subsystem: Sony Corporation Device [104d:9069] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: Sony Corporation Device [104d:9069] 00: 86 80 48 24 07 00 10 00 a5 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 10 10 20 f0 00 80 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 10 50: 0d 00 00 00 4d 10 69 90 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 87 0f 06 08 00 00 00 00 00:1f.0 ISA bridge [0601]: Intel Corporation Mobile 5 Series Chipset LPC Interface Controller [8086:3b09] (rev 05) Subsystem: Sony Corporation Device [104d:9069] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- 00: 86 80 09 3b 07 00 10 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4d 10 69 90 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 04 00 00 80 00 00 00 01 05 00 00 10 00 00 00 50: f8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 07 0a 0b 07 90 00 00 00 80 0b 0b 0a f8 00 00 00 70: f8 00 f8 00 f8 00 f8 00 f8 00 f8 00 f8 00 f8 00 80: 10 00 00 3f 00 00 00 00 01 06 3c 00 69 00 04 00 90: 00 00 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 a0: 04 06 20 00 00 00 02 00 00 45 00 20 00 03 00 80 b0: 00 00 00 00 00 00 00 00 00 a0 02 08 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 00 00 67 45 00 00 cf ff 00 00 08 00 00 00 e0: 09 00 10 11 f1 0a e4 0e 40 b7 46 58 06 24 b8 02 f0: 01 c0 d1 fe 00 00 00 00 87 0f 06 08 00 00 00 00 00:1f.2 SATA controller [0106]: Intel Corporation 5 Series/3400 Series Chipset 4 port SATA AHCI Controller [8086:3b29] (rev 05) (prog-if 01 [AHCI 1.0]) Subsystem: Sony Corporation Device [104d:9069] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Message-ID: the following patch was just integrated into master: commit 384c255400a042a075692c71e33e3de5718ec6c0 Author: Ky?sti M?lkki Date: Tue Feb 7 23:50:17 2012 +0200 Remove no-op Makefiles under mainboard directory Patch removes following files: src/mainboard/amd/serengeti_cheetah/Makefile.inc src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc src/mainboard/broadcom/blast/Makefile.inc src/mainboard/hp/dl145_g1/Makefile.inc src/mainboard/msi/ms9282/Makefile.inc src/mainboard/supermicro/h8dme/Makefile.inc src/mainboard/tyan/s2881/Makefile.inc src/mainboard/tyan/s2892/Makefile.inc src/mainboard/via/epia-m700/Makefile.inc Change-Id: I020776313abff1772be38afc896af51ca5ab6453 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Tue Feb 7 23:13:39 2012, giving +1 Reviewed-By: Stefan Reinauer at Thu Feb 9 01:38:26 2012, giving +2 See http://review.coreboot.org/612 for details. -gerrit From peter at stuge.se Thu Feb 9 12:06:46 2012 From: peter at stuge.se (Peter Stuge) Date: Thu, 9 Feb 2012 12:06:46 +0100 Subject: [coreboot] sony vaio (VPCS12X9E) In-Reply-To: References: Message-ID: <20120209110646.27090.qmail@stuge.se> Hi Jan, Jan Berce wrote: > I have seen your tutorial for gethering information Where was that exactly? > I have attached all other files and I hope they will be some help > to you in your progress. No, it's just noise, and we should work to change any tutorial that suggests otherwise. Helpful is contributed development time and to a much much lesser degree spare hardware. > 00:00.0 Host bridge [0600]: Intel Corporation Core Processor DRAM Controller [8086:0044] (rev 02) Nehalem is currently not supported at all. > 00:16.0 Communication controller [0780]: Intel Corporation 5 Series/3400 Series Chipset HECI Controller [8086:3b64] (rev 06) 3400 is also not supported. > ff:00.0 Host bridge [0600]: Intel Corporation Core Processor QuickPath Architecture Generic Non-core Registers [8086:2c62] (rev 02) And indeed, QPI is not supported. If you want to work on this platform please calculate years of effort. //Peter From gerrit at coreboot.org Thu Feb 9 12:23:03 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 9 Feb 2012 12:23:03 +0100 Subject: [coreboot] New patch to review for coreboot: 79de936 AMD and VIA cpus : Rename Kconfig directives References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/613 -gerrit commit 79de93607292082c3e9e3662c1d585050aad9616 Author: Ky?sti M?lkki Date: Tue Feb 7 23:28:05 2012 +0200 AMD and VIA cpus : Rename Kconfig directives Apply the un-written naming rule: Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147 Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/Makefile.inc | 6 +++--- src/cpu/amd/model_gx1/Kconfig | 7 ++++--- src/cpu/amd/model_gx2/Kconfig | 7 +++---- src/cpu/amd/model_lx/Kconfig | 6 +++--- src/cpu/via/Makefile.inc | 4 ++-- src/cpu/via/model_c3/Kconfig | 9 ++++++++- src/cpu/via/model_c7/Kconfig | 10 ++++------ src/include/lib.h | 2 +- src/mainboard/aaeon/pfm-540i_revb/Kconfig | 2 +- src/mainboard/advantech/pcm-5820/Kconfig | 2 +- src/mainboard/amd/db800/Kconfig | 2 +- src/mainboard/amd/norwich/Kconfig | 2 +- src/mainboard/amd/rumba/Kconfig | 2 +- src/mainboard/artecgroup/dbe61/Kconfig | 2 +- src/mainboard/asi/mb_5blgp/Kconfig | 2 +- src/mainboard/asi/mb_5blmp/Kconfig | 2 +- src/mainboard/axus/tc320/Kconfig | 2 +- src/mainboard/bcom/winnet100/Kconfig | 2 +- src/mainboard/bcom/winnetp680/Kconfig | 2 +- src/mainboard/digitallogic/msm800sev/Kconfig | 2 +- src/mainboard/eaglelion/5bcm/Kconfig | 2 +- src/mainboard/iei/juki-511p/Kconfig | 2 +- src/mainboard/iei/nova4899r/Kconfig | 2 +- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 2 +- src/mainboard/jetway/j7f24/Kconfig | 2 +- src/mainboard/lippert/frontrunner/Kconfig | 2 +- src/mainboard/lippert/hurricane-lx/Kconfig | 2 +- src/mainboard/lippert/literunner-lx/Kconfig | 2 +- src/mainboard/lippert/roadrunner-lx/Kconfig | 2 +- src/mainboard/lippert/spacerunner-lx/Kconfig | 2 +- src/mainboard/pcengines/alix1c/Kconfig | 2 +- src/mainboard/pcengines/alix2d/Kconfig | 2 +- src/mainboard/televideo/tc7020/Kconfig | 2 +- src/mainboard/traverse/geos/Kconfig | 2 +- src/mainboard/via/epia-cn/Kconfig | 2 +- src/mainboard/via/epia-m/Kconfig | 2 +- src/mainboard/via/epia-m700/Kconfig | 2 +- src/mainboard/via/epia-n/Kconfig | 2 +- src/mainboard/via/epia/Kconfig | 2 +- src/mainboard/via/pc2500e/Kconfig | 2 +- src/mainboard/via/vt8454c/Kconfig | 2 +- src/mainboard/winent/pl6064/Kconfig | 2 +- src/mainboard/wyse/s50/Kconfig | 2 +- 43 files changed, 63 insertions(+), 58 deletions(-) diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index e695473..c7ff51d 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -8,9 +8,9 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32 -subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 -subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 -subdirs-$(CONFIG_CPU_AMD_LX) += model_lx +subdirs-$(CONFIG_CPU_AMD_MODEL_GX1) += model_gx1 +subdirs-$(CONFIG_CPU_AMD_MODEL_GX2) += model_gx2 +subdirs-$(CONFIG_CPU_AMD_MODEL_LX) += model_lx subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 diff --git a/src/cpu/amd/model_gx1/Kconfig b/src/cpu/amd/model_gx1/Kconfig index c1c9b28..54e62ee 100644 --- a/src/cpu/amd/model_gx1/Kconfig +++ b/src/cpu/amd/model_gx1/Kconfig @@ -17,16 +17,17 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config CPU_AMD_GX1 +config CPU_AMD_MODEL_GX1 bool +if CPU_AMD_MODEL_GX1 + config DCACHE_RAM_BASE hex default 0xc0000 - depends on CPU_AMD_GX1 config DCACHE_RAM_SIZE hex default 0x01000 - depends on CPU_AMD_GX1 +endif # CPU_AMD_MODEL_GX1 diff --git a/src/cpu/amd/model_gx2/Kconfig b/src/cpu/amd/model_gx2/Kconfig index 4515a71..c7c0c84 100644 --- a/src/cpu/amd/model_gx2/Kconfig +++ b/src/cpu/amd/model_gx2/Kconfig @@ -17,10 +17,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config CPU_AMD_GX2 +config CPU_AMD_MODEL_GX2 bool -if CPU_AMD_GX2 +if CPU_AMD_MODEL_GX2 config CPU_SPECIFIC_OPTIONS def_bool y @@ -55,5 +55,4 @@ config VSA_FILENAME help The path and filename of the file to use as VSA. -endif # CPU_AMD_GX2 - +endif # CPU_AMD_MODEL_GX2 diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/model_lx/Kconfig index 742ef69..593f15a 100644 --- a/src/cpu/amd/model_lx/Kconfig +++ b/src/cpu/amd/model_lx/Kconfig @@ -1,7 +1,7 @@ -config CPU_AMD_LX +config CPU_AMD_MODEL_LX bool -if CPU_AMD_LX +if CPU_AMD_MODEL_LX config CPU_SPECIFIC_OPTIONS def_bool y @@ -36,4 +36,4 @@ config VSA_FILENAME help The path and filename of the file to use as VSA. -endif # CPU_AMD_LX +endif # CPU_AMD_MODEL_LX diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 512f82b..472b8dd 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,3 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += model_c7 -subdirs-$(CONFIG_CPU_VIA_C3) += model_c3 +subdirs-$(CONFIG_CPU_VIA_MODEL_C7) += model_c7 +subdirs-$(CONFIG_CPU_VIA_MODEL_C3) += model_c3 diff --git a/src/cpu/via/model_c3/Kconfig b/src/cpu/via/model_c3/Kconfig index d613909..49a3395 100644 --- a/src/cpu/via/model_c3/Kconfig +++ b/src/cpu/via/model_c3/Kconfig @@ -1,4 +1,11 @@ -config CPU_VIA_C3 +config CPU_VIA_MODEL_C3 bool + +if CPU_VIA_MODEL_C3 + +config CPU_SPECIFIC_OPTIONS + def_bool y select UDELAY_TSC select MMX + +endif # CPU_VIA_MODEL_C3 diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig index 8e6f0e8..7790ecc 100644 --- a/src/cpu/via/model_c7/Kconfig +++ b/src/cpu/via/model_c7/Kconfig @@ -1,9 +1,9 @@ -config CPU_VIA_C7 +config CPU_VIA_MODEL_C7 bool -if CPU_VIA_C7 +if CPU_VIA_MODEL_C7 -config CPU_SPECFIC_OPTIONS +config CPU_SPECIFIC_OPTIONS def_bool y select UDELAY_TSC select MMX @@ -13,11 +13,9 @@ config CPU_SPECFIC_OPTIONS config DCACHE_RAM_BASE hex default 0xffef0000 - depends on CPU_VIA_C7 config DCACHE_RAM_SIZE hex default 0x8000 - depends on CPU_VIA_C7 -endif # CPU_VIA_C7 +endif # CPU_VIA_MODEL_C7 diff --git a/src/include/lib.h b/src/include/lib.h index bbe735f..346a1f9 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -41,7 +41,7 @@ int ram_check_nodie(unsigned long start, unsigned long stop); void quick_ram_check(void); /* Defined in romstage.c */ -#if CONFIG_CPU_AMD_LX +#if CONFIG_CPU_AMD_MODEL_LX void cache_as_ram_main(void); #else void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig index 3b31ffb..598fcbf 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig +++ b/src/mainboard/aaeon/pfm-540i_revb/Kconfig @@ -3,7 +3,7 @@ if BOARD_AAEON_PFM_540I_REVB config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_SMSC_SMSCSUPERIO diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig index 7c87e28..d68def8 100644 --- a/src/mainboard/advantech/pcm-5820/Kconfig +++ b/src/mainboard/advantech/pcm-5820/Kconfig @@ -21,7 +21,7 @@ if BOARD_ADVANTECH_PCM_5820 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977F diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig index 834e085..4ed5b26 100644 --- a/src/mainboard/amd/db800/Kconfig +++ b/src/mainboard/amd/db800/Kconfig @@ -3,7 +3,7 @@ if BOARD_AMD_DB800 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig index b265eeb..ad123a2 100644 --- a/src/mainboard/amd/norwich/Kconfig +++ b/src/mainboard/amd/norwich/Kconfig @@ -3,7 +3,7 @@ if BOARD_AMD_NORWICH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index 0477f32..253f45d 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -21,7 +21,7 @@ if BOARD_AMD_RUMBA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX2 + select CPU_AMD_MODEL_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 select UDELAY_TSC diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig index 846000c..f3df1f6 100644 --- a/src/mainboard/artecgroup/dbe61/Kconfig +++ b/src/mainboard/artecgroup/dbe61/Kconfig @@ -3,7 +3,7 @@ if BOARD_ARTECGROUP_DBE61 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig index 5278369..96cadab 100644 --- a/src/mainboard/asi/mb_5blgp/Kconfig +++ b/src/mainboard/asi/mb_5blgp/Kconfig @@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLGP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC87351 diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig index 5b3b5bd..9a35b43 100644 --- a/src/mainboard/asi/mb_5blmp/Kconfig +++ b/src/mainboard/asi/mb_5blmp/Kconfig @@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLMP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC87351 diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig index dde2a36..84aa1e1 100644 --- a/src/mainboard/axus/tc320/Kconfig +++ b/src/mainboard/axus/tc320/Kconfig @@ -21,7 +21,7 @@ if BOARD_AXUS_TC320 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig index dbb2cb8..de18392 100644 --- a/src/mainboard/bcom/winnet100/Kconfig +++ b/src/mainboard/bcom/winnet100/Kconfig @@ -21,7 +21,7 @@ if BOARD_BCOM_WINNET100 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/bcom/winnetp680/Kconfig b/src/mainboard/bcom/winnetp680/Kconfig index 78e014e..a48c82f 100644 --- a/src/mainboard/bcom/winnetp680/Kconfig +++ b/src/mainboard/bcom/winnetp680/Kconfig @@ -3,7 +3,7 @@ if BOARD_BCOM_WINNETP680 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C7 + select CPU_VIA_MODEL_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig index 444023b..599a03a 100644 --- a/src/mainboard/digitallogic/msm800sev/Kconfig +++ b/src/mainboard/digitallogic/msm800sev/Kconfig @@ -3,7 +3,7 @@ if BOARD_DIGITALLOGIC_MSM800SEV config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/eaglelion/5bcm/Kconfig b/src/mainboard/eaglelion/5bcm/Kconfig index 65dd802..0d8f746 100644 --- a/src/mainboard/eaglelion/5bcm/Kconfig +++ b/src/mainboard/eaglelion/5bcm/Kconfig @@ -21,7 +21,7 @@ if BOARD_EAGLELION_5BCM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/iei/juki-511p/Kconfig b/src/mainboard/iei/juki-511p/Kconfig index d948929..efbec9f 100644 --- a/src/mainboard/iei/juki-511p/Kconfig +++ b/src/mainboard/iei/juki-511p/Kconfig @@ -21,7 +21,7 @@ if BOARD_IEI_JUKI_511P config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977F diff --git a/src/mainboard/iei/nova4899r/Kconfig b/src/mainboard/iei/nova4899r/Kconfig index 3cc5ddb..4a0e928 100644 --- a/src/mainboard/iei/nova4899r/Kconfig +++ b/src/mainboard/iei/nova4899r/Kconfig @@ -21,7 +21,7 @@ if BOARD_IEI_NOVA_4899R config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977TF diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index e393609..eff5247 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -3,7 +3,7 @@ if BOARD_IEI_PCISA_LX_800_R10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/jetway/j7f24/Kconfig b/src/mainboard/jetway/j7f24/Kconfig index fa17eba..402f359 100644 --- a/src/mainboard/jetway/j7f24/Kconfig +++ b/src/mainboard/jetway/j7f24/Kconfig @@ -4,7 +4,7 @@ if BOARD_JETWAY_J7F24 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C7 + select CPU_VIA_MODEL_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_FINTEK_F71805F diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig index 4e8cee0..fe5d31c 100644 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ b/src/mainboard/lippert/frontrunner/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_FRONTRUNNER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX2 + select CPU_AMD_MODEL_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 select HAVE_DEBUG_SMBUS diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 9b20aa0..f8c1910 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_HURRICANE_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 7b45d36..0a46736 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_LITERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 4e29742..b8c4bbb 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_ROADRUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index f273d6c..917f38a 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_SPACERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 0a016a5..93f1608 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX1C config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..81fa594 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX2D config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig index b3233d9..2c34946 100644 --- a/src/mainboard/televideo/tc7020/Kconfig +++ b/src/mainboard/televideo/tc7020/Kconfig @@ -21,7 +21,7 @@ if BOARD_TELEVIDEO_TC7020 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_MODEL_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index dd6c8dd..640f451 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -3,7 +3,7 @@ if BOARD_TRAVERSE_GEOS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig index e7920e7..9cd5adf 100644 --- a/src/mainboard/via/epia-cn/Kconfig +++ b/src/mainboard/via/epia-cn/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_CN config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C7 + select CPU_VIA_MODEL_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_VIA_VT1211 diff --git a/src/mainboard/via/epia-m/Kconfig b/src/mainboard/via/epia-m/Kconfig index bf7f13d..6359f5e 100644 --- a/src/mainboard/via/epia-m/Kconfig +++ b/src/mainboard/via/epia-m/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_M config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C3 + select CPU_VIA_MODEL_C3 select NORTHBRIDGE_VIA_VT8623 select SOUTHBRIDGE_VIA_VT8235 select SOUTHBRIDGE_RICOH_RL5C476 diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig index 4396cc3..c0ccdf1 100644 --- a/src/mainboard/via/epia-m700/Kconfig +++ b/src/mainboard/via/epia-m700/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_M700 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C7 + select CPU_VIA_MODEL_C7 select NORTHBRIDGE_VIA_VX800 select SUPERIO_WINBOND_W83697HF select BOARD_HAS_FADT diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 4806753..8ef508d 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_N config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C3 + select CPU_VIA_MODEL_C3 select NORTHBRIDGE_VIA_CN400 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF diff --git a/src/mainboard/via/epia/Kconfig b/src/mainboard/via/epia/Kconfig index 60ce4f5..9aa409c 100644 --- a/src/mainboard/via/epia/Kconfig +++ b/src/mainboard/via/epia/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_EPIA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C3 + select CPU_VIA_MODEL_C3 select NORTHBRIDGE_VIA_VT8601 select SOUTHBRIDGE_VIA_VT8231 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig index 70aa8d7..1f38cdc 100644 --- a/src/mainboard/via/pc2500e/Kconfig +++ b/src/mainboard/via/pc2500e/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_PC2500E config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C7 + select CPU_VIA_MODEL_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_ITE_IT8716F diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index c9a0105..3475230 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -3,7 +3,7 @@ if BOARD_VIA_VT8454C config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_VIA_C7 + select CPU_VIA_MODEL_C7 select NORTHBRIDGE_VIA_CX700 select SUPERIO_VIA_VT1211 select BOARD_HAS_FADT diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig index 4f367f1..17ddad0 100644 --- a/src/mainboard/winent/pl6064/Kconfig +++ b/src/mainboard/winent/pl6064/Kconfig @@ -3,7 +3,7 @@ if BOARD_WINENT_PL6064 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_MODEL_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig index dff01f9..586a661 100644 --- a/src/mainboard/wyse/s50/Kconfig +++ b/src/mainboard/wyse/s50/Kconfig @@ -21,7 +21,7 @@ if BOARD_WYSE_S50 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX2 + select CPU_AMD_MODEL_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 select UDELAY_TSC From gerrit at coreboot.org Thu Feb 9 15:08:33 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 9 Feb 2012 15:08:33 +0100 Subject: [coreboot] Patch set updated for coreboot: 1a82de2 AMD Geode cpus: apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/613 -gerrit commit 1a82de2b58c285fed98ced2af76a61b02afba3ed Author: Ky?sti M?lkki Date: Thu Feb 9 16:07:41 2012 +0200 AMD Geode cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Rename directories and Kconfig as follows: model_lx -> geode_lx model_gx1 -> geode_gx1 model_gx2 -> geode_gx2 Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147 Signed-off-by: Ky?sti M?lkki --- src/cpu/amd/Kconfig | 6 +- src/cpu/amd/Makefile.inc | 6 +- src/cpu/amd/geode_gx1/Kconfig | 33 ++ src/cpu/amd/geode_gx1/Makefile.inc | 28 ++ src/cpu/amd/geode_gx1/cpu_setup.inc | 68 ++++ src/cpu/amd/geode_gx1/geode_gx1_init.c | 101 ++++++ src/cpu/amd/geode_gx1/gx_setup.inc | 47 +++ src/cpu/amd/geode_gx2/Kconfig | 58 ++++ src/cpu/amd/geode_gx2/Makefile.inc | 9 + src/cpu/amd/geode_gx2/cache_as_ram.inc | 208 ++++++++++++ src/cpu/amd/geode_gx2/cpubug.c | 349 ++++++++++++++++++++ src/cpu/amd/geode_gx2/cpureginit.c | 129 +++++++ src/cpu/amd/geode_gx2/geode_gx2_init.c | 46 +++ src/cpu/amd/geode_gx2/syspreinit.c | 20 ++ src/cpu/amd/geode_lx/Kconfig | 39 +++ src/cpu/amd/geode_lx/Makefile.inc | 9 + src/cpu/amd/geode_lx/cache_as_ram.inc | 234 +++++++++++++ src/cpu/amd/geode_lx/cpubug.c | 91 +++++ src/cpu/amd/geode_lx/cpureginit.c | 267 +++++++++++++++ src/cpu/amd/geode_lx/geode_lx_init.c | 74 ++++ src/cpu/amd/geode_lx/msrinit.c | 64 ++++ src/cpu/amd/geode_lx/syspreinit.c | 46 +++ src/cpu/amd/model_gx1/Kconfig | 32 -- src/cpu/amd/model_gx1/Makefile.inc | 28 -- src/cpu/amd/model_gx1/cpu_setup.inc | 68 ---- src/cpu/amd/model_gx1/gx_setup.inc | 47 --- src/cpu/amd/model_gx1/model_gx1_init.c | 101 ------ src/cpu/amd/model_gx2/Kconfig | 59 ---- src/cpu/amd/model_gx2/Makefile.inc | 9 - src/cpu/amd/model_gx2/cache_as_ram.inc | 208 ------------ src/cpu/amd/model_gx2/cpubug.c | 349 -------------------- src/cpu/amd/model_gx2/cpureginit.c | 129 ------- src/cpu/amd/model_gx2/model_gx2_init.c | 46 --- src/cpu/amd/model_gx2/syspreinit.c | 20 -- src/cpu/amd/model_lx/Kconfig | 39 --- src/cpu/amd/model_lx/Makefile.inc | 9 - src/cpu/amd/model_lx/cache_as_ram.inc | 234 ------------- src/cpu/amd/model_lx/cpubug.c | 91 ----- src/cpu/amd/model_lx/cpureginit.c | 267 --------------- src/cpu/amd/model_lx/model_lx_init.c | 74 ---- src/cpu/amd/model_lx/msrinit.c | 64 ---- src/cpu/amd/model_lx/syspreinit.c | 46 --- src/include/lib.h | 2 +- src/mainboard/aaeon/pfm-540i_revb/Kconfig | 2 +- src/mainboard/aaeon/pfm-540i_revb/devicetree.cb | 2 +- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 6 +- src/mainboard/advantech/pcm-5820/Kconfig | 2 +- src/mainboard/advantech/pcm-5820/devicetree.cb | 2 +- src/mainboard/amd/db800/Kconfig | 2 +- src/mainboard/amd/db800/devicetree.cb | 2 +- src/mainboard/amd/db800/romstage.c | 6 +- src/mainboard/amd/norwich/Kconfig | 2 +- src/mainboard/amd/norwich/devicetree.cb | 2 +- src/mainboard/amd/norwich/romstage.c | 6 +- src/mainboard/amd/rumba/Kconfig | 2 +- src/mainboard/amd/rumba/devicetree.cb | 2 +- src/mainboard/amd/rumba/romstage.c | 6 +- src/mainboard/artecgroup/dbe61/Kconfig | 2 +- src/mainboard/artecgroup/dbe61/devicetree.cb | 2 +- src/mainboard/artecgroup/dbe61/romstage.c | 6 +- src/mainboard/asi/mb_5blgp/Kconfig | 2 +- src/mainboard/asi/mb_5blgp/devicetree.cb | 2 +- src/mainboard/asi/mb_5blmp/Kconfig | 2 +- src/mainboard/asi/mb_5blmp/devicetree.cb | 2 +- src/mainboard/axus/tc320/Kconfig | 2 +- src/mainboard/axus/tc320/devicetree.cb | 2 +- src/mainboard/bcom/winnet100/Kconfig | 2 +- src/mainboard/bcom/winnet100/devicetree.cb | 2 +- src/mainboard/digitallogic/msm800sev/Kconfig | 2 +- src/mainboard/digitallogic/msm800sev/devicetree.cb | 2 +- src/mainboard/digitallogic/msm800sev/romstage.c | 6 +- src/mainboard/eaglelion/5bcm/Kconfig | 2 +- src/mainboard/eaglelion/5bcm/devicetree.cb | 2 +- src/mainboard/iei/juki-511p/Kconfig | 2 +- src/mainboard/iei/juki-511p/devicetree.cb | 2 +- src/mainboard/iei/nova4899r/Kconfig | 2 +- src/mainboard/iei/nova4899r/devicetree.cb | 2 +- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 2 +- src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb | 2 +- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 6 +- src/mainboard/lippert/frontrunner/Kconfig | 2 +- src/mainboard/lippert/frontrunner/devicetree.cb | 2 +- src/mainboard/lippert/frontrunner/romstage.c | 6 +- src/mainboard/lippert/hurricane-lx/Kconfig | 2 +- src/mainboard/lippert/hurricane-lx/devicetree.cb | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 6 +- src/mainboard/lippert/literunner-lx/Kconfig | 2 +- src/mainboard/lippert/literunner-lx/devicetree.cb | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 6 +- src/mainboard/lippert/roadrunner-lx/Kconfig | 2 +- src/mainboard/lippert/roadrunner-lx/devicetree.cb | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 6 +- src/mainboard/lippert/spacerunner-lx/Kconfig | 2 +- src/mainboard/lippert/spacerunner-lx/devicetree.cb | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 6 +- src/mainboard/pcengines/alix1c/Kconfig | 2 +- src/mainboard/pcengines/alix1c/devicetree.cb | 2 +- src/mainboard/pcengines/alix1c/romstage.c | 6 +- src/mainboard/pcengines/alix2d/Kconfig | 2 +- src/mainboard/pcengines/alix2d/devicetree.cb | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 6 +- src/mainboard/televideo/tc7020/Kconfig | 2 +- src/mainboard/televideo/tc7020/devicetree.cb | 2 +- src/mainboard/traverse/geos/Kconfig | 2 +- src/mainboard/traverse/geos/devicetree.cb | 2 +- src/mainboard/traverse/geos/romstage.c | 6 +- src/mainboard/winent/pl6064/Kconfig | 2 +- src/mainboard/winent/pl6064/devicetree.cb | 2 +- src/mainboard/winent/pl6064/romstage.c | 6 +- src/mainboard/wyse/s50/Kconfig | 2 +- src/mainboard/wyse/s50/devicetree.cb | 2 +- src/mainboard/wyse/s50/romstage.c | 6 +- 112 files changed, 2030 insertions(+), 2030 deletions(-) diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index 2f4ff33..dd78ca9 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -16,9 +16,9 @@ source src/cpu/amd/socket_S1G1/Kconfig source src/cpu/amd/model_fxx/Kconfig source src/cpu/amd/model_10xxx/Kconfig -source src/cpu/amd/model_gx1/Kconfig -source src/cpu/amd/model_gx2/Kconfig -source src/cpu/amd/model_lx/Kconfig +source src/cpu/amd/geode_gx1/Kconfig +source src/cpu/amd/geode_gx2/Kconfig +source src/cpu/amd/geode_lx/Kconfig source src/cpu/amd/sc520/Kconfig diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index e695473..2ea376a 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -8,9 +8,9 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32 -subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 -subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 -subdirs-$(CONFIG_CPU_AMD_LX) += model_lx +subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1 +subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2 +subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 diff --git a/src/cpu/amd/geode_gx1/Kconfig b/src/cpu/amd/geode_gx1/Kconfig new file mode 100644 index 0000000..4a90c26 --- /dev/null +++ b/src/cpu/amd/geode_gx1/Kconfig @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_AMD_GEODE_GX1 + bool + +if CPU_AMD_GEODE_GX1 + +config DCACHE_RAM_BASE + hex + default 0xc0000 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + +endif # CPU_AMD_GEODE_GX1 diff --git a/src/cpu/amd/geode_gx1/Makefile.inc b/src/cpu/amd/geode_gx1/Makefile.inc new file mode 100644 index 0000000..d5bb1ef --- /dev/null +++ b/src/cpu/amd/geode_gx1/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +driver-y += geode_gx1_init.c + +cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc +cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc diff --git a/src/cpu/amd/geode_gx1/cpu_setup.inc b/src/cpu/amd/geode_gx1/cpu_setup.inc new file mode 100644 index 0000000..d701f8d --- /dev/null +++ b/src/cpu/amd/geode_gx1/cpu_setup.inc @@ -0,0 +1,68 @@ +/* + freebios/src/northbridge/nsc/gx1/cpu_setup.inc + + Copyright (c) 2002 Christer Weinigel + + Initialize the GX1 CPU configuration registers +*/ + +/* USES: esi, ecx, eax */ + +#include + + movl %eax, %ebp /* preserve bist */ + +cpu_setup_start: + leal cpu_setup_table, %esi + movl $cpu_setup_len, %ecx + +cpu_setup_loop: + movw (%esi), %ax + addl $2, %esi + outb %al, $0x22 + movb %ah, %al + outb %al, $0x23 + loop cpu_setup_loop + + movb $0xff, %al /* DIR1 -- Identification Register 1 */ + outb %al, $0x22 + inb $0x23, %al + cmpb $0x63, %al /* Revision for GXLV rev 3 */ + jbe cpu_no_ccr4 + + movb $0xe8, %al /* CCR4 */ + outb %al, $0x22 + inb $0x23, %al + orb $0x20, %al /* Enable FPU Fast Mode */ + outb %al, $0x23 + + movb $0xf0, %al /* PCR1 --- Performace Control */ + outb %al, $0x22 + inb $0x23, %al + orb $0x02, %al /* Incrementor on, whatever that is */ + outb %al, $0x23 + + movb $0x20, %al /* PCR0 --- Performace Control */ + outb %al, $0x22 + inb $0x23, %al + orb $0x20, %al /* Must be 1 according to data book */ + orb $0x04, %al /* Incrementor Margin 10 */ + outb %al, $0x23 +cpu_no_ccr4: + + jmp cpu_setup_end + +cpu_setup_table: + .byte 0xc1, 0x00 /* NO SMIs */ + .byte 0xc3, 0x14 /* Enable CPU config register */ + .byte 0x20, 0x00 + .byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */ + .byte 0xc2, 0x00 + .byte 0xe8, 0x98 + .byte 0xc3, 0xf8 /* Enable CPU config register */ +cpu_setup_len = (.-cpu_setup_table)/2 + +cpu_setup_end: + nop + + movl %ebp, %eax /* Restore bist */ diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c new file mode 100644 index 0000000..60f9473 --- /dev/null +++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c @@ -0,0 +1,101 @@ +#include +#include +#include +#include +#include +#include +#include + +#if 0 +#include +#include + +static void gx1_cpu_setup(void) +{ + unsigned char rreg; + unsigned char cpu_table[] = { + 0xc1, 0x00, /* NO SMIs */ + 0xc3, 0x14, /* Enable CPU config register */ + 0x20, 0x00, /* */ + 0xb8, GX_BASE>>30, /* Enable GXBASE address */ + 0xc2, 0x00, + 0xe8, 0x98, + 0xc3, 0xf8, /* Enable CPU config register */ + 0x00, 0x00 + }; + unsigned char *cPtr = cpu_table; + + while(rreg = *cPtr++) { + unsigned char rval = *cPtr++; + outb(rreg, 0x22); + outb(rval, 0x23); + } + + outb(0xff, 0x22); /* DIR1 -- Identification register 1 */ + if(inb(0x23) > 0x63) { /* Rev greater than R3 */ + outb(0xe8, 0x22); + outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */ + + outb(0xf0, 0x22); + outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */ + + outb(0x20, 0x22); + outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */ + /* Bit 2 Incrementor margin 10 */ + + } +} + +static void gx1_gx_setup(void) +{ +unsigned long gx_setup_table[] = { + GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC, + GX_BASE + DC_GENERAL_CFG, 0, + GX_BASE + DC_UNLOCK, 0, + GX_BASE + BC_DRAM_TOP, 0x3fffffff, + GX_BASE + BC_XMAP_1, 0x60, + GX_BASE + BC_XMAP_2, 0, + GX_BASE + BC_XMAP_3, 0, + GX_BASE + MC_BANK_CFG, 0x00700070, + GX_BASE + MC_MEM_CNTRL1, XBUSARB, + GX_BASE + MC_GBASE_ADD, 0xff, + 0, 0 + }; + +unsigned long *gxPtr = gx_setup_table; +unsigned long *gxdPtr; +unsigned long addr; + + while(addr = *gxPtr++) { + gxdPtr = (unsigned long *)addr; + *gxdPtr = *gxPtr++; + } +} +#endif + +static void geode_gx1_init(device_t dev) +{ +#if 0 + gx1_cpu_setup(); + gx1_gx_setup(); +#endif + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Enable the local cpu apics */ + setup_lapic(); +}; + +static struct device_operations cpu_dev_ops = { + .init = geode_gx1_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_CYRIX, 0x0540 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/geode_gx1/gx_setup.inc b/src/cpu/amd/geode_gx1/gx_setup.inc new file mode 100644 index 0000000..6d0e289 --- /dev/null +++ b/src/cpu/amd/geode_gx1/gx_setup.inc @@ -0,0 +1,47 @@ +/* + freebios/src/northbridge/nsc/gx1/gx_setup.inc + + Copyright (c) 2002 Christer Weinigel + + Setup the GX_BASE registers on a National Semiconductor Geode CPU +*/ + +#include + + movl %eax, %ebp /* Preserve bist */ + +gx_setup_start: + leal gx_setup_table, %esi + movl $gx_setup_len, %ecx + movl $GX_BASE, %edi + +gx_setup_loop: + movw (%esi), %di /* Only read the low word of address */ + addl $4, %esi + movl (%esi), %eax /* Data */ + addl $4, %esi + movl %eax, (%edi) + loop gx_setup_loop + + jmp gx_setup_end + +gx_setup_table: + /* Allow writes to config registers */ + .long DC_UNLOCK, DC_UNLOCK_MAGIC + .long DC_GENERAL_CFG, 0 + .long DC_UNLOCK, 0 + + .long BC_DRAM_TOP, 0x3fffffff + .long BC_XMAP_1, 0x60 + .long BC_XMAP_2, 0 + .long BC_XMAP_3, 0 + + .long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */ + .long MC_MEM_CNTRL1, XBUSARB + .long MC_GBASE_ADD, 0x7ff /* Almost 1GB */ +gx_setup_len = (.-gx_setup_table)/8 + +gx_setup_end: + nop + + movl %ebp, %eax /* Restore bist */ diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig new file mode 100644 index 0000000..0e25542 --- /dev/null +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_AMD_GEODE_GX2 + bool + +if CPU_AMD_GEODE_GX2 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select CACHE_AS_RAM + +config DCACHE_RAM_BASE + hex + default 0xc8000 + +config DCACHE_RAM_SIZE + hex + default 0x04000 + +config GEODE_VSA + bool + default y + select PCI_OPTION_ROM_RUN_REALMODE + +config GEODE_VSA_FILE + bool "Add a VSA image" + help + Select this option if you have an AMD Geode GX2 vsa that you would + like to add to your ROM. + + You will be able to specify the location and file name of the + image later. + +config VSA_FILENAME + string "AMD Geode GX2 VSA path and filename" + depends on GEODE_VSA_FILE + default "gpl_vsa_gx_102.bin" + help + The path and filename of the file to use as VSA. + +endif # CPU_AMD_GEODE_GX2 diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc new file mode 100644 index 0000000..b70537a --- /dev/null +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -0,0 +1,9 @@ +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += geode_gx2_init.c +ramstage-y += cpubug.c + +cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc new file mode 100644 index 0000000..0af2fdf --- /dev/null +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) + +#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */ +#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ +#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ +#include +#include +/*************************************************************************** +/** +/** DCacheSetup +/** +/** Setup data cache for use as RAM for a stack. +/** +/** Max. size data cache =0x4000 (16KB) +/** +/***************************************************************************/ +DCacheSetup: + /* Save the BIST result */ + movl %eax, %ebx + + invd + /* set cache properties */ + movl $CPU_RCONF_DEFAULT, %ecx + rdmsr + movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ + wrmsr + + /* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */ + movl $CPU_DM_CONFIG0, %ecx + rdmsr + andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ + wrmsr + + /* Get cleaned up. */ + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ + /* remember, there is NO stack yet... */ + + /* Tell cache we want to fill WAY 0 starting at the top */ + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_INDEX, %ecx + wrmsr + + /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ + movl $GX2_STACK_BASE, %ebp /* init to start address */ + orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ + + /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ + movl $GX2_NUM_CACHELINES, %edi +DCacheSetupFillWay: + + /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ + /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ + movw $0x04, %si + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_DATA, %ecx +DCacheSetup_quadWordLoop: + wrmsr + decw %si + jnz DCacheSetup_quadWordLoop + + /* Set the tag for this line,need to do this for every new cache line to validate it! */ + /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ + xorl %edx, %edx + movl %ebp, %eax + movl $CPU_DC_TAG, %ecx + wrmsr + + /* switch to next line */ + /* lines are in Bits8:2 */ + /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */ + wrmsr + + decl %edi + jnz DCacheSetupFillWay + + /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ + addl $GX2_CACHEWAY_SIZE, %ebp + cmpl $GX2_STACK_END, %ebp + jge leave_DCacheSetup + movl $GX2_NUM_CACHELINES, %edi + + /* switch to next way */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x01, %eax + andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */ + wrmsr + + jmp DCacheSetupFillWay + +leave_DCacheSetup: + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ + /* Memory reads and writes will all hit in the cache. */ + /* Cache updates and memory write-backs will not occur ! */ + movl %cr0, %eax + orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ + movl %eax, %cr0 + + /* Now point sp to the cached stack. */ + /* The stack will be fully functional at this location. No system memory is required at all ! */ + /* set up the stack pointer */ + movl $GX2_STACK_END, %eax + movl %eax, %esp + + /* test the stack*/ + movl $0x0F0F05A5A, %edx + pushl %edx + popl %ecx + cmpl %ecx, %edx + je DCacheSetupGood + + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad +DCacheSetupGood: + /* Go do early init and memory setup */ + + /* Restore the BIST result */ + movl %ebx, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function */ + call main +done_cache_as_ram_main: + + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi + + /* Clear the cache out to ram */ + wbinvd + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + + /* TODO For suspend/resume the cache will have to live between + * CONFIG_RAMBASE and CONFIG_RAMTOP + */ + + cld /* clear direction flag */ + + /* copy coreboot from it's initial load location to + * the location it is compiled to run at. + * Normally this is copying from FLASH ROM to RAM. + */ + movl %ebp, %esi + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c new file mode 100644 index 0000000..473766c --- /dev/null +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -0,0 +1,349 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if 0 +void bug645(void) +{ + msr_t msr; + rdmsr(CPU_ID_CONFIG); + msr.whatever |= ID_CONFIG_SERIAL_SET; + wrmsr(msr); +} + +void bug573(void) +{ + msr_t msr; + msr = rdmsr(MC_GLD_MSR_PM); + msr.eax &= 0xfff3; + wrmsr(MC_GLD_MSR_PM); +} +#endif + +/* pcideadlock + * + * Bugtool #465 and #609 + * PCI cache deadlock + * There is also fix code in cache and PCI functions. This bug is very is pervasive. + */ +static void pcideadlock(void) +{ + msr_t msr; + + /* forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting + * for PCI writes to complete. + */ + msr = rdmsr(CPU_DM_CONFIG0); + msr.hi &= ~(7<= CPU_REV_2_1){ + msrnum = CPU_PF_BTB_CONF; + msr = rdmsr(msrnum); + msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET; + wrmsr(msrnum, msr); + } + +/* FPU impercise exceptions bit */ + { + msrnum = CPU_FPU_MSR_MODE; + msr = rdmsr(msrnum); + msr.lo |= FPU_IE_SET; + wrmsr(msrnum, msr); + } +} diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c new file mode 100644 index 0000000..7e481b5 --- /dev/null +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -0,0 +1,46 @@ +#include +#include +#include +#include +#include +#include +#include + +static void vsm_end_post_smi(void) +{ + __asm__ volatile ( + "push %ax\n" + "mov $0x5000, %ax\n" + ".byte 0x0f, 0x38\n" + "pop %ax\n" + ); +} + +static void geode_gx2_init(device_t dev) +{ + printk(BIOS_DEBUG, "geode_gx2_init\n"); + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Enable the local cpu apics */ + //setup_lapic(); + + vsm_end_post_smi(); + + printk(BIOS_DEBUG, "geode_gx2_init DONE\n"); +}; + +static struct device_operations cpu_dev_ops = { + .init = geode_gx2_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_NSC, 0x0552 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c new file mode 100644 index 0000000..8140348 --- /dev/null +++ b/src/cpu/amd/geode_gx2/syspreinit.c @@ -0,0 +1,20 @@ +/* StartTimer1 + * + * Entry: none + * Exit: Starts Timer 1 for port 61 use + * Destroys: Al, + */ +static void StartTimer1(void) +{ + outb(0x56, 0x43); + outb(0x12, 0x41); +} + +void SystemPreInit(void) +{ + /* they want a jump ... */ +#if !CONFIG_CACHE_AS_RAM + __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); +#endif + StartTimer1(); +} diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig new file mode 100644 index 0000000..e5462c6 --- /dev/null +++ b/src/cpu/amd/geode_lx/Kconfig @@ -0,0 +1,39 @@ +config CPU_AMD_GEODE_LX + bool + +if CPU_AMD_GEODE_LX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select CACHE_AS_RAM + +config DCACHE_RAM_BASE + hex + default 0xc8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config GEODE_VSA + bool + default y + select PCI_OPTION_ROM_RUN_REALMODE + +config GEODE_VSA_FILE + bool "Add a VSA image" + help + Select this option if you have an AMD Geode LX vsa that you would + like to add to your ROM. + + You will be able to specify the location and file name of the + image later. + +config VSA_FILENAME + string "AMD Geode LX VSA path and filename" + depends on GEODE_VSA_FILE + default "gpl_vsa_lx_102.bin" + help + The path and filename of the file to use as VSA. + +endif # CPU_AMD_GEODE_LX diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc new file mode 100644 index 0000000..a5e1281 --- /dev/null +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -0,0 +1,9 @@ +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += geode_lx_init.c +ramstage-y += cpubug.c + +cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc new file mode 100644 index 0000000..a1d775d --- /dev/null +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) + +#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ +#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ +#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ +#include +#include +/*************************************************************************** +/** +/** DCacheSetup +/** +/** Setup data cache for use as RAM for a stack. +/** +/***************************************************************************/ +DCacheSetup: + /* Save the BIST result */ + movl %eax, %ebx + + invd + /* set cache properties */ + movl $CPU_RCONF_DEFAULT, %ecx + rdmsr + movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ + wrmsr + + /* in LX DCDIS is set after POR which disables the cache..., clear this bit */ + movl CPU_DM_CONFIG0,%ecx + rdmsr + andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ + wrmsr + + /* get cache timing params from BIOS config data locations and apply */ + /* fix delay controls for DM and IM arrays */ + /* fix delay controls for DM and IM arrays */ + movl $CPU_BC_MSS_ARRAY_CTL0, %ecx + xorl %edx, %edx + movl $0x2814D352, %eax + wrmsr + + movl $CPU_BC_MSS_ARRAY_CTL1, %ecx + xorl %edx, %edx + movl $0x1068334D, %eax + wrmsr + + movl $CPU_BC_MSS_ARRAY_CTL2, %ecx + movl $0x00000106, %edx + movl $0x83104104, %eax + wrmsr + + movl $GLCP_FIFOCTL, %ecx + rdmsr + movl $0x00000005, %edx + wrmsr + + /* Enable setting */ + movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx + xorl %edx, %edx + movl $0x01, %eax + wrmsr + + /* Get cleaned up. */ + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ + /* remember, there is NO stack yet... */ + + /* Tell cache we want to fill WAY 0 starting at the top */ + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_INDEX, %ecx + wrmsr + + /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ + movl $LX_STACK_BASE, %ebp /* init to start address */ + orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ + + /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ + movl $LX_NUM_CACHELINES, %edi +DCacheSetupFillWay: + + /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ + /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ + movw $0x04, %si + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_DATA, %ecx +DCacheSetup_quadWordLoop: + wrmsr + decw %si + jnz DCacheSetup_quadWordLoop + + /* Set the tag for this line, need to do this for every new cache line to validate it! */ + /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ + xorl %edx, %edx + movl %ebp, %eax + movl $CPU_DC_TAG, %ecx + wrmsr + + /* switch to next line */ + /* lines are in Bits10:4 */ + /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */ + wrmsr + + decl %edi + jnz DCacheSetupFillWay + + /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ + addl $LX_CACHEWAY_SIZE, %ebp + cmpl $LX_STACK_END, %ebp + jge leave_DCacheSetup + movl $LX_NUM_CACHELINES, %edi + + /* switch to next way */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x01, %eax + andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */ + wrmsr + + jmp DCacheSetupFillWay + +leave_DCacheSetup: + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ + /* Memory reads and writes will all hit in the cache. */ + /* Cache updates and memory write-backs will not occur ! */ + movl %cr0, %eax + orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ + movl %eax, %cr0 + + /* Now point sp to the cached stack. */ + /* The stack will be fully functional at this location. No system memory is required at all ! */ + /* set up the stack pointer */ + movl $LX_STACK_END, %eax + movl %eax, %esp + + /* test the stack*/ + movl $0x0F0F05A5A, %edx + pushl %edx + popl %ecx + cmpl %ecx, %edx + je DCacheSetupGood + + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad +DCacheSetupGood: + /* Go do early init and memory setup */ + + /* Restore the BIST result */ + movl %ebx, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function */ + call main +done_cache_as_ram_main: + + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi + + /* Clear the cache out to ram */ + wbinvd + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + + /* TODO For suspend/resume the cache will have to live between + * CONFIG_RAMBASE and CONFIG_RAMTOP + */ + + cld /* clear direction flag */ + + /* copy coreboot from it's initial load location to + * the location it is compiled to run at. + * Normally this is copying from FLASH ROM to RAM. + */ + movl %ebp, %esi + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c new file mode 100644 index 0000000..e3b6e51 --- /dev/null +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Indrek Kruusa + * Copyright (C) 2006 Ronald G. Minnich + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************************** + * + * pcideadlock + * + * Bugtool #465 and #609 + * PCI cache deadlock + * There is also fix code in cache and PCI functions. This bug is very is pervasive. + * + **************************************************************************/ +static void pcideadlock(void) +{ + msr_t msr; + + /* + * forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting + * for PCI writes to complete. + */ + msr = rdmsr(CPU_DM_CONFIG0); + msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; + wrmsr(CPU_DM_CONFIG0, msr); + + /* write serialize memory hole to PCI. Need to unWS when something is + * shadowed regardless of cachablility. + */ + msr.lo = 0x021212121; + msr.hi = 0x021212121; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); +} + +/****************************************************************************/ +/***/ +/** DisableMemoryReorder*/ +/***/ +/** PBZ 3659:*/ +/** The MC reordered transactions incorrectly and breaks coherency.*/ +/** Disable reording and take a potential performance hit.*/ +/** This is safe to do here and not in MC init since there is nothing*/ +/** to maintain coherency with and the cache is not enabled yet.*/ +/***/ +/****************************************************************************/ +static void disablememoryreadorder(void) +{ + msr_t msr; + + msr = rdmsr(MC_CF8F_DATA); + msr.hi |= CF8F_UPPER_REORDER_DIS_SET; + wrmsr(MC_CF8F_DATA, msr); +} + +/* For cpu version C3. Should be the only released version */ +void cpubug(void) +{ + pcideadlock(); + disablememoryreadorder(); + printk(BIOS_DEBUG, "Done cpubug fixes \n"); +} diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c new file mode 100644 index 0000000..bad98b5 --- /dev/null +++ b/src/cpu/amd/geode_lx/cpureginit.c @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Indrek Kruusa + * Copyright (C) 2006 Ronald G. Minnich + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/************************************************************************** +;* +;* SetDelayControl +;* +;*************************************************************************/ +#include "cpu/x86/msr.h" + + + + +/** + * Delay Control Settings table from AMD (MCP 0x4C00000F). + */ +static const msrinit_t delay_msr_table[] = { + {CPU_BC_MSS_ARRAY_CTL0, {.hi = 0x00000000, .lo = 0x2814D352}}, + {CPU_BC_MSS_ARRAY_CTL1, {.hi = 0x00000000, .lo = 0x1068334D}}, + {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}}, +}; + + + +static const struct delay_controls { + u8 dimms; + u8 devices; + u32 slow_hi; + u32 slow_low; + u32 fast_hi; + u32 fast_low; +} delay_control_table[] = { + /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ + { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, + { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, + { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, + { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, + { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, + { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, +}; + +/* + * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM + * in slot 0, but it should be clear for all 2 DIMM settings and if a + * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. + * + * Settings for single DIMM and no VTT termination (like DB800 platform) + * 0xF2F100FF 0x56960004 + * ------------------------------------- + * ADDR/CTL have 22 ohm series R + * DQ/DQM/DQS have 33 ohm series R + */ + +/** + * This is Black Magic DRAM timing juju[1]. + * + * DRAM delay depends on CPU clock, memory bus clock, memory bus loading, + * memory bus termination, your middle initial (ha! caught you!), GeodeLink + * clock rate, and DRAM timing specifications. + * + * From this the code computes a number which is "known to work". No, + * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger) + * is hooked up, then just don't do anything. This code was written by a master + * of the Dark Arts at AMD and should not be modified in any way. + * + * [1] (http://www.thefreedictionary.com/juju) + * + * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent). + * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent). + * @param terminated The bus is terminated. (mainboard dependent). + */ +static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated) +{ + u32 glspeed; + u8 spdbyte0, spdbyte1, dimms, i; + msr_t msr; + + glspeed = GeodeLinkSpeed(); + + /* Fix delay controls for DM and IM arrays. */ + for (i = 0; i < ARRAY_SIZE(delay_msr_table); i++) + wrmsr(delay_msr_table[i].index, delay_msr_table[i].msr); + + msr = rdmsr(GLCP_FIFOCTL); + msr.hi = 0x00000005; + wrmsr(GLCP_FIFOCTL, msr); + + /* Enable setting. */ + msr.hi = 0; + msr.lo = 0x00000001; + wrmsr(CPU_BC_MSS_ARRAY_CTL_ENA, msr); + + /* Debug Delay Control setup check. + * Leave it alone if it has been setup. FS2 or something is here. + */ + msr = rdmsr(GLCP_DELAY_CONTROLS); + if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) + return; + + /* Delay Controls based on DIMM loading. UGH! + * Number of devices = module width (SPD 6) / device width (SPD 13) + * * physical banks (SPD 5) + * + * Note: We only support a module width of 64. + */ + dimms = 0; + spdbyte0 = spd_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH); + if (spdbyte0 != 0xFF) { + dimms++; + spdbyte0 = (u8)64 / spdbyte0 * + (u8)(spd_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); + } else { + spdbyte0 = 0; + } + + spdbyte1 = spd_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH); + if (spdbyte1 != 0xFF) { + dimms++; + spdbyte1 = (u8)64 / spdbyte1 * + (u8)(spd_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); + } else { + spdbyte1 = 0; + } + + /* Zero GLCP_DELAY_CONTROLS MSR */ + msr.hi = msr.lo = 0; + + /* Save some power, disable clock to second DIMM if it is empty. */ + if (spdbyte1 == 0) + msr.hi |= DELAY_UPPER_DISABLE_CLK135; + + spdbyte0 += spdbyte1; + + if ((dimms == 1) && (terminated == DRAM_TERMINATED)) { + msr.hi = 0xF2F100FF; + msr.lo = 0x56960004; + } else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) { + if ((dimms == delay_control_table[i].dimms) && + (spdbyte0 <= delay_control_table[i].devices)) { + if (glspeed < 334) { + msr.hi |= delay_control_table[i].slow_hi; + msr.lo |= delay_control_table[i].slow_low; + } else { + msr.hi |= delay_control_table[i].fast_hi; + msr.lo |= delay_control_table[i].fast_low; + } + break; + } + } + wrmsr(GLCP_DELAY_CONTROLS, msr); +} + +/* ***************************************************************************/ +/* * cpuRegInit*/ +/* ***************************************************************************/ +void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) +{ + int msrnum; + msr_t msr; + + /* Castle 2.0 BTM periodic sync period. */ + /* [40:37] 1 sync record per 256 bytes */ + print_debug("Castle 2.0 BTM periodic sync period.\n"); + msrnum = CPU_PF_CONF; + msr = rdmsr(msrnum); + msr.hi |= (0x8 << 5); + wrmsr(msrnum, msr); + + /* + * LX performance setting. + * Enable Quack for fewer re-RAS on the MC + */ + print_debug("Enable Quack for fewer re-RAS on the MC\n"); + msrnum = GLIU0_ARB; + msr = rdmsr(msrnum); + msr.hi &= ~ARB_UPPER_DACK_EN_SET; + msr.hi |= ARB_UPPER_QUACK_EN_SET; + wrmsr(msrnum, msr); + + msrnum = GLIU1_ARB; + msr = rdmsr(msrnum); + msr.hi &= ~ARB_UPPER_DACK_EN_SET; + msr.hi |= ARB_UPPER_QUACK_EN_SET; + wrmsr(msrnum, msr); + + /* GLIU port active enable, limit south pole masters + * (AES and PCI) to one outstanding transaction. + */ + print_debug(" GLIU port active enable\n"); + msrnum = GLIU1_PORT_ACTIVE; + msr = rdmsr(msrnum); + msr.lo &= ~0x880; + wrmsr(msrnum, msr); + + /* Set the Delay Control in GLCP */ + print_debug("Set the Delay Control in GLCP\n"); + SetDelayControl(dimm0, dimm1, terminated); + + /* Enable RSDC */ + print_debug("Enable RSDC\n"); + msrnum = CPU_AC_SMM_CTL; + msr = rdmsr(msrnum); + msr.lo |= SMM_INST_EN_SET; + wrmsr(msrnum, msr); + + /* FPU imprecise exceptions bit */ + print_debug("FPU imprecise exceptions bit\n"); + msrnum = CPU_FPU_MSR_MODE; + msr = rdmsr(msrnum); + msr.lo |= FPU_IE_SET; + wrmsr(msrnum, msr); + + /* Power Savers (Do after BIST) */ + /* Enable Suspend on HLT & PAUSE instructions */ + print_debug("Enable Suspend on HLT & PAUSE instructions\n"); + msrnum = CPU_XC_CONFIG; + msr = rdmsr(msrnum); + msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; + wrmsr(msrnum, msr); + + /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ + print_debug("Enable SUSP and allow TSC to run in Suspend\n"); + msrnum = CPU_BC_CONF_0; + msr = rdmsr(msrnum); + msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; + msr.lo &= 0x0F0FFFFFF; + msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ + wrmsr(msrnum, msr); + + /* Disable the debug clock to save power. */ + /* NOTE: leave it enabled for fs2 debug */ + if (debug_clock_disable && 0) { + msrnum = GLCP_DBGCLKCTL; + msr.hi = 0; + msr.lo = 0; + wrmsr(msrnum, msr); + } + + /* Setup throttling delays to proper mode if it is ever enabled. */ + print_debug("Setup throttling delays to proper mode\n"); + msrnum = GLCP_TH_OD; + msr.hi = 0; + msr.lo = 0x00000603C; + wrmsr(msrnum, msr); + print_debug("Done cpuRegInit\n"); +} diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c new file mode 100644 index 0000000..bb9a73e --- /dev/null +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Indrek Kruusa + * Copyright (C) 2006 Ronald G. Minnich + * Copyright (C) 2006 Stefan Reinauer + * Copyright (C) 2006 Andrei Birjukov + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void vsm_end_post_smi(void) +{ + __asm__ volatile ("push %ax\n" + "mov $0x5000, %ax\n" + ".byte 0x0f, 0x38\n" "pop %ax\n"); +} + +static void geode_lx_init(device_t dev) +{ + printk(BIOS_DEBUG, "geode_lx_init\n"); + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Enable the local cpu apics */ + //setup_lapic(); + + // do VSA late init + vsm_end_post_smi(); + + // Set gate A20 (legacy vsm disables it in late init) + printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92)); + outb(0x02, 0x92); + printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92)); + + printk(BIOS_DEBUG, "CPU geode_lx_init DONE\n"); +}; + +static struct device_operations cpu_dev_ops = { + .init = geode_lx_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_AMD, 0x05A2}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c new file mode 100644 index 0000000..1118250 --- /dev/null +++ b/src/cpu/amd/geode_lx/msrinit.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "cpu/x86/msr.h" + +static const msrinit_t msr_table[] = +{ + {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB. + * Rom Properties: Write Serialize, WriteProtect. + * RomBase: 0xFFFC0 + * SysTop to RomBase Properties: Write Back. + * SysTop: 0x000A0 + * System Memory Properties: (Write Back) */ + {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ + {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ + {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ + + /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ + {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF + {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF + {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF + {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF + {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF + {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF + + /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. + * It doesn't really matter in fact how much, however, because the only usage + * of this extended memory will be to host the coreboot_ram stage at RAMBASE, + * currently 1Mb. + * These registers will be set to their correct value by the Northbridge init code. + * + * WARNING: if coreboot_ram could not be loaded, these registers are probably + * incorrectly set here. You may comment the following two lines and set RAMBASE + * to 0x4000 to revert to the previous behavior for LX-boards. + */ + {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 + {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 +}; + +static void msr_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(msr_table); i++) + wrmsr(msr_table[i].index, msr_table[i].msr); +} + + diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c new file mode 100644 index 0000000..35c54fb --- /dev/null +++ b/src/cpu/amd/geode_lx/syspreinit.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Indrek Kruusa + * Copyright (C) 2006 Ronald G. Minnich + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* ***************************************************************************/ +/* **/ +/* * StartTimer1*/ +/* **/ +/* * Entry: none*/ +/* * Exit: Starts Timer 1 for port 61 use*/ +/* * Destroys: Al,*/ +/* **/ +/* ***************************************************************************/ +static void StartTimer1(void) +{ + outb(0x56, 0x43); + outb(0x12, 0x41); +} + +void SystemPreInit(void) +{ + + /* they want a jump ... */ +#if !CONFIG_CACHE_AS_RAM + __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); +#endif + StartTimer1(); +} diff --git a/src/cpu/amd/model_gx1/Kconfig b/src/cpu/amd/model_gx1/Kconfig deleted file mode 100644 index c1c9b28..0000000 --- a/src/cpu/amd/model_gx1/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config CPU_AMD_GX1 - bool - -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_AMD_GX1 - -config DCACHE_RAM_SIZE - hex - default 0x01000 - depends on CPU_AMD_GX1 - diff --git a/src/cpu/amd/model_gx1/Makefile.inc b/src/cpu/amd/model_gx1/Makefile.inc deleted file mode 100644 index bf543a4..0000000 --- a/src/cpu/amd/model_gx1/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -driver-y += model_gx1_init.c - -cpu_incs += $(src)/cpu/amd/model_gx1/cpu_setup.inc -cpu_incs += $(src)/cpu/amd/model_gx1/gx_setup.inc diff --git a/src/cpu/amd/model_gx1/cpu_setup.inc b/src/cpu/amd/model_gx1/cpu_setup.inc deleted file mode 100644 index d701f8d..0000000 --- a/src/cpu/amd/model_gx1/cpu_setup.inc +++ /dev/null @@ -1,68 +0,0 @@ -/* - freebios/src/northbridge/nsc/gx1/cpu_setup.inc - - Copyright (c) 2002 Christer Weinigel - - Initialize the GX1 CPU configuration registers -*/ - -/* USES: esi, ecx, eax */ - -#include - - movl %eax, %ebp /* preserve bist */ - -cpu_setup_start: - leal cpu_setup_table, %esi - movl $cpu_setup_len, %ecx - -cpu_setup_loop: - movw (%esi), %ax - addl $2, %esi - outb %al, $0x22 - movb %ah, %al - outb %al, $0x23 - loop cpu_setup_loop - - movb $0xff, %al /* DIR1 -- Identification Register 1 */ - outb %al, $0x22 - inb $0x23, %al - cmpb $0x63, %al /* Revision for GXLV rev 3 */ - jbe cpu_no_ccr4 - - movb $0xe8, %al /* CCR4 */ - outb %al, $0x22 - inb $0x23, %al - orb $0x20, %al /* Enable FPU Fast Mode */ - outb %al, $0x23 - - movb $0xf0, %al /* PCR1 --- Performace Control */ - outb %al, $0x22 - inb $0x23, %al - orb $0x02, %al /* Incrementor on, whatever that is */ - outb %al, $0x23 - - movb $0x20, %al /* PCR0 --- Performace Control */ - outb %al, $0x22 - inb $0x23, %al - orb $0x20, %al /* Must be 1 according to data book */ - orb $0x04, %al /* Incrementor Margin 10 */ - outb %al, $0x23 -cpu_no_ccr4: - - jmp cpu_setup_end - -cpu_setup_table: - .byte 0xc1, 0x00 /* NO SMIs */ - .byte 0xc3, 0x14 /* Enable CPU config register */ - .byte 0x20, 0x00 - .byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */ - .byte 0xc2, 0x00 - .byte 0xe8, 0x98 - .byte 0xc3, 0xf8 /* Enable CPU config register */ -cpu_setup_len = (.-cpu_setup_table)/2 - -cpu_setup_end: - nop - - movl %ebp, %eax /* Restore bist */ diff --git a/src/cpu/amd/model_gx1/gx_setup.inc b/src/cpu/amd/model_gx1/gx_setup.inc deleted file mode 100644 index 6d0e289..0000000 --- a/src/cpu/amd/model_gx1/gx_setup.inc +++ /dev/null @@ -1,47 +0,0 @@ -/* - freebios/src/northbridge/nsc/gx1/gx_setup.inc - - Copyright (c) 2002 Christer Weinigel - - Setup the GX_BASE registers on a National Semiconductor Geode CPU -*/ - -#include - - movl %eax, %ebp /* Preserve bist */ - -gx_setup_start: - leal gx_setup_table, %esi - movl $gx_setup_len, %ecx - movl $GX_BASE, %edi - -gx_setup_loop: - movw (%esi), %di /* Only read the low word of address */ - addl $4, %esi - movl (%esi), %eax /* Data */ - addl $4, %esi - movl %eax, (%edi) - loop gx_setup_loop - - jmp gx_setup_end - -gx_setup_table: - /* Allow writes to config registers */ - .long DC_UNLOCK, DC_UNLOCK_MAGIC - .long DC_GENERAL_CFG, 0 - .long DC_UNLOCK, 0 - - .long BC_DRAM_TOP, 0x3fffffff - .long BC_XMAP_1, 0x60 - .long BC_XMAP_2, 0 - .long BC_XMAP_3, 0 - - .long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */ - .long MC_MEM_CNTRL1, XBUSARB - .long MC_GBASE_ADD, 0x7ff /* Almost 1GB */ -gx_setup_len = (.-gx_setup_table)/8 - -gx_setup_end: - nop - - movl %ebp, %eax /* Restore bist */ diff --git a/src/cpu/amd/model_gx1/model_gx1_init.c b/src/cpu/amd/model_gx1/model_gx1_init.c deleted file mode 100644 index e3c9034..0000000 --- a/src/cpu/amd/model_gx1/model_gx1_init.c +++ /dev/null @@ -1,101 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#include -#include - -static void gx1_cpu_setup(void) -{ - unsigned char rreg; - unsigned char cpu_table[] = { - 0xc1, 0x00, /* NO SMIs */ - 0xc3, 0x14, /* Enable CPU config register */ - 0x20, 0x00, /* */ - 0xb8, GX_BASE>>30, /* Enable GXBASE address */ - 0xc2, 0x00, - 0xe8, 0x98, - 0xc3, 0xf8, /* Enable CPU config register */ - 0x00, 0x00 - }; - unsigned char *cPtr = cpu_table; - - while(rreg = *cPtr++) { - unsigned char rval = *cPtr++; - outb(rreg, 0x22); - outb(rval, 0x23); - } - - outb(0xff, 0x22); /* DIR1 -- Identification register 1 */ - if(inb(0x23) > 0x63) { /* Rev greater than R3 */ - outb(0xe8, 0x22); - outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */ - - outb(0xf0, 0x22); - outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */ - - outb(0x20, 0x22); - outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */ - /* Bit 2 Incrementor margin 10 */ - - } -} - -static void gx1_gx_setup(void) -{ -unsigned long gx_setup_table[] = { - GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC, - GX_BASE + DC_GENERAL_CFG, 0, - GX_BASE + DC_UNLOCK, 0, - GX_BASE + BC_DRAM_TOP, 0x3fffffff, - GX_BASE + BC_XMAP_1, 0x60, - GX_BASE + BC_XMAP_2, 0, - GX_BASE + BC_XMAP_3, 0, - GX_BASE + MC_BANK_CFG, 0x00700070, - GX_BASE + MC_MEM_CNTRL1, XBUSARB, - GX_BASE + MC_GBASE_ADD, 0xff, - 0, 0 - }; - -unsigned long *gxPtr = gx_setup_table; -unsigned long *gxdPtr; -unsigned long addr; - - while(addr = *gxPtr++) { - gxdPtr = (unsigned long *)addr; - *gxdPtr = *gxPtr++; - } -} -#endif - -static void model_gx1_init(device_t dev) -{ -#if 0 - gx1_cpu_setup(); - gx1_gx_setup(); -#endif - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Enable the local cpu apics */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_gx1_init, -}; - -static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_CYRIX, 0x0540 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/model_gx2/Kconfig b/src/cpu/amd/model_gx2/Kconfig deleted file mode 100644 index 4515a71..0000000 --- a/src/cpu/amd/model_gx2/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config CPU_AMD_GX2 - bool - -if CPU_AMD_GX2 - -config CPU_SPECIFIC_OPTIONS - def_bool y - select CACHE_AS_RAM - -config DCACHE_RAM_BASE - hex - default 0xc8000 - -config DCACHE_RAM_SIZE - hex - default 0x04000 - -config GEODE_VSA - bool - default y - select PCI_OPTION_ROM_RUN_REALMODE - -config GEODE_VSA_FILE - bool "Add a VSA image" - help - Select this option if you have an AMD Geode GX2 vsa that you would - like to add to your ROM. - - You will be able to specify the location and file name of the - image later. - -config VSA_FILENAME - string "AMD Geode GX2 VSA path and filename" - depends on GEODE_VSA_FILE - default "gpl_vsa_gx_102.bin" - help - The path and filename of the file to use as VSA. - -endif # CPU_AMD_GX2 - diff --git a/src/cpu/amd/model_gx2/Makefile.inc b/src/cpu/amd/model_gx2/Makefile.inc deleted file mode 100644 index 5e6d9ca..0000000 --- a/src/cpu/amd/model_gx2/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm - -driver-y += model_gx2_init.c -ramstage-y += cpubug.c - -cpu_incs += $(src)/cpu/amd/model_gx2/cache_as_ram.inc diff --git a/src/cpu/amd/model_gx2/cache_as_ram.inc b/src/cpu/amd/model_gx2/cache_as_ram.inc deleted file mode 100644 index 0af2fdf..0000000 --- a/src/cpu/amd/model_gx2/cache_as_ram.inc +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2010 Nils Jacobs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ -#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) - -#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */ -#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ -#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE) -#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ -#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ -#include -#include -/*************************************************************************** -/** -/** DCacheSetup -/** -/** Setup data cache for use as RAM for a stack. -/** -/** Max. size data cache =0x4000 (16KB) -/** -/***************************************************************************/ -DCacheSetup: - /* Save the BIST result */ - movl %eax, %ebx - - invd - /* set cache properties */ - movl $CPU_RCONF_DEFAULT, %ecx - rdmsr - movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ - wrmsr - - /* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */ - movl $CPU_DM_CONFIG0, %ecx - rdmsr - andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ - wrmsr - - /* Get cleaned up. */ - xorl %edi, %edi - xorl %esi, %esi - xorl %ebp, %ebp - - /* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ - /* remember, there is NO stack yet... */ - - /* Tell cache we want to fill WAY 0 starting at the top */ - xorl %edx, %edx - xorl %eax, %eax - movl $CPU_DC_INDEX, %ecx - wrmsr - - /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ - movl $GX2_STACK_BASE, %ebp /* init to start address */ - orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ - - /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ - movl $GX2_NUM_CACHELINES, %edi -DCacheSetupFillWay: - - /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ - /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ - movw $0x04, %si - xorl %edx, %edx - xorl %eax, %eax - movl $CPU_DC_DATA, %ecx -DCacheSetup_quadWordLoop: - wrmsr - decw %si - jnz DCacheSetup_quadWordLoop - - /* Set the tag for this line,need to do this for every new cache line to validate it! */ - /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ - xorl %edx, %edx - movl %ebp, %eax - movl $CPU_DC_TAG, %ecx - wrmsr - - /* switch to next line */ - /* lines are in Bits8:2 */ - /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ - movl $CPU_DC_INDEX, %ecx - rdmsr - addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */ - wrmsr - - decl %edi - jnz DCacheSetupFillWay - - /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ - addl $GX2_CACHEWAY_SIZE, %ebp - cmpl $GX2_STACK_END, %ebp - jge leave_DCacheSetup - movl $GX2_NUM_CACHELINES, %edi - - /* switch to next way */ - movl $CPU_DC_INDEX, %ecx - rdmsr - addl $0x01, %eax - andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */ - wrmsr - - jmp DCacheSetupFillWay - -leave_DCacheSetup: - xorl %edi, %edi - xorl %esi, %esi - xorl %ebp, %ebp - - /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ - /* Memory reads and writes will all hit in the cache. */ - /* Cache updates and memory write-backs will not occur ! */ - movl %cr0, %eax - orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ - movl %eax, %cr0 - - /* Now point sp to the cached stack. */ - /* The stack will be fully functional at this location. No system memory is required at all ! */ - /* set up the stack pointer */ - movl $GX2_STACK_END, %eax - movl %eax, %esp - - /* test the stack*/ - movl $0x0F0F05A5A, %edx - pushl %edx - popl %ecx - cmpl %ecx, %edx - je DCacheSetupGood - - post_code(0xc5) -DCacheSetupBad: - hlt /* issues */ - jmp DCacheSetupBad -DCacheSetupGood: - /* Go do early init and memory setup */ - - /* Restore the BIST result */ - movl %ebx, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function */ - call main -done_cache_as_ram_main: - - /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ - - push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi - cld - rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi - - /* Clear the cache out to ram */ - wbinvd - /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 - - /* clear boot_complete flag */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - - /* TODO For suspend/resume the cache will have to live between - * CONFIG_RAMBASE and CONFIG_RAMTOP - */ - - cld /* clear direction flag */ - - /* copy coreboot from it's initial load location to - * the location it is compiled to run at. - * Normally this is copying from FLASH ROM to RAM. - */ - movl %ebp, %esi - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - diff --git a/src/cpu/amd/model_gx2/cpubug.c b/src/cpu/amd/model_gx2/cpubug.c deleted file mode 100644 index 473766c..0000000 --- a/src/cpu/amd/model_gx2/cpubug.c +++ /dev/null @@ -1,349 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if 0 -void bug645(void) -{ - msr_t msr; - rdmsr(CPU_ID_CONFIG); - msr.whatever |= ID_CONFIG_SERIAL_SET; - wrmsr(msr); -} - -void bug573(void) -{ - msr_t msr; - msr = rdmsr(MC_GLD_MSR_PM); - msr.eax &= 0xfff3; - wrmsr(MC_GLD_MSR_PM); -} -#endif - -/* pcideadlock - * - * Bugtool #465 and #609 - * PCI cache deadlock - * There is also fix code in cache and PCI functions. This bug is very is pervasive. - */ -static void pcideadlock(void) -{ - msr_t msr; - - /* forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting - * for PCI writes to complete. - */ - msr = rdmsr(CPU_DM_CONFIG0); - msr.hi &= ~(7<= CPU_REV_2_1){ - msrnum = CPU_PF_BTB_CONF; - msr = rdmsr(msrnum); - msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET; - wrmsr(msrnum, msr); - } - -/* FPU impercise exceptions bit */ - { - msrnum = CPU_FPU_MSR_MODE; - msr = rdmsr(msrnum); - msr.lo |= FPU_IE_SET; - wrmsr(msrnum, msr); - } -} diff --git a/src/cpu/amd/model_gx2/model_gx2_init.c b/src/cpu/amd/model_gx2/model_gx2_init.c deleted file mode 100644 index 241c0f9..0000000 --- a/src/cpu/amd/model_gx2/model_gx2_init.c +++ /dev/null @@ -1,46 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include - -static void vsm_end_post_smi(void) -{ - __asm__ volatile ( - "push %ax\n" - "mov $0x5000, %ax\n" - ".byte 0x0f, 0x38\n" - "pop %ax\n" - ); -} - -static void model_gx2_init(device_t dev) -{ - printk(BIOS_DEBUG, "model_gx2_init\n"); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Enable the local cpu apics */ - //setup_lapic(); - - vsm_end_post_smi(); - - printk(BIOS_DEBUG, "model_gx2_init DONE\n"); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_gx2_init, -}; - -static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_NSC, 0x0552 }, - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/model_gx2/syspreinit.c b/src/cpu/amd/model_gx2/syspreinit.c deleted file mode 100644 index 8140348..0000000 --- a/src/cpu/amd/model_gx2/syspreinit.c +++ /dev/null @@ -1,20 +0,0 @@ -/* StartTimer1 - * - * Entry: none - * Exit: Starts Timer 1 for port 61 use - * Destroys: Al, - */ -static void StartTimer1(void) -{ - outb(0x56, 0x43); - outb(0x12, 0x41); -} - -void SystemPreInit(void) -{ - /* they want a jump ... */ -#if !CONFIG_CACHE_AS_RAM - __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); -#endif - StartTimer1(); -} diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/model_lx/Kconfig deleted file mode 100644 index 742ef69..0000000 --- a/src/cpu/amd/model_lx/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -config CPU_AMD_LX - bool - -if CPU_AMD_LX - -config CPU_SPECIFIC_OPTIONS - def_bool y - select CACHE_AS_RAM - -config DCACHE_RAM_BASE - hex - default 0xc8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - -config GEODE_VSA - bool - default y - select PCI_OPTION_ROM_RUN_REALMODE - -config GEODE_VSA_FILE - bool "Add a VSA image" - help - Select this option if you have an AMD Geode LX vsa that you would - like to add to your ROM. - - You will be able to specify the location and file name of the - image later. - -config VSA_FILENAME - string "AMD Geode LX VSA path and filename" - depends on GEODE_VSA_FILE - default "gpl_vsa_lx_102.bin" - help - The path and filename of the file to use as VSA. - -endif # CPU_AMD_LX diff --git a/src/cpu/amd/model_lx/Makefile.inc b/src/cpu/amd/model_lx/Makefile.inc deleted file mode 100644 index 3455d1e..0000000 --- a/src/cpu/amd/model_lx/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm - -driver-y += model_lx_init.c -ramstage-y += cpubug.c - -cpu_incs += $(src)/cpu/amd/model_lx/cache_as_ram.inc diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc deleted file mode 100644 index a1d775d..0000000 --- a/src/cpu/amd/model_lx/cache_as_ram.inc +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ -#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) - -#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */ -#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ -#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) -#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ -#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ -#include -#include -/*************************************************************************** -/** -/** DCacheSetup -/** -/** Setup data cache for use as RAM for a stack. -/** -/***************************************************************************/ -DCacheSetup: - /* Save the BIST result */ - movl %eax, %ebx - - invd - /* set cache properties */ - movl $CPU_RCONF_DEFAULT, %ecx - rdmsr - movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ - wrmsr - - /* in LX DCDIS is set after POR which disables the cache..., clear this bit */ - movl CPU_DM_CONFIG0,%ecx - rdmsr - andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ - wrmsr - - /* get cache timing params from BIOS config data locations and apply */ - /* fix delay controls for DM and IM arrays */ - /* fix delay controls for DM and IM arrays */ - movl $CPU_BC_MSS_ARRAY_CTL0, %ecx - xorl %edx, %edx - movl $0x2814D352, %eax - wrmsr - - movl $CPU_BC_MSS_ARRAY_CTL1, %ecx - xorl %edx, %edx - movl $0x1068334D, %eax - wrmsr - - movl $CPU_BC_MSS_ARRAY_CTL2, %ecx - movl $0x00000106, %edx - movl $0x83104104, %eax - wrmsr - - movl $GLCP_FIFOCTL, %ecx - rdmsr - movl $0x00000005, %edx - wrmsr - - /* Enable setting */ - movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx - xorl %edx, %edx - movl $0x01, %eax - wrmsr - - /* Get cleaned up. */ - xorl %edi, %edi - xorl %esi, %esi - xorl %ebp, %ebp - - /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ - /* remember, there is NO stack yet... */ - - /* Tell cache we want to fill WAY 0 starting at the top */ - xorl %edx, %edx - xorl %eax, %eax - movl $CPU_DC_INDEX, %ecx - wrmsr - - /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ - movl $LX_STACK_BASE, %ebp /* init to start address */ - orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ - - /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ - movl $LX_NUM_CACHELINES, %edi -DCacheSetupFillWay: - - /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ - /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ - movw $0x04, %si - xorl %edx, %edx - xorl %eax, %eax - movl $CPU_DC_DATA, %ecx -DCacheSetup_quadWordLoop: - wrmsr - decw %si - jnz DCacheSetup_quadWordLoop - - /* Set the tag for this line, need to do this for every new cache line to validate it! */ - /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ - xorl %edx, %edx - movl %ebp, %eax - movl $CPU_DC_TAG, %ecx - wrmsr - - /* switch to next line */ - /* lines are in Bits10:4 */ - /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ - movl $CPU_DC_INDEX, %ecx - rdmsr - addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */ - wrmsr - - decl %edi - jnz DCacheSetupFillWay - - /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ - addl $LX_CACHEWAY_SIZE, %ebp - cmpl $LX_STACK_END, %ebp - jge leave_DCacheSetup - movl $LX_NUM_CACHELINES, %edi - - /* switch to next way */ - movl $CPU_DC_INDEX, %ecx - rdmsr - addl $0x01, %eax - andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */ - wrmsr - - jmp DCacheSetupFillWay - -leave_DCacheSetup: - xorl %edi, %edi - xorl %esi, %esi - xorl %ebp, %ebp - - /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ - /* Memory reads and writes will all hit in the cache. */ - /* Cache updates and memory write-backs will not occur ! */ - movl %cr0, %eax - orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ - movl %eax, %cr0 - - /* Now point sp to the cached stack. */ - /* The stack will be fully functional at this location. No system memory is required at all ! */ - /* set up the stack pointer */ - movl $LX_STACK_END, %eax - movl %eax, %esp - - /* test the stack*/ - movl $0x0F0F05A5A, %edx - pushl %edx - popl %ecx - cmpl %ecx, %edx - je DCacheSetupGood - - post_code(0xc5) -DCacheSetupBad: - hlt /* issues */ - jmp DCacheSetupBad -DCacheSetupGood: - /* Go do early init and memory setup */ - - /* Restore the BIST result */ - movl %ebx, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function */ - call main -done_cache_as_ram_main: - - /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ - - push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi - cld - rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi - - /* Clear the cache out to ram */ - wbinvd - /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 - - /* clear boot_complete flag */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - - /* TODO For suspend/resume the cache will have to live between - * CONFIG_RAMBASE and CONFIG_RAMTOP - */ - - cld /* clear direction flag */ - - /* copy coreboot from it's initial load location to - * the location it is compiled to run at. - * Normally this is copying from FLASH ROM to RAM. - */ - movl %ebp, %esi - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c deleted file mode 100644 index e3b6e51..0000000 --- a/src/cpu/amd/model_lx/cpubug.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Indrek Kruusa - * Copyright (C) 2006 Ronald G. Minnich - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/************************************************************************** - * - * pcideadlock - * - * Bugtool #465 and #609 - * PCI cache deadlock - * There is also fix code in cache and PCI functions. This bug is very is pervasive. - * - **************************************************************************/ -static void pcideadlock(void) -{ - msr_t msr; - - /* - * forces serialization of all load misses. Setting this bit prevents the - * DM pipe from backing up if a read request has to be held up waiting - * for PCI writes to complete. - */ - msr = rdmsr(CPU_DM_CONFIG0); - msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; - wrmsr(CPU_DM_CONFIG0, msr); - - /* write serialize memory hole to PCI. Need to unWS when something is - * shadowed regardless of cachablility. - */ - msr.lo = 0x021212121; - msr.hi = 0x021212121; - wrmsr(CPU_RCONF_A0_BF, msr); - wrmsr(CPU_RCONF_C0_DF, msr); - wrmsr(CPU_RCONF_E0_FF, msr); -} - -/****************************************************************************/ -/***/ -/** DisableMemoryReorder*/ -/***/ -/** PBZ 3659:*/ -/** The MC reordered transactions incorrectly and breaks coherency.*/ -/** Disable reording and take a potential performance hit.*/ -/** This is safe to do here and not in MC init since there is nothing*/ -/** to maintain coherency with and the cache is not enabled yet.*/ -/***/ -/****************************************************************************/ -static void disablememoryreadorder(void) -{ - msr_t msr; - - msr = rdmsr(MC_CF8F_DATA); - msr.hi |= CF8F_UPPER_REORDER_DIS_SET; - wrmsr(MC_CF8F_DATA, msr); -} - -/* For cpu version C3. Should be the only released version */ -void cpubug(void) -{ - pcideadlock(); - disablememoryreadorder(); - printk(BIOS_DEBUG, "Done cpubug fixes \n"); -} diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c deleted file mode 100644 index bad98b5..0000000 --- a/src/cpu/amd/model_lx/cpureginit.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Indrek Kruusa - * Copyright (C) 2006 Ronald G. Minnich - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/************************************************************************** -;* -;* SetDelayControl -;* -;*************************************************************************/ -#include "cpu/x86/msr.h" - - - - -/** - * Delay Control Settings table from AMD (MCP 0x4C00000F). - */ -static const msrinit_t delay_msr_table[] = { - {CPU_BC_MSS_ARRAY_CTL0, {.hi = 0x00000000, .lo = 0x2814D352}}, - {CPU_BC_MSS_ARRAY_CTL1, {.hi = 0x00000000, .lo = 0x1068334D}}, - {CPU_BC_MSS_ARRAY_CTL2, {.hi = 0x00000106, .lo = 0x83104104}}, -}; - - - -static const struct delay_controls { - u8 dimms; - u8 devices; - u32 slow_hi; - u32 slow_low; - u32 fast_hi; - u32 fast_low; -} delay_control_table[] = { - /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ - { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, - { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, - { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, - { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, - { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, - { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, -}; - -/* - * Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM - * in slot 0, but it should be clear for all 2 DIMM settings and if a - * single DIMM is in slot 1. Bits 54:52 should always be set to '111'. - * - * Settings for single DIMM and no VTT termination (like DB800 platform) - * 0xF2F100FF 0x56960004 - * ------------------------------------- - * ADDR/CTL have 22 ohm series R - * DQ/DQM/DQS have 33 ohm series R - */ - -/** - * This is Black Magic DRAM timing juju[1]. - * - * DRAM delay depends on CPU clock, memory bus clock, memory bus loading, - * memory bus termination, your middle initial (ha! caught you!), GeodeLink - * clock rate, and DRAM timing specifications. - * - * From this the code computes a number which is "known to work". No, - * hardware is not an exact science. And, finally, if an FS2 (JTAG debugger) - * is hooked up, then just don't do anything. This code was written by a master - * of the Dark Arts at AMD and should not be modified in any way. - * - * [1] (http://www.thefreedictionary.com/juju) - * - * @param dimm0 The SMBus address of DIMM 0 (mainboard dependent). - * @param dimm1 The SMBus address of DIMM 1 (mainboard dependent). - * @param terminated The bus is terminated. (mainboard dependent). - */ -static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated) -{ - u32 glspeed; - u8 spdbyte0, spdbyte1, dimms, i; - msr_t msr; - - glspeed = GeodeLinkSpeed(); - - /* Fix delay controls for DM and IM arrays. */ - for (i = 0; i < ARRAY_SIZE(delay_msr_table); i++) - wrmsr(delay_msr_table[i].index, delay_msr_table[i].msr); - - msr = rdmsr(GLCP_FIFOCTL); - msr.hi = 0x00000005; - wrmsr(GLCP_FIFOCTL, msr); - - /* Enable setting. */ - msr.hi = 0; - msr.lo = 0x00000001; - wrmsr(CPU_BC_MSS_ARRAY_CTL_ENA, msr); - - /* Debug Delay Control setup check. - * Leave it alone if it has been setup. FS2 or something is here. - */ - msr = rdmsr(GLCP_DELAY_CONTROLS); - if (msr.lo & ~(DELAY_LOWER_STATUS_MASK)) - return; - - /* Delay Controls based on DIMM loading. UGH! - * Number of devices = module width (SPD 6) / device width (SPD 13) - * * physical banks (SPD 5) - * - * Note: We only support a module width of 64. - */ - dimms = 0; - spdbyte0 = spd_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH); - if (spdbyte0 != 0xFF) { - dimms++; - spdbyte0 = (u8)64 / spdbyte0 * - (u8)(spd_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); - } else { - spdbyte0 = 0; - } - - spdbyte1 = spd_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH); - if (spdbyte1 != 0xFF) { - dimms++; - spdbyte1 = (u8)64 / spdbyte1 * - (u8)(spd_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); - } else { - spdbyte1 = 0; - } - - /* Zero GLCP_DELAY_CONTROLS MSR */ - msr.hi = msr.lo = 0; - - /* Save some power, disable clock to second DIMM if it is empty. */ - if (spdbyte1 == 0) - msr.hi |= DELAY_UPPER_DISABLE_CLK135; - - spdbyte0 += spdbyte1; - - if ((dimms == 1) && (terminated == DRAM_TERMINATED)) { - msr.hi = 0xF2F100FF; - msr.lo = 0x56960004; - } else for (i = 0; i < ARRAY_SIZE(delay_control_table); i++) { - if ((dimms == delay_control_table[i].dimms) && - (spdbyte0 <= delay_control_table[i].devices)) { - if (glspeed < 334) { - msr.hi |= delay_control_table[i].slow_hi; - msr.lo |= delay_control_table[i].slow_low; - } else { - msr.hi |= delay_control_table[i].fast_hi; - msr.lo |= delay_control_table[i].fast_low; - } - break; - } - } - wrmsr(GLCP_DELAY_CONTROLS, msr); -} - -/* ***************************************************************************/ -/* * cpuRegInit*/ -/* ***************************************************************************/ -void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) -{ - int msrnum; - msr_t msr; - - /* Castle 2.0 BTM periodic sync period. */ - /* [40:37] 1 sync record per 256 bytes */ - print_debug("Castle 2.0 BTM periodic sync period.\n"); - msrnum = CPU_PF_CONF; - msr = rdmsr(msrnum); - msr.hi |= (0x8 << 5); - wrmsr(msrnum, msr); - - /* - * LX performance setting. - * Enable Quack for fewer re-RAS on the MC - */ - print_debug("Enable Quack for fewer re-RAS on the MC\n"); - msrnum = GLIU0_ARB; - msr = rdmsr(msrnum); - msr.hi &= ~ARB_UPPER_DACK_EN_SET; - msr.hi |= ARB_UPPER_QUACK_EN_SET; - wrmsr(msrnum, msr); - - msrnum = GLIU1_ARB; - msr = rdmsr(msrnum); - msr.hi &= ~ARB_UPPER_DACK_EN_SET; - msr.hi |= ARB_UPPER_QUACK_EN_SET; - wrmsr(msrnum, msr); - - /* GLIU port active enable, limit south pole masters - * (AES and PCI) to one outstanding transaction. - */ - print_debug(" GLIU port active enable\n"); - msrnum = GLIU1_PORT_ACTIVE; - msr = rdmsr(msrnum); - msr.lo &= ~0x880; - wrmsr(msrnum, msr); - - /* Set the Delay Control in GLCP */ - print_debug("Set the Delay Control in GLCP\n"); - SetDelayControl(dimm0, dimm1, terminated); - - /* Enable RSDC */ - print_debug("Enable RSDC\n"); - msrnum = CPU_AC_SMM_CTL; - msr = rdmsr(msrnum); - msr.lo |= SMM_INST_EN_SET; - wrmsr(msrnum, msr); - - /* FPU imprecise exceptions bit */ - print_debug("FPU imprecise exceptions bit\n"); - msrnum = CPU_FPU_MSR_MODE; - msr = rdmsr(msrnum); - msr.lo |= FPU_IE_SET; - wrmsr(msrnum, msr); - - /* Power Savers (Do after BIST) */ - /* Enable Suspend on HLT & PAUSE instructions */ - print_debug("Enable Suspend on HLT & PAUSE instructions\n"); - msrnum = CPU_XC_CONFIG; - msr = rdmsr(msrnum); - msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; - wrmsr(msrnum, msr); - - /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ - print_debug("Enable SUSP and allow TSC to run in Suspend\n"); - msrnum = CPU_BC_CONF_0; - msr = rdmsr(msrnum); - msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; - msr.lo &= 0x0F0FFFFFF; - msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ - wrmsr(msrnum, msr); - - /* Disable the debug clock to save power. */ - /* NOTE: leave it enabled for fs2 debug */ - if (debug_clock_disable && 0) { - msrnum = GLCP_DBGCLKCTL; - msr.hi = 0; - msr.lo = 0; - wrmsr(msrnum, msr); - } - - /* Setup throttling delays to proper mode if it is ever enabled. */ - print_debug("Setup throttling delays to proper mode\n"); - msrnum = GLCP_TH_OD; - msr.hi = 0; - msr.lo = 0x00000603C; - wrmsr(msrnum, msr); - print_debug("Done cpuRegInit\n"); -} diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c deleted file mode 100644 index 85e6bfb..0000000 --- a/src/cpu/amd/model_lx/model_lx_init.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Indrek Kruusa - * Copyright (C) 2006 Ronald G. Minnich - * Copyright (C) 2006 Stefan Reinauer - * Copyright (C) 2006 Andrei Birjukov - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void vsm_end_post_smi(void) -{ - __asm__ volatile ("push %ax\n" - "mov $0x5000, %ax\n" - ".byte 0x0f, 0x38\n" "pop %ax\n"); -} - -static void model_lx_init(device_t dev) -{ - printk(BIOS_DEBUG, "model_lx_init\n"); - - /* Turn on caching if we haven't already */ - x86_enable_cache(); - - /* Enable the local cpu apics */ - //setup_lapic(); - - // do VSA late init - vsm_end_post_smi(); - - // Set gate A20 (legacy vsm disables it in late init) - printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92)); - outb(0x02, 0x92); - printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92)); - - printk(BIOS_DEBUG, "CPU model_lx_init DONE\n"); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_lx_init, -}; - -static struct cpu_device_id cpu_table[] = { - {X86_VENDOR_AMD, 0x05A2}, - {0, 0}, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c deleted file mode 100644 index 1118250..0000000 --- a/src/cpu/amd/model_lx/msrinit.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "cpu/x86/msr.h" - -static const msrinit_t msr_table[] = -{ - {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB. - * Rom Properties: Write Serialize, WriteProtect. - * RomBase: 0xFFFC0 - * SysTop to RomBase Properties: Write Back. - * SysTop: 0x000A0 - * System Memory Properties: (Write Back) */ - {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ - {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ - {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ - - /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ - {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF - {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF - {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF - {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF - {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF - {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF - - /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. - * It doesn't really matter in fact how much, however, because the only usage - * of this extended memory will be to host the coreboot_ram stage at RAMBASE, - * currently 1Mb. - * These registers will be set to their correct value by the Northbridge init code. - * - * WARNING: if coreboot_ram could not be loaded, these registers are probably - * incorrectly set here. You may comment the following two lines and set RAMBASE - * to 0x4000 to revert to the previous behavior for LX-boards. - */ - {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 - {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 -}; - -static void msr_init(void) -{ - int i; - for (i = 0; i < ARRAY_SIZE(msr_table); i++) - wrmsr(msr_table[i].index, msr_table[i].msr); -} - - diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c deleted file mode 100644 index 35c54fb..0000000 --- a/src/cpu/amd/model_lx/syspreinit.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Indrek Kruusa - * Copyright (C) 2006 Ronald G. Minnich - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* ***************************************************************************/ -/* **/ -/* * StartTimer1*/ -/* **/ -/* * Entry: none*/ -/* * Exit: Starts Timer 1 for port 61 use*/ -/* * Destroys: Al,*/ -/* **/ -/* ***************************************************************************/ -static void StartTimer1(void) -{ - outb(0x56, 0x43); - outb(0x12, 0x41); -} - -void SystemPreInit(void) -{ - - /* they want a jump ... */ -#if !CONFIG_CACHE_AS_RAM - __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); -#endif - StartTimer1(); -} diff --git a/src/include/lib.h b/src/include/lib.h index bbe735f..ea09887 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -41,7 +41,7 @@ int ram_check_nodie(unsigned long start, unsigned long stop); void quick_ram_check(void); /* Defined in romstage.c */ -#if CONFIG_CPU_AMD_LX +#if CONFIG_CPU_AMD_GEODE_LX void cache_as_ram_main(void); #else void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig index 3b31ffb..9986987 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig +++ b/src/mainboard/aaeon/pfm-540i_revb/Kconfig @@ -3,7 +3,7 @@ if BOARD_AAEON_PFM_540I_REVB config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_SMSC_SMSCSUPERIO diff --git a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb index b049160..3987584 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb +++ b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb @@ -66,7 +66,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index b638a07..4b510a9 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -55,9 +55,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig index 7c87e28..4e5c8f3 100644 --- a/src/mainboard/advantech/pcm-5820/Kconfig +++ b/src/mainboard/advantech/pcm-5820/Kconfig @@ -21,7 +21,7 @@ if BOARD_ADVANTECH_PCM_5820 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977F diff --git a/src/mainboard/advantech/pcm-5820/devicetree.cb b/src/mainboard/advantech/pcm-5820/devicetree.cb index b416e9a..b77fd06 100644 --- a/src/mainboard/advantech/pcm-5820/devicetree.cb +++ b/src/mainboard/advantech/pcm-5820/devicetree.cb @@ -51,6 +51,6 @@ chip northbridge/amd/gx1 # Northbridge register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/geode_gx1 # CPU end end diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig index 834e085..ee2aa0f 100644 --- a/src/mainboard/amd/db800/Kconfig +++ b/src/mainboard/amd/db800/Kconfig @@ -3,7 +3,7 @@ if BOARD_AMD_DB800 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb index e872571..e0f20dc 100644 --- a/src/mainboard/amd/db800/devicetree.cb +++ b/src/mainboard/amd/db800/devicetree.cb @@ -60,7 +60,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 264f1a8..3590c37 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -49,9 +49,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig index b265eeb..dec8e01 100644 --- a/src/mainboard/amd/norwich/Kconfig +++ b/src/mainboard/amd/norwich/Kconfig @@ -3,7 +3,7 @@ if BOARD_AMD_NORWICH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index 533ea92..b2ede77 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 097965f..d8fca5a 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -46,9 +46,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index 0477f32..3f55d01 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -21,7 +21,7 @@ if BOARD_AMD_RUMBA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX2 + select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 select UDELAY_TSC diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index 40490e1..e55f5c7 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/gx2 device lapic_cluster 0 on - chip cpu/amd/model_gx2 + chip cpu/amd/geode_gx2 device lapic 0 on end end end diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 49dfa68..cec7c36 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -26,9 +26,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_gx2/cpureginit.c" -#include "cpu/amd/model_gx2/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_gx2/cpureginit.c" +#include "cpu/amd/geode_gx2/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig index 846000c..55c96ba 100644 --- a/src/mainboard/artecgroup/dbe61/Kconfig +++ b/src/mainboard/artecgroup/dbe61/Kconfig @@ -3,7 +3,7 @@ if BOARD_ARTECGROUP_DBE61 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb index 4c2aab4..c8110d1 100644 --- a/src/mainboard/artecgroup/dbe61/devicetree.cb +++ b/src/mainboard/artecgroup/dbe61/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 83b59bb..f97af92 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -61,9 +61,9 @@ static int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig index 5278369..b4aa59f 100644 --- a/src/mainboard/asi/mb_5blgp/Kconfig +++ b/src/mainboard/asi/mb_5blgp/Kconfig @@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLGP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC87351 diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb index f50be6e..3ad1acb 100644 --- a/src/mainboard/asi/mb_5blgp/devicetree.cb +++ b/src/mainboard/asi/mb_5blgp/devicetree.cb @@ -50,6 +50,6 @@ chip northbridge/amd/gx1 # Northbridge register "ide1_enable" = "0" # No connector on this board end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/geode_gx1 # CPU end end diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig index 5b3b5bd..8ce924e 100644 --- a/src/mainboard/asi/mb_5blmp/Kconfig +++ b/src/mainboard/asi/mb_5blmp/Kconfig @@ -21,7 +21,7 @@ if BOARD_ASI_MB_5BLMP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC87351 diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb index ded603a..e3e0d95 100644 --- a/src/mainboard/asi/mb_5blmp/devicetree.cb +++ b/src/mainboard/asi/mb_5blmp/devicetree.cb @@ -42,7 +42,7 @@ chip northbridge/amd/gx1 # Northbridge register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/geode_gx1 # CPU end end diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig index dde2a36..fbe68e5 100644 --- a/src/mainboard/axus/tc320/Kconfig +++ b/src/mainboard/axus/tc320/Kconfig @@ -21,7 +21,7 @@ if BOARD_AXUS_TC320 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb index cf670c7..3c17690 100644 --- a/src/mainboard/axus/tc320/devicetree.cb +++ b/src/mainboard/axus/tc320/devicetree.cb @@ -50,6 +50,6 @@ chip northbridge/amd/gx1 # Northbridge # register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/geode_gx1 # CPU end end diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig index dbb2cb8..5b74b4c 100644 --- a/src/mainboard/bcom/winnet100/Kconfig +++ b/src/mainboard/bcom/winnet100/Kconfig @@ -21,7 +21,7 @@ if BOARD_BCOM_WINNET100 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/bcom/winnet100/devicetree.cb b/src/mainboard/bcom/winnet100/devicetree.cb index 872b8f3..20c117e 100644 --- a/src/mainboard/bcom/winnet100/devicetree.cb +++ b/src/mainboard/bcom/winnet100/devicetree.cb @@ -51,6 +51,6 @@ chip northbridge/amd/gx1 # Northbridge register "ide1_enable" = "0" # Not available/needed on this board end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/geode_gx1 # CPU end end diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig index 444023b..0b54906 100644 --- a/src/mainboard/digitallogic/msm800sev/Kconfig +++ b/src/mainboard/digitallogic/msm800sev/Kconfig @@ -3,7 +3,7 @@ if BOARD_DIGITALLOGIC_MSM800SEV config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index c4dfa17..e00b36f 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -77,7 +77,7 @@ chip northbridge/amd/lx # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 2f4cef1..d30e2b0 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -30,9 +30,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/eaglelion/5bcm/Kconfig b/src/mainboard/eaglelion/5bcm/Kconfig index 65dd802..f96c494 100644 --- a/src/mainboard/eaglelion/5bcm/Kconfig +++ b/src/mainboard/eaglelion/5bcm/Kconfig @@ -21,7 +21,7 @@ if BOARD_EAGLELION_5BCM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb index a08ffd4..94e8fab 100644 --- a/src/mainboard/eaglelion/5bcm/devicetree.cb +++ b/src/mainboard/eaglelion/5bcm/devicetree.cb @@ -45,7 +45,7 @@ chip northbridge/amd/gx1 end end - chip cpu/amd/model_gx1 + chip cpu/amd/geode_gx1 end end diff --git a/src/mainboard/iei/juki-511p/Kconfig b/src/mainboard/iei/juki-511p/Kconfig index d948929..e44253f 100644 --- a/src/mainboard/iei/juki-511p/Kconfig +++ b/src/mainboard/iei/juki-511p/Kconfig @@ -21,7 +21,7 @@ if BOARD_IEI_JUKI_511P config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977F diff --git a/src/mainboard/iei/juki-511p/devicetree.cb b/src/mainboard/iei/juki-511p/devicetree.cb index be5f064..8592c09 100644 --- a/src/mainboard/iei/juki-511p/devicetree.cb +++ b/src/mainboard/iei/juki-511p/devicetree.cb @@ -50,7 +50,7 @@ chip northbridge/amd/gx1 end end - chip cpu/amd/model_gx1 + chip cpu/amd/geode_gx1 end end diff --git a/src/mainboard/iei/nova4899r/Kconfig b/src/mainboard/iei/nova4899r/Kconfig index 3cc5ddb..a829796 100644 --- a/src/mainboard/iei/nova4899r/Kconfig +++ b/src/mainboard/iei/nova4899r/Kconfig @@ -21,7 +21,7 @@ if BOARD_IEI_NOVA_4899R config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977TF diff --git a/src/mainboard/iei/nova4899r/devicetree.cb b/src/mainboard/iei/nova4899r/devicetree.cb index e6a0c80..8055fb1 100644 --- a/src/mainboard/iei/nova4899r/devicetree.cb +++ b/src/mainboard/iei/nova4899r/devicetree.cb @@ -57,7 +57,7 @@ chip northbridge/amd/gx1 end end - chip cpu/amd/model_gx1 + chip cpu/amd/geode_gx1 end end diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index e393609..eae72ae 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -3,7 +3,7 @@ if BOARD_IEI_PCISA_LX_800_R10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb index a7e74d0..2d37ecf 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb +++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb @@ -68,7 +68,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 4121e3e..aec9843 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -53,9 +53,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig index 4e8cee0..ba1d5f1 100644 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ b/src/mainboard/lippert/frontrunner/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_FRONTRUNNER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX2 + select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 select HAVE_DEBUG_SMBUS diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index fa7c6e7..63ac140 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/gx2 device lapic_cluster 0 on - chip cpu/amd/model_gx2 + chip cpu/amd/geode_gx2 device lapic 0 on end end end diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 9717250..bdbf059 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -66,9 +66,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_gx2/cpureginit.c" -#include "cpu/amd/model_gx2/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_gx2/cpureginit.c" +#include "cpu/amd/geode_gx2/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 9b20aa0..118809d 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_HURRICANE_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/hurricane-lx/devicetree.cb b/src/mainboard/lippert/hurricane-lx/devicetree.cb index 17c0b8b..5aa4cd4 100644 --- a/src/mainboard/lippert/hurricane-lx/devicetree.cb +++ b/src/mainboard/lippert/hurricane-lx/devicetree.cb @@ -83,7 +83,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index fe00731..29aa9d1 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -77,9 +77,9 @@ static int smc_send_config(unsigned char config_data) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 7b45d36..12a3ae1 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_LITERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/literunner-lx/devicetree.cb b/src/mainboard/lippert/literunner-lx/devicetree.cb index 44d6010..b142471 100644 --- a/src/mainboard/lippert/literunner-lx/devicetree.cb +++ b/src/mainboard/lippert/literunner-lx/devicetree.cb @@ -80,7 +80,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 1245a43..1e82bdb 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -118,9 +118,9 @@ static int smc_send_config(unsigned char config_data) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 4e29742..2d11b33 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_ROADRUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/roadrunner-lx/devicetree.cb b/src/mainboard/lippert/roadrunner-lx/devicetree.cb index eae8479..73d1d88 100644 --- a/src/mainboard/lippert/roadrunner-lx/devicetree.cb +++ b/src/mainboard/lippert/roadrunner-lx/devicetree.cb @@ -82,7 +82,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 87718b5..20e5b6a 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -53,9 +53,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index f273d6c..99ecf7c 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -3,7 +3,7 @@ if BOARD_LIPPERT_SPACERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_ITE_IT8712F diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb index 1fd2c54..4bb1508 100644 --- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb +++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb @@ -83,7 +83,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 299079c..9dcb37b 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -118,9 +118,9 @@ static int smc_send_config(unsigned char config_data) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 0a016a5..315b7ed 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX1C config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 4af91ca..91d9350 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -77,7 +77,7 @@ chip northbridge/amd/lx # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 7e025a8..f109031 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -107,9 +107,9 @@ static u8 spd_read_byte(u8 device, u8 address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..c2e4b2e 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX2D config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index edcbc06..836ba35 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -37,7 +37,7 @@ chip northbridge/amd/lx # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 6ced8f2..0e8cc63 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -106,9 +106,9 @@ static u8 spd_read_byte(u8 device, u8 address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" /** Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig index b3233d9..9147fc6 100644 --- a/src/mainboard/televideo/tc7020/Kconfig +++ b/src/mainboard/televideo/tc7020/Kconfig @@ -21,7 +21,7 @@ if BOARD_TELEVIDEO_TC7020 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX1 + select CPU_AMD_GEODE_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 diff --git a/src/mainboard/televideo/tc7020/devicetree.cb b/src/mainboard/televideo/tc7020/devicetree.cb index bf89cf2..10188a3 100644 --- a/src/mainboard/televideo/tc7020/devicetree.cb +++ b/src/mainboard/televideo/tc7020/devicetree.cb @@ -52,6 +52,6 @@ chip northbridge/amd/gx1 # Northbridge register "ide1_enable" = "0" # Not available/needed on this board end end - chip cpu/amd/model_gx1 # CPU + chip cpu/amd/geode_gx1 # CPU end end diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index dd6c8dd..40679fe 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -3,7 +3,7 @@ if BOARD_TRAVERSE_GEOS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select HAVE_PIRQ_TABLE diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb index eab70c7..44b36f6 100644 --- a/src/mainboard/traverse/geos/devicetree.cb +++ b/src/mainboard/traverse/geos/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 80a9557..588681b 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -47,9 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig index 4f367f1..7db7de5 100644 --- a/src/mainboard/winent/pl6064/Kconfig +++ b/src/mainboard/winent/pl6064/Kconfig @@ -3,7 +3,7 @@ if BOARD_WINENT_PL6064 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_LX + select CPU_AMD_GEODE_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 select SUPERIO_WINBOND_W83627HF diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index ff20fed..82fd21e 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -73,7 +73,7 @@ chip northbridge/amd/lx end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_lx + chip cpu/amd/geode_lx device lapic 0 on end end end diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index a8b684e..6651acd 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -51,9 +51,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig index dff01f9..982935d 100644 --- a/src/mainboard/wyse/s50/Kconfig +++ b/src/mainboard/wyse/s50/Kconfig @@ -21,7 +21,7 @@ if BOARD_WYSE_S50 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_GX2 + select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 select UDELAY_TSC diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb index e7cf0c2..d43b81e 100644 --- a/src/mainboard/wyse/s50/devicetree.cb +++ b/src/mainboard/wyse/s50/devicetree.cb @@ -44,7 +44,7 @@ chip northbridge/amd/gx2 end # APIC cluster is late CPU init. device lapic_cluster 0 on - chip cpu/amd/model_gx2 + chip cpu/amd/geode_gx2 device lapic 0 on end end end diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 12fc446..9e5dd53 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -45,9 +45,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" -#include "cpu/amd/model_gx2/cpureginit.c" -#include "cpu/amd/model_gx2/syspreinit.c" -#include "cpu/amd/model_lx/msrinit.c" +#include "cpu/amd/geode_gx2/cpureginit.c" +#include "cpu/amd/geode_gx2/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" void main(unsigned long bist) { From gerrit at coreboot.org Thu Feb 9 15:54:08 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 9 Feb 2012 15:54:08 +0100 Subject: [coreboot] New patch to review for coreboot: ede2da9 VIA cpus: apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/614 -gerrit commit ede2da9d2d9fffcf8a57d19958bedf595cc46f01 Author: Ky?sti M?lkki Date: Thu Feb 9 16:51:38 2012 +0200 VIA cpus: apply un-written naming rules Rename files and directories: model_c3 -> c3 model_c7 -> c7 Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126 Signed-off-by: Ky?sti M?lkki --- src/cpu/via/Kconfig | 4 +- src/cpu/via/Makefile.inc | 4 +- src/cpu/via/c3/Kconfig | 11 ++ src/cpu/via/c3/Makefile.inc | 8 + src/cpu/via/c3/c3_init.c | 53 ++++++ src/cpu/via/c7/Kconfig | 21 +++ src/cpu/via/c7/Makefile.inc | 10 ++ src/cpu/via/c7/c7_init.c | 231 +++++++++++++++++++++++++++ src/cpu/via/model_c3/Kconfig | 4 - src/cpu/via/model_c3/Makefile.inc | 8 - src/cpu/via/model_c3/model_c3_init.c | 53 ------ src/cpu/via/model_c7/Kconfig | 23 --- src/cpu/via/model_c7/Makefile.inc | 10 -- src/cpu/via/model_c7/model_c7_init.c | 231 --------------------------- src/mainboard/bcom/winnetp680/devicetree.cb | 2 +- src/mainboard/jetway/j7f24/devicetree.cb | 2 +- src/mainboard/via/epia-cn/devicetree.cb | 2 +- src/mainboard/via/epia-m/devicetree.cb | 2 +- src/mainboard/via/epia-m700/devicetree.cb | 2 +- src/mainboard/via/epia-n/devicetree.cb | 2 +- src/mainboard/via/epia/devicetree.cb | 2 +- src/mainboard/via/pc2500e/devicetree.cb | 2 +- src/mainboard/via/vt8454c/devicetree.cb | 2 +- 23 files changed, 347 insertions(+), 342 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 006fb8b..570d408 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,2 @@ -source src/cpu/via/model_c3/Kconfig -source src/cpu/via/model_c7/Kconfig +source src/cpu/via/c3/Kconfig +source src/cpu/via/c7/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 512f82b..2616111 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,3 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += model_c7 -subdirs-$(CONFIG_CPU_VIA_C3) += model_c3 +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig new file mode 100644 index 0000000..a5b4f22 --- /dev/null +++ b/src/cpu/via/c3/Kconfig @@ -0,0 +1,11 @@ +config CPU_VIA_C3 + bool + +if CPU_VIA_C3 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + +endif # CPU_VIA_C3 diff --git a/src/cpu/via/c3/Makefile.inc b/src/cpu/via/c3/Makefile.inc new file mode 100644 index 0000000..e6b889a --- /dev/null +++ b/src/cpu/via/c3/Makefile.inc @@ -0,0 +1,8 @@ +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../../intel/microcode + +driver-y += c3_init.c diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c new file mode 100644 index 0000000..7d94384 --- /dev/null +++ b/src/cpu/via/c3/c3_init.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +static void c3_init(device_t dev) +{ + x86_enable_cache(); + x86_setup_mtrrs(); + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); +}; + +static struct device_operations cpu_dev_ops = { + .init = c3_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_CENTAUR, 0x0670 }, // VIA C3 Samual 2 + Ezra + { X86_VENDOR_CENTAUR, 0x0680 }, // VIA C3 Ezra-T + { X86_VENDOR_CENTAUR, 0x0690 }, // VIA C3 Nehemiah + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig new file mode 100644 index 0000000..ebbb8f9 --- /dev/null +++ b/src/cpu/via/c7/Kconfig @@ -0,0 +1,21 @@ +config CPU_VIA_C7 + bool + +if CPU_VIA_C7 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_C7 diff --git a/src/cpu/via/c7/Makefile.inc b/src/cpu/via/c7/Makefile.inc new file mode 100644 index 0000000..5300f5d --- /dev/null +++ b/src/cpu/via/c7/Makefile.inc @@ -0,0 +1,10 @@ +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../../intel/microcode + +driver-y += c7_init.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c new file mode 100644 index 0000000..510e66d --- /dev/null +++ b/src/cpu/via/c7/c7_init.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 + +static int c7a_speed_translation[] = { +// LFM HFM + 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M + 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V + 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V + 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V + 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V + 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V + 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V + 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV + 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV + 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV + 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV +}; + +static int c7d_speed_translation[] = { +// LFM HFM + 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M + 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V + 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V + 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V + 0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V + 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV + 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV + 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV + 0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV + 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV + 0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV +}; + +static void set_c7_speed(int model) { + int cnt, current, new, i; + msr_t msr; + printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n"); + + // Enable Speedstep + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + msr = rdmsr(MSR_IA32_PERF_STATUS); + + printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n", + ((int)(msr.lo & 0xff) * 16 + 700), + ((int)((msr.hi >> 16) & 0xff) * 16 + 700), + ((int)(msr.hi & 0xff) * 16 + 700)); + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + (int)((msr.lo >> 8) & 0xff), + (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff)); + + printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo); + + /* Wait while CPU is busy */ + cnt = 0; + while (msr.lo & ((1 << 16) | (1 << 17))) { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, "Could not update multiplier and voltage.\n"); + return; + } + } + + current = msr.lo & 0xffff; + + // Start out with no change. + new = current; + switch (model) { + case 10: // model A + for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) { + if ((c7a_speed_translation[i] == current) && + ((c7a_speed_translation[i + 1] & 0xff00) == + (msr.hi & 0xff00))) { + new = c7a_speed_translation[i + 1]; + } + } + break; + case 13: // model D + for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) { + if ((c7d_speed_translation[i] == current) && + ((c7d_speed_translation[i + 1] & 0xff00) == + (msr.hi & 0xff00))) { + new = c7d_speed_translation[i + 1]; + } + } + break; + default: + print_info("CPU type not known, multiplier unchanged.\n"); + } + + msr.lo = new; + msr.hi = 0; + printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo); + + wrmsr(MSR_IA32_PERF_CTL, msr); + + /* Wait until the power transition ends */ + cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700)); + printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff)); +} + +static void c7_init(device_t dev) +{ + u8 brand; + struct cpuinfo_x86 c; + msr_t msr; + + get_fms(&c, dev->device); + + printk(BIOS_INFO, "Detected VIA "); + + switch (c.x86_model) { + case 10: + msr = rdmsr(0x1153); + brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3; + printk(BIOS_INFO, "Model A "); + break; + case 13: + msr = rdmsr(0x1154); + brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff; + printk(BIOS_INFO, "Model D "); + break; + default: + printk(BIOS_INFO, "Model Unknown "); + brand = 0xff; + } + + switch (brand) { + case 0: + printk(BIOS_INFO, "C7-M\n"); + break; + case 1: + printk(BIOS_INFO, "C7\n"); + break; + case 2: + printk(BIOS_INFO, "Eden\n"); + break; + case 3: + printk(BIOS_INFO, "C7-D\n"); + break; + default: + printk(BIOS_INFO, "%02x (please report)\n", brand); + } + + /* Gear up */ + set_c7_speed(c.x86_model); + + /* Enable APIC */ + msr = rdmsr(0x1107); + msr.lo |= 1<<24; + wrmsr(0x1107, msr); + + /* Turn on cache */ + x86_enable_cache(); + + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + + /* Enable the local cpu apics */ + setup_lapic(); +}; + +static struct device_operations cpu_dev_ops = { + .init = c7_init, +}; + +/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact + * ID, the cpu mask (stepping) is masked out and the check is repeated. This + * allows us to keep the table significantly smaller. + */ + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther + {X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther + {X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/model_c3/Kconfig b/src/cpu/via/model_c3/Kconfig deleted file mode 100644 index d613909..0000000 --- a/src/cpu/via/model_c3/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -config CPU_VIA_C3 - bool - select UDELAY_TSC - select MMX diff --git a/src/cpu/via/model_c3/Makefile.inc b/src/cpu/via/model_c3/Makefile.inc deleted file mode 100644 index 320b649..0000000 --- a/src/cpu/via/model_c3/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../../intel/microcode - -driver-y += model_c3_init.c diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c deleted file mode 100644 index 0c5315b..0000000 --- a/src/cpu/via/model_c3/model_c3_init.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include - -static void model_c3_init(device_t dev) -{ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Enable the local cpu apics */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_c3_init, -}; - -static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_CENTAUR, 0x0670 }, // VIA C3 Samual 2 + Ezra - { X86_VENDOR_CENTAUR, 0x0680 }, // VIA C3 Ezra-T - { X86_VENDOR_CENTAUR, 0x0690 }, // VIA C3 Nehemiah - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig deleted file mode 100644 index 8e6f0e8..0000000 --- a/src/cpu/via/model_c7/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -config CPU_VIA_C7 - bool - -if CPU_VIA_C7 - -config CPU_SPECFIC_OPTIONS - def_bool y - select UDELAY_TSC - select MMX - select SSE2 - select CACHE_AS_RAM - -config DCACHE_RAM_BASE - hex - default 0xffef0000 - depends on CPU_VIA_C7 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - depends on CPU_VIA_C7 - -endif # CPU_VIA_C7 diff --git a/src/cpu/via/model_c7/Makefile.inc b/src/cpu/via/model_c7/Makefile.inc deleted file mode 100644 index c6ab45e..0000000 --- a/src/cpu/via/model_c7/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../../intel/microcode - -driver-y += model_c7_init.c - -cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c deleted file mode 100644 index 585f749..0000000 --- a/src/cpu/via/model_c7/model_c7_init.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MSR_IA32_PERF_STATUS 0x00000198 -#define MSR_IA32_PERF_CTL 0x00000199 -#define MSR_IA32_MISC_ENABLE 0x000001a0 - -static int c7a_speed_translation[] = { -// LFM HFM - 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M - 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V - 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V - 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V - 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V - 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V - 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V - 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV - 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV - 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV - 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV -}; - -static int c7d_speed_translation[] = { -// LFM HFM - 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M - 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V - 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V - 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V - 0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V - 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV - 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV - 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV - 0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV - 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV - 0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV -}; - -static void set_c7_speed(int model) { - int cnt, current, new, i; - msr_t msr; - printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n"); - - // Enable Speedstep - msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLE, msr); - - msr = rdmsr(MSR_IA32_PERF_STATUS); - - printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n", - ((int)(msr.lo & 0xff) * 16 + 700), - ((int)((msr.hi >> 16) & 0xff) * 16 + 700), - ((int)(msr.hi & 0xff) * 16 + 700)); - - printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", - (int)((msr.lo >> 8) & 0xff), - (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff)); - - printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo); - - /* Wait while CPU is busy */ - cnt = 0; - while (msr.lo & ((1 << 16) | (1 << 17))) { - udelay(16); - msr = rdmsr(MSR_IA32_PERF_STATUS); - cnt++; - if (cnt > 128) { - printk(BIOS_WARNING, "Could not update multiplier and voltage.\n"); - return; - } - } - - current = msr.lo & 0xffff; - - // Start out with no change. - new = current; - switch (model) { - case 10: // model A - for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) { - if ((c7a_speed_translation[i] == current) && - ((c7a_speed_translation[i + 1] & 0xff00) == - (msr.hi & 0xff00))) { - new = c7a_speed_translation[i + 1]; - } - } - break; - case 13: // model D - for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) { - if ((c7d_speed_translation[i] == current) && - ((c7d_speed_translation[i + 1] & 0xff00) == - (msr.hi & 0xff00))) { - new = c7d_speed_translation[i + 1]; - } - } - break; - default: - print_info("CPU type not known, multiplier unchanged.\n"); - } - - msr.lo = new; - msr.hi = 0; - printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo); - - wrmsr(MSR_IA32_PERF_CTL, msr); - - /* Wait until the power transition ends */ - cnt = 0; - do { - udelay(16); - msr = rdmsr(MSR_IA32_PERF_STATUS); - cnt++; - if (cnt > 128) { - printk(BIOS_WARNING, "Error while updating multiplier and voltage\n"); - break; - } - } while (msr.lo & ((1 << 16) | (1 << 17))); - - printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700)); - printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff)); -} - -static void model_c7_init(device_t dev) -{ - u8 brand; - struct cpuinfo_x86 c; - msr_t msr; - - get_fms(&c, dev->device); - - printk(BIOS_INFO, "Detected VIA "); - - switch (c.x86_model) { - case 10: - msr = rdmsr(0x1153); - brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3; - printk(BIOS_INFO, "Model A "); - break; - case 13: - msr = rdmsr(0x1154); - brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff; - printk(BIOS_INFO, "Model D "); - break; - default: - printk(BIOS_INFO, "Model Unknown "); - brand = 0xff; - } - - switch (brand) { - case 0: - printk(BIOS_INFO, "C7-M\n"); - break; - case 1: - printk(BIOS_INFO, "C7\n"); - break; - case 2: - printk(BIOS_INFO, "Eden\n"); - break; - case 3: - printk(BIOS_INFO, "C7-D\n"); - break; - default: - printk(BIOS_INFO, "%02x (please report)\n", brand); - } - - /* Gear up */ - set_c7_speed(c.x86_model); - - /* Enable APIC */ - msr = rdmsr(0x1107); - msr.lo |= 1<<24; - wrmsr(0x1107, msr); - - /* Turn on cache */ - x86_enable_cache(); - - /* Set up Memory Type Range Registers */ - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Enable the local cpu apics */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = model_c7_init, -}; - -/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact - * ID, the cpu mask (stepping) is masked out and the check is repeated. This - * allows us to keep the table significantly smaller. - */ - -static struct cpu_device_id cpu_table[] = { - {X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther - {X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther - {X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M - {0, 0}, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/mainboard/bcom/winnetp680/devicetree.cb b/src/mainboard/bcom/winnetp680/devicetree.cb index c86bc6a..3e31223 100644 --- a/src/mainboard/bcom/winnetp680/devicetree.cb +++ b/src/mainboard/bcom/winnetp680/devicetree.cb @@ -57,7 +57,7 @@ chip northbridge/via/cn700 # Northbridge end end device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 + chip cpu/via/c7 # VIA C7 device lapic 0 on end # APIC end end diff --git a/src/mainboard/jetway/j7f24/devicetree.cb b/src/mainboard/jetway/j7f24/devicetree.cb index cbc45c3..16dd2f6 100644 --- a/src/mainboard/jetway/j7f24/devicetree.cb +++ b/src/mainboard/jetway/j7f24/devicetree.cb @@ -55,7 +55,7 @@ chip northbridge/via/cn700 # Northbridge end end device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 + chip cpu/via/c7 # VIA C7 device lapic 0 on end # APIC end end diff --git a/src/mainboard/via/epia-cn/devicetree.cb b/src/mainboard/via/epia-cn/devicetree.cb index 727ccc5..96a2222 100644 --- a/src/mainboard/via/epia-cn/devicetree.cb +++ b/src/mainboard/via/epia-cn/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/via/cn700 # Northbridge end end device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 + chip cpu/via/c7 # VIA C7 device lapic 0 on end # APIC end end diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb index cc4a39d..3db72ee 100644 --- a/src/mainboard/via/epia-m/devicetree.cb +++ b/src/mainboard/via/epia-m/devicetree.cb @@ -1,7 +1,7 @@ chip northbridge/via/vt8623 device lapic_cluster 0 on - chip cpu/via/model_c3 + chip cpu/via/c3 device lapic 0 on end end end diff --git a/src/mainboard/via/epia-m700/devicetree.cb b/src/mainboard/via/epia-m700/devicetree.cb index 4e8e2a8..a687f09 100644 --- a/src/mainboard/via/epia-m700/devicetree.cb +++ b/src/mainboard/via/epia-m700/devicetree.cb @@ -17,7 +17,7 @@ chip northbridge/via/vx800 # Northbridge # end end device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 + chip cpu/via/c7 # VIA C7 device lapic 0 on end # APIC end end diff --git a/src/mainboard/via/epia-n/devicetree.cb b/src/mainboard/via/epia-n/devicetree.cb index 651a1a2..3505374 100644 --- a/src/mainboard/via/epia-n/devicetree.cb +++ b/src/mainboard/via/epia-n/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/via/cn400 # Northbridge device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c3 # VIA C3 + chip cpu/via/c3 # VIA C3 device lapic 0 on end # APIC end end diff --git a/src/mainboard/via/epia/devicetree.cb b/src/mainboard/via/epia/devicetree.cb index b883e56..c906074 100644 --- a/src/mainboard/via/epia/devicetree.cb +++ b/src/mainboard/via/epia/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/via/vt8601 end device lapic_cluster 0 on - chip cpu/via/model_c3 + chip cpu/via/c3 device lapic 0 on end end end diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb index 05ce877..bb3ddcc 100644 --- a/src/mainboard/via/pc2500e/devicetree.cb +++ b/src/mainboard/via/pc2500e/devicetree.cb @@ -82,7 +82,7 @@ chip northbridge/via/cn700 # Northbridge end end device lapic_cluster 0 on # APIC cluster - chip cpu/via/model_c7 # VIA C7 + chip cpu/via/c7 # VIA C7 device lapic 0 on end # APIC end end diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb index 1a5bf54..ab09071 100644 --- a/src/mainboard/via/vt8454c/devicetree.cb +++ b/src/mainboard/via/vt8454c/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/via/cx700 device lapic_cluster 0 on - chip cpu/via/model_c7 + chip cpu/via/c7 device lapic 0 on end end end From gerrit at coreboot.org Thu Feb 9 19:45:51 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 9 Feb 2012 19:45:51 +0100 Subject: [coreboot] Patch merged into coreboot/master: ede2da9 VIA cpus: apply un-written naming rules References: Message-ID: the following patch was just integrated into master: commit ede2da9d2d9fffcf8a57d19958bedf595cc46f01 Author: Ky?sti M?lkki Date: Thu Feb 9 16:51:38 2012 +0200 VIA cpus: apply un-written naming rules Rename files and directories: model_c3 -> c3 model_c7 -> c7 Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Feb 9 16:08:30 2012, giving +1 Reviewed-By: Stefan Reinauer at Thu Feb 9 19:45:49 2012, giving +2 See http://review.coreboot.org/614 for details. -gerrit From gerrit at coreboot.org Thu Feb 9 21:05:59 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Thu, 9 Feb 2012 21:05:59 +0100 Subject: [coreboot] New patch to review for coreboot: e5ce5d2 i5000: halt second BSP References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit e5ce5d2160acc69fae296c1fcf89f2c12dadd1e3 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/Makefile.inc | 1 + src/northbridge/intel/i5000/halt_second_bsp.S | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..0c3ce0d 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S \ No newline at end of file diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..da13178 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,23 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + cli + hlt +tloop: jmp tloop + +1: /* Restore BIST */ + mov %ebp, %eax From gerrit at coreboot.org Thu Feb 9 21:12:51 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 9 Feb 2012 21:12:51 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3220062 Add Intel Socket LGA771 References: Message-ID: the following patch was just integrated into master: commit 3220062a8c6312889c98688c6cee0ced13e31dbf Author: Sven Schnelle Date: Fri Dec 2 16:21:35 2011 +0100 Add Intel Socket LGA771 Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8 Signed-off-by: Sven Schnelle Build-Tested: build bot (Jenkins) at Sat Dec 17 20:02:48 2011, giving +1 Reviewed-By: Sven Schnelle at Thu Feb 9 21:12:32 2012, giving +2 See http://review.coreboot.org/492 for details. -gerrit From gerrit at coreboot.org Thu Feb 9 22:06:28 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Thu, 9 Feb 2012 22:06:28 +0100 Subject: [coreboot] Patch set updated for coreboot: 8c64567 i5000: halt second BSP References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit 8c64567a2309229fba3a891fe15b0d55da2ff0b0 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/Makefile.inc | 1 + src/northbridge/intel/i5000/halt_second_bsp.S | 29 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..5e75159 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..4d52224 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli + hlt +tloop: jmp tloop + +1: /* Restore BIST */ + mov %ebp, %eax From gerrit at coreboot.org Thu Feb 9 22:08:08 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Thu, 9 Feb 2012 22:08:08 +0100 Subject: [coreboot] Patch set updated for coreboot: 74c0819 i5000: halt second BSP References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit 74c0819a95be57196d9f25aebbf9f61aa8114749 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/Makefile.inc | 1 + src/northbridge/intel/i5000/halt_second_bsp.S | 29 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..5e75159 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..a1a1b15 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli +loop: hlt + jmp loop + +1: /* Restore BIST */ + mov %ebp, %eax From gerrit at coreboot.org Fri Feb 10 10:28:20 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 10 Feb 2012 10:28:20 +0100 Subject: [coreboot] Patch merged into coreboot/master: 74c0819 i5000: halt second BSP References: Message-ID: the following patch was just integrated into master: commit 74c0819a95be57196d9f25aebbf9f61aa8114749 Author: Sven Schnelle Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle Build-Tested: build bot (Jenkins) at Thu Feb 9 22:30:52 2012, giving +1 Reviewed-By: Sven Schnelle at Fri Feb 10 10:28:17 2012, giving +2 See http://review.coreboot.org/615 for details. -gerrit From gerrit at coreboot.org Fri Feb 10 11:40:50 2012 From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com)) Date: Fri, 10 Feb 2012 11:40:50 +0100 Subject: [coreboot] New patch to review for coreboot: ec43d38 libpayload: fix possible mem leak in get_option_as_string() References: Message-ID: Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/616 -gerrit commit ec43d3821cc94bc7d600ed8e63d903196160d1c7 Author: Mathias Krause Date: Wed Feb 8 10:31:42 2012 +0100 libpayload: fix possible mem leak in get_option_as_string() Change-Id: I7c3adbd1b72be81585bbaabb42532fc4cad57f58 Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/options.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 10d165e..8161c22 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -292,7 +292,7 @@ int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_opti *dest = strdup((const char*)cmos_enum->text); break; default: /* fail */ - return 1; + ret = 1; } free(raw); return ret; From gerrit at coreboot.org Fri Feb 10 11:40:50 2012 From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com)) Date: Fri, 10 Feb 2012 11:40:50 +0100 Subject: [coreboot] New patch to review for coreboot: 26ddf1e libpayload: code cosmetics References: Message-ID: Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/617 -gerrit commit 26ddf1e0580b4b31a4576760bdbe6f640eb8fd72 Author: Mathias Krause Date: Wed Feb 8 10:32:57 2012 +0100 libpayload: code cosmetics Be consistend with coding style at least within a function -- don't mix sizeof with plain values. Change-Id: Iefb5b7fe4f54977f5505fc9cea65c9c4af3e7f3a Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/options.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 8161c22..7c76251 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -309,7 +309,7 @@ int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_op switch (cmos_entry->config) { case 'h': /* only works on little endian */ - raw = malloc(8); + raw = malloc(sizeof(u64)); *(u64*)raw = strtoull(value, NULL, 0); break; case 's': From gerrit at coreboot.org Fri Feb 10 11:53:27 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 10 Feb 2012 11:53:27 +0100 Subject: [coreboot] New patch to review for coreboot: b8948df Intel cpus: apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/618 -gerrit commit b8948dffe9dc658a915399f80a0e06d78bf983f4 Author: Ky?sti M?lkki Date: Fri Feb 10 12:42:49 2012 +0200 Intel cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x. Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/bga956/Kconfig | 3 --- src/cpu/intel/bga956/Makefile.inc | 12 ------------ src/cpu/intel/bga956/bga956.c | 7 ------- src/cpu/intel/bga956/chip.h | 4 ---- src/cpu/intel/model_1067x/Kconfig | 2 +- src/cpu/intel/model_6ex/Kconfig | 2 +- src/cpu/intel/model_6fx/Kconfig | 2 +- src/cpu/intel/socket_BGA956/Kconfig | 3 +++ src/cpu/intel/socket_BGA956/Makefile.inc | 12 ++++++++++++ src/cpu/intel/socket_BGA956/chip.h | 4 ++++ src/cpu/intel/socket_BGA956/socket_BGA956.c | 7 +++++++ src/cpu/intel/socket_LGA771/Kconfig | 1 - src/cpu/intel/socket_mFCPGA478/Kconfig | 4 ++-- src/mainboard/intel/eagleheights/devicetree.cb | 2 +- 15 files changed, 33 insertions(+), 34 deletions(-) diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 274c101..05f947d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -4,7 +4,7 @@ # Therefore: ONLY include Makefile.inc from socket directories! subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 -subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 diff --git a/src/cpu/intel/bga956/Kconfig b/src/cpu/intel/bga956/Kconfig deleted file mode 100644 index e70c48b..0000000 --- a/src/cpu/intel/bga956/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config CPU_INTEL_SOCKET_BGA956 - bool - select CPU_INTEL_CORE2 diff --git a/src/cpu/intel/bga956/Makefile.inc b/src/cpu/intel/bga956/Makefile.inc deleted file mode 100644 index a0ace12..0000000 --- a/src/cpu/intel/bga956/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -ramstage-y += bga956.c -subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading - -# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/bga956/bga956.c b/src/cpu/intel/bga956/bga956.c deleted file mode 100644 index 3469215..0000000 --- a/src/cpu/intel/bga956/bga956.c +++ /dev/null @@ -1,7 +0,0 @@ -#include -#include "chip.h" - - -struct chip_operations cpu_intel_bga956_ops = { - CHIP_NAME("BGA956 CPU") -}; diff --git a/src/cpu/intel/bga956/chip.h b/src/cpu/intel/bga956/chip.h deleted file mode 100644 index 0f32d33..0000000 --- a/src/cpu/intel/bga956/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -extern struct chip_operations cpu_intel_bga956_ops; - -struct cpu_intel_bga956_config { -}; diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 4ddba39..b079922 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_1067X bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 89005b8..31d24bd 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE +config CPU_INTEL_MODEL_6EX bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 2551057..851685c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_6FX bool select SMP select SSE2 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig new file mode 100644 index 0000000..a764348 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -0,0 +1,3 @@ +config CPU_INTEL_SOCKET_BGA956 + bool + select CPU_INTEL_MODEL_1067X diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc new file mode 100644 index 0000000..a290e69 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -0,0 +1,12 @@ +ramstage-y += socket_BGA956.c +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_BGA956/chip.h b/src/cpu/intel/socket_BGA956/chip.h new file mode 100644 index 0000000..29b220d --- /dev/null +++ b/src/cpu/intel/socket_BGA956/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_bga956_ops; + +struct cpu_intel_socket_bga956_config { +}; diff --git a/src/cpu/intel/socket_BGA956/socket_BGA956.c b/src/cpu/intel/socket_BGA956/socket_BGA956.c new file mode 100644 index 0000000..4609a91 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/socket_BGA956.c @@ -0,0 +1,7 @@ +#include +#include "chip.h" + + +struct chip_operations cpu_intel_socket_bga956_ops = { + CHIP_NAME("Socket BGA956 CPU") +}; diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 0821c3e..62bd17b 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,7 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool select CPU_INTEL_MODEL_6FX - select CPU_INTEL_CORE2 select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 3f39303..2d241cf 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -5,8 +5,8 @@ if CPU_INTEL_SOCKET_MFCPGA478 config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_CORE - select CPU_INTEL_CORE2 + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX select MMX select SSE select CACHE_AS_RAM diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index e628dda..9971264 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -65,7 +65,7 @@ chip northbridge/intel/i3100 end end device lapic_cluster 0 on - chip cpu/intel/bga956 + chip cpu/intel/socket_BGA956 device lapic 0 on end end end From gerrit at coreboot.org Fri Feb 10 12:36:11 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 10 Feb 2012 12:36:11 +0100 Subject: [coreboot] Patch set updated for coreboot: 929b6ee Intel cpus: apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/618 -gerrit commit 929b6ee50329b5850f4f0b9a1bc8010cc682f534 Author: Ky?sti M?lkki Date: Fri Feb 10 13:32:13 2012 +0200 Intel cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x. Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/Kconfig | 2 +- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/bga956/Kconfig | 3 --- src/cpu/intel/bga956/Makefile.inc | 12 ------------ src/cpu/intel/bga956/bga956.c | 7 ------- src/cpu/intel/bga956/chip.h | 4 ---- src/cpu/intel/model_1067x/Kconfig | 2 +- src/cpu/intel/model_6ex/Kconfig | 2 +- src/cpu/intel/model_6fx/Kconfig | 2 +- src/cpu/intel/socket_BGA956/Kconfig | 3 +++ src/cpu/intel/socket_BGA956/Makefile.inc | 12 ++++++++++++ src/cpu/intel/socket_BGA956/chip.h | 4 ++++ src/cpu/intel/socket_BGA956/socket_BGA956.c | 6 ++++++ src/cpu/intel/socket_LGA771/Kconfig | 1 - src/cpu/intel/socket_mFCPGA478/Kconfig | 4 ++-- src/mainboard/intel/eagleheights/devicetree.cb | 2 +- 16 files changed, 33 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 31c701c..81a834c 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -16,9 +16,9 @@ source src/cpu/intel/model_f3x/Kconfig source src/cpu/intel/model_f4x/Kconfig source src/cpu/intel/ep80579/Kconfig # Sockets/Slots -source src/cpu/intel/bga956/Kconfig source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/slot_1/Kconfig +source src/cpu/intel/socket_BGA956/Kconfig source src/cpu/intel/socket_FC_PGA370/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 274c101..05f947d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -4,7 +4,7 @@ # Therefore: ONLY include Makefile.inc from socket directories! subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 -subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 diff --git a/src/cpu/intel/bga956/Kconfig b/src/cpu/intel/bga956/Kconfig deleted file mode 100644 index e70c48b..0000000 --- a/src/cpu/intel/bga956/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config CPU_INTEL_SOCKET_BGA956 - bool - select CPU_INTEL_CORE2 diff --git a/src/cpu/intel/bga956/Makefile.inc b/src/cpu/intel/bga956/Makefile.inc deleted file mode 100644 index a0ace12..0000000 --- a/src/cpu/intel/bga956/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -ramstage-y += bga956.c -subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading - -# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/bga956/bga956.c b/src/cpu/intel/bga956/bga956.c deleted file mode 100644 index 3469215..0000000 --- a/src/cpu/intel/bga956/bga956.c +++ /dev/null @@ -1,7 +0,0 @@ -#include -#include "chip.h" - - -struct chip_operations cpu_intel_bga956_ops = { - CHIP_NAME("BGA956 CPU") -}; diff --git a/src/cpu/intel/bga956/chip.h b/src/cpu/intel/bga956/chip.h deleted file mode 100644 index 0f32d33..0000000 --- a/src/cpu/intel/bga956/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -extern struct chip_operations cpu_intel_bga956_ops; - -struct cpu_intel_bga956_config { -}; diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 4ddba39..b079922 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_1067X bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 89005b8..31d24bd 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE +config CPU_INTEL_MODEL_6EX bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 2551057..851685c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_6FX bool select SMP select SSE2 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig new file mode 100644 index 0000000..a764348 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -0,0 +1,3 @@ +config CPU_INTEL_SOCKET_BGA956 + bool + select CPU_INTEL_MODEL_1067X diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc new file mode 100644 index 0000000..a290e69 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -0,0 +1,12 @@ +ramstage-y += socket_BGA956.c +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_BGA956/chip.h b/src/cpu/intel/socket_BGA956/chip.h new file mode 100644 index 0000000..68ec1d2 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_BGA956_ops; + +struct cpu_intel_socket_BGA956_config { +}; diff --git a/src/cpu/intel/socket_BGA956/socket_BGA956.c b/src/cpu/intel/socket_BGA956/socket_BGA956.c new file mode 100644 index 0000000..53667c1 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/socket_BGA956.c @@ -0,0 +1,6 @@ +#include +#include "chip.h" + +struct chip_operations cpu_intel_socket_BGA956_ops = { + CHIP_NAME("Socket BGA956 CPU") +}; diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 0821c3e..62bd17b 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,7 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool select CPU_INTEL_MODEL_6FX - select CPU_INTEL_CORE2 select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 3f39303..2d241cf 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -5,8 +5,8 @@ if CPU_INTEL_SOCKET_MFCPGA478 config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_CORE - select CPU_INTEL_CORE2 + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX select MMX select SSE select CACHE_AS_RAM diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index e628dda..9971264 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -65,7 +65,7 @@ chip northbridge/intel/i3100 end end device lapic_cluster 0 on - chip cpu/intel/bga956 + chip cpu/intel/socket_BGA956 device lapic 0 on end end end From gerrit at coreboot.org Fri Feb 10 14:37:06 2012 From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org)) Date: Fri, 10 Feb 2012 14:37:06 +0100 Subject: [coreboot] New patch to review for coreboot: be0e1ca Remove non-existent include References: Message-ID: Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/619 -gerrit commit be0e1ca4c628ec4ae65f43fa28a035441ad0ebb3 Author: Sven Schnelle Date: Fri Feb 10 14:36:27 2012 +0100 Remove non-existent include Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf Signed-off-by: Sven Schnelle --- src/northbridge/intel/i5000/raminit.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 95610ce..139a33c 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include From gerrit at coreboot.org Fri Feb 10 14:54:37 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 10 Feb 2012 14:54:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: be0e1ca Remove non-existent include References: Message-ID: the following patch was just integrated into master: commit be0e1ca4c628ec4ae65f43fa28a035441ad0ebb3 Author: Sven Schnelle Date: Fri Feb 10 14:36:27 2012 +0100 Remove non-existent include Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf Signed-off-by: Sven Schnelle Build-Tested: build bot (Jenkins) at Fri Feb 10 14:49:15 2012, giving +1 Reviewed-By: Sven Schnelle at Fri Feb 10 14:54:35 2012, giving +2 See http://review.coreboot.org/619 for details. -gerrit From gerrit at coreboot.org Fri Feb 10 15:15:03 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 10 Feb 2012 15:15:03 +0100 Subject: [coreboot] Patch merged into coreboot/master: ec43d38 libpayload: fix possible mem leak in get_option_as_string() References: Message-ID: the following patch was just integrated into master: commit ec43d3821cc94bc7d600ed8e63d903196160d1c7 Author: Mathias Krause Date: Wed Feb 8 10:31:42 2012 +0100 libpayload: fix possible mem leak in get_option_as_string() Change-Id: I7c3adbd1b72be81585bbaabb42532fc4cad57f58 Signed-off-by: Mathias Krause Build-Tested: build bot (Jenkins) at Fri Feb 10 11:53:17 2012, giving +1 Reviewed-By: Peter Stuge at Fri Feb 10 15:15:01 2012, giving +2 See http://review.coreboot.org/616 for details. -gerrit From gerrit at coreboot.org Fri Feb 10 23:40:09 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 10 Feb 2012 23:40:09 +0100 Subject: [coreboot] Patch merged into coreboot/master: 929b6ee Intel cpus: apply un-written naming rules References: Message-ID: the following patch was just integrated into master: commit 929b6ee50329b5850f4f0b9a1bc8010cc682f534 Author: Ky?sti M?lkki Date: Fri Feb 10 13:32:13 2012 +0200 Intel cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x. Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Fri Feb 10 12:50:47 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 10 23:40:07 2012, giving +2 See http://review.coreboot.org/618 for details. -gerrit From gerrit at coreboot.org Mon Feb 13 11:09:01 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Mon, 13 Feb 2012 11:09:01 +0100 Subject: [coreboot] New patch to review for coreboot: 4ed0d36 Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/620 -gerrit commit 4ed0d36ae46fa37b7ea9d5dcc68d0e4d0e4f5e7e Author: zbao Date: Mon Feb 13 16:21:34 2012 +0800 Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao --- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 + src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 4 + src/southbridge/amd/cimx/sb800/spi.c | 210 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/spi.h | 42 ++++++ 4 files changed, 258 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30d2133..2b55fee 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -27,6 +27,8 @@ romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c + driver-y += smbus.c driver-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index db5343d..25aba95 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -158,4 +158,8 @@ typedef union _PCI_ADDR { #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#if CONFIG_HAVE_ACPI_RESUME == 1 +#include "spi.h" +#endif + #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c new file mode 100644 index 0000000..ed8f51d --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include "SBPLATFORM.h" + + +void executeCommand(volatile u8 * spi_address) +{ + *(spi_address + 2) |= 1; +} + +void wait4CommandComplete(volatile u8 * spi_address) +{ + while (*(spi_address + 2) & 1) + printk(BIOS_DEBUG, "wait4CommandComplete\n"); +} + +void resetInternalFIFOPointer(volatile u8 * spi_address) +{ + u8 val; + + do { + *(spi_address + 2) |= 0x10; + val = *(spi_address + 0xd); + } while (val & 0x7); +} + +u8 readSPIStatus(volatile u8 * spi_address) +{ + u8 val; + *spi_address = 0x05; + *(spi_address + 1) = 0x11; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = 0x0; /* dummy */ + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + resetInternalFIFOPointer(spi_address); + val = *(spi_address + 0xC); + val = *(spi_address + 0xC); + return val; +} + +void wait4FlashPartReady(volatile u8 * spi_address) +{ + while (readSPIStatus(spi_address) & 1) ; +} + +void writeSPIStatus(volatile u8 * spi_address, u8 status) +{ + *spi_address = 0x50; /* EWSR */ + *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ + executeCommand(spi_address); + wait4CommandComplete(spi_address); + + *spi_address = 0x01; /* WRSR */ + *(spi_address + 1) = 0x01; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = status; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); + + readSPIStatus(spi_address); +} + +void readSPIID(volatile u8 * spi_address) +{ + u8 mid = 0, did = 0; + *spi_address = 0x90; + *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + resetInternalFIFOPointer(spi_address); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + + mid = *(spi_address + 0xC); + did = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); +} + +void SPIWriteEnable(volatile u8 * spi_address) +{ + *spi_address = 0x06; /* Write Enable */ + *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ + executeCommand(spi_address); + wait4CommandComplete(spi_address); + //wait4FlashPartReady(spi_address); +} + +void sectorEraseSPI(volatile u8 * spi_address, u32 address) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x20; + *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ + + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void chipEraseSPI(volatile u8 * spi_address) +{ + SPIWriteEnable(spi_address); + *spi_address = 0xC7; + *(spi_address + 1) = 0x00; + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void byteProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void dwordnoneAAIProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + u8 i; + /* + * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); + */ + for (i = 0; i < 4; i++) { + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + data >>= 8; + address++; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); + } +} + +void dwordProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 7; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + *(spi_address + 0xC) = (data >> 8) & 0xFF; + *(spi_address + 0xC) = (data >> 16) & 0xFF; + *(spi_address + 0xC) = (data >> 24) & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void directByteProgram(volatile u8 * spi_address, volatile u32 * address, u32 data) +{ + SPIWriteEnable(spi_address); + *address = data; + wait4FlashPartReady(spi_address); +} diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h new file mode 100644 index 0000000..1e781f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.h @@ -0,0 +1,42 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _SB800_CIMX_SPI_H_ +#define _SB800_CIMX_SPI_H_ + +void executeCommand(volatile u8 * spi_address); +void wait4CommandComplete(volatile u8 * spi_address); +void resetInternalFIFOPointer(volatile u8 * spi_address); +u8 readSPIStatus(volatile u8 * spi_address); +void wait4FlashPartReady(volatile u8 * spi_address); +void writeSPIStatus(volatile u8 * spi_address, u8 status); +void readSPIID(volatile u8 * spi_address); +void SPIWriteEnable(volatile u8 * spi_address); +void sectorEraseSPI(volatile u8 * spi_address, u32 address); +void chipEraseSPI(volatile u8 * spi_address); +void byteProgram(volatile u8 * spi_address, u32 address, u32 data); +void dwordnoneAAIProgram(volatile u8 * spi_address, u32 address, u32 data); +void dwordProgram(volatile u8 * spi_address, u32 address, u32 data); +void directByteProgram(volatile u8 * spi_address, volatile u32 * address, u32 data); + +#endif From gerrit at coreboot.org Mon Feb 13 11:09:01 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Mon, 13 Feb 2012 11:09:01 +0100 Subject: [coreboot] New patch to review for coreboot: eca128f Add Southbridge support for S3. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621 -gerrit commit eca128f9dc287039d8f919fe28b6d63cff43fe9a Author: zbao Date: Mon Feb 13 16:35:30 2012 +0800 Add Southbridge support for S3. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao --- src/southbridge/amd/cimx/sb800/cfg.c | 33 +++++++++++++++++++++++++---- src/southbridge/amd/cimx/sb800/early.c | 21 +++++++++++++++++++ src/southbridge/amd/cimx/sb800/late.c | 19 +++++++++++++++++ src/southbridge/amd/cimx/sb800/lpc.c | 18 ++++++++++++++++ src/southbridge/amd/cimx/sb800/lpc.h | 3 ++ src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 +++ 6 files changed, 93 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a9e35bc..32c28cc 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,10 +17,31 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include #include "SBPLATFORM.h" #include "cfg.h" +#include +#include + +#define SB800_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0E) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + return (int)tmp; +} +#endif /** * @brief South Bridge CIMx configuration @@ -30,10 +51,13 @@ */ void sb800_cimx_config(AMDSBCFG *sb_config) { - if (!sb_config) { + if (!sb_config) return; - } - //memset(sb_config, 0, sizeof(AMDSBCFG)); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_get_sleep_type() == 3) + sb_config->S3Resume = 1; +#endif /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; @@ -132,4 +156,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config) } #endif //!__PRE_RAM__ } - diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52..5e9d2b4 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include #include /* inl, outl */ #include /* device_t */ +#include #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,22 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +struct cbmem_entry *get_cbmem_toc(void) +{ + uint32_t xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, /* BIOSRAM_INDEX */0xCD4); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(/* BIOSRAM_DATA */0xCD5) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8c7abdb..c69782b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,7 @@ #include #include /* smbus_bus_operations */ #include /* printk */ +#include #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ @@ -351,6 +352,17 @@ void sb_Late_Post(void) AmdSbDispatcher(sb_config); } +void sb_Before_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} /** * @brief SB Cimx entry point sbBeforePciInit wrapper @@ -468,7 +480,14 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) + sb_Before_Pci_Init(); + else + sb_Before_Pci_Restore_Init(); +#else sb_Before_Pci_Init(); +#endif break; default: diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..08f1ee5 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,25 @@ #include #include #include "lpc.h" +#include +#include +#include +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xf8, i; /* temp */ + printk(BIOS_DEBUG, "dword=%x\n", dword); + for (i = 0; i<4; i++) { + printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8..f6ffd53 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -21,6 +21,9 @@ #define _SB800_LPC_H_ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 42a7ba9..5e510de 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); void sb_Mid_Post_Init(void); void sb_Late_Post(void); +void sb_Before_Pci_Restore_Init(void); +void sb_After_Pci_Restore_Init(void); + +int acpi_is_wakeup_early(void); /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, From gerrit at coreboot.org Mon Feb 13 11:09:02 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Mon, 13 Feb 2012 11:09:02 +0100 Subject: [coreboot] New patch to review for coreboot: e02b5b9 S3 code in vendorcode folder. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622 -gerrit commit e02b5b9e01987f4aea1a8e4e33cf356ba7d8a8c8 Author: zbao Date: Mon Feb 13 16:55:28 2012 +0800 S3 code in vendorcode folder. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 10 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 158 ++--------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 204 +++++++++++++++++++++ src/vendorcode/amd/agesa/f14/gcccar.inc | 192 +++++++++++--------- 4 files changed, 328 insertions(+), 236 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 58438b9..5ce3ee3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=a" (value) + : + : "memory"); return value; } @@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D "mov %%eax, %%cr0" : : "a" (Data) + : "memory" ); } @@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void) __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); } - static __inline__ __attribute__((always_inline)) void __lidt(void *Source) { __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index c4c3892..ac613b1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -66,196 +66,64 @@ *---------------------------------------------------------------------------------------- */ -// typedef unsigned int uintptr_t; +// typedef unsigned int uintptr_t; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + +/* VOID ExecuteFinalHltInstruction ( IN UINT32 SharedCore, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ); - +*/ VOID SetIdtr ( IN IDT_BASE_LIMIT *IdtInfo, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID GetCsSelector ( IN UINT16 *Selector, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID NmiHandler ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteHltInstruction ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteWbinvdInstruction ( IN AMD_CONFIG_PARAMS *StdHeader ); - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahalt.s VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..509e962 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f14/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: +/* AMD- TODO - check these stack access are correct */ + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ + +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* restore variable MTTR6 and MTTR7 to default states */ + movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $10, %ecx /* .while (cl < 010h) */ + jge 6f + wrmsr + inc %ecx + 6: /* .endw */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 63f3ea9..981d976 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -37,99 +37,113 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized From gerrit at coreboot.org Mon Feb 13 11:09:02 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Mon, 13 Feb 2012 11:09:02 +0100 Subject: [coreboot] New patch to review for coreboot: ba9cb49 S3 code in coreboot public folder. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit ba9cb4978782d979393e0e9bdcc190fe353b1282 Author: zbao Date: Mon Feb 13 17:32:11 2012 +0800 S3 code in coreboot public folder. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao --- src/arch/x86/Makefile.inc | 10 + src/arch/x86/boot/acpi.c | 2 + src/arch/x86/boot/tables.c | 3 +- src/boot/hardwaremain.c | 5 +- src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/Kconfig | 8 + src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/cpu/amd/agesa/family14/model_14_init.c | 165 ++++++----- src/cpu/amd/agesa/s3_resume.c | 375 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 45 +++ src/devices/pci_device.c | 10 + src/include/cbmem.h | 11 +- src/lib/cbmem.c | 2 + src/northbridge/amd/agesa/family14/northbridge.c | 104 ++++-- 15 files changed, 636 insertions(+), 114 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..31de1e3 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -107,6 +107,16 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi endif +ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) +# This S3 storage area in flash is a bit tricky. The location is set and used +# by the southbridge ROM access functions. This should probably be +# connected with the #define somehow... + @printf " S3 NVRAM 0xffff0000 (S3 storage area)\n" + rm -f $(obj)/s3.rom + dd if=/dev/zero of=$(obj)/fill.rom bs=20k count=1 2> /dev/null + $(CBFSTOOL) $@.tmp add $(obj)/fill.rom "s3nv" raw 0xffff0000 + rm -f $(obj)/s3.rom +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..077f47c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -474,6 +474,8 @@ void suspend_resume(void) wake_vec = acpi_find_wakeup_vector(); if (wake_vec) acpi_jump_to_wakeup(wake_vec); + else + die("Error: No Wake Vector Found!\n Reset for normal boot path."); } /* This is to be filled by SB code - startup value what was found. */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 29d2ec0..ba5cdf3 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -230,13 +230,12 @@ struct lb_memory *write_tables(void) } post_code(0x9e); - #if CONFIG_HAVE_ACPI_RESUME /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..56a5f0c 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -35,7 +35,7 @@ it with the version available from LANL. #include #include #include -#if CONFIG_HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME == 1 #include #endif #if CONFIG_WRITE_HIGH_TABLES @@ -94,7 +94,8 @@ void hardwaremain(int boot_complete) cbmem_initialize(); #endif #if CONFIG_HAVE_ACPI_RESUME == 1 - suspend_resume(); + if (acpi_slp_type == 3) + suspend_resume(); post_code(0x8a); #endif diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..cfe6a43 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -20,5 +20,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 702270c..d1140f3 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,3 +67,11 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 +config RESUME_SCRATCH_MEMORY_SIZE +# This is derived from AGESA gccar.inc +# BSP_STACK_SIZE + CORE0_STACK_SIZE * 8 + CORE1_STACK_SIZE * 64 + HEAP_SIZE +# For 2 core Fam14: BSP_STACK_SIZE + CORE1_STACK_SIZE + HEAP_SIZE +# 0x10000 + 0x1000 + 20000 + hex + default 0x31000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 774d401..b08ceeb 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 6f697cf..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,109 +32,126 @@ #include #include #include +#include +#include #define MCI_STATUS 0x401 msr_t rdmsr_amd(u32 index) { - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; } void wrmsr_amd(u32 index, msr_t msr) { - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); } static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { - .init = model_14_init, + .init = model_14_init, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ - { 0, 0 }, + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { 0, 0 }, }; static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, + .ops = &cpu_dev_ops, + .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..94976c3 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,375 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include +#include +#include +#include +#include +#if CONFIG_WRITE_HIGH_TABLES +#include +#endif +#include +#include +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +/* + * TODO: This memcopy is replicated from another CAR resume file and should + * be removed and a library/coreboot call used. + */ +void inline __attribute__ ((always_inline)) memcopy(void *dest, const void *src, + unsigned long bytes) +{ + int d0, d1, d2; + asm volatile ("cld ; rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" + "jz 1f\n\t" + "rep ; movsb\n\t" "1:":"=&c" (d0), "=&D"(d1), "=&S"(d2) + :"0"(bytes / 4), "g"(bytes), "1"((long)dest), + "2"((long)src) + :"memory", "cc"); +} + +void restore_mtrr(void) +{ + UINT64 msrdata; + u32 msr; + AMD_CONFIG_PARAMS StdHeader; + volatile UINT64 *msrPtr = (volatile UINT64 *)S3_DATA_MTRR_POS; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + LibAmdMsrRead(SYS_CFG, &msrdata, &StdHeader); + msrdata |= SYSCFG_MSR_MtrrFixDramModEn; + LibAmdMsrWrite(SYS_CFG, &msrdata, &StdHeader); + + /* Now restore the Fixed MTRRs */ + msrdata = *msrPtr; + msrPtr++; + LibAmdMsrWrite(0x250, &msrdata, &StdHeader); + + msrdata = *msrPtr; + msrPtr++; + LibAmdMsrWrite(0x258, &msrdata, &StdHeader); + + msrdata = *msrPtr; + msrPtr++; + LibAmdMsrWrite(0x259, &msrdata, &StdHeader); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msrdata = *msrPtr; + msrPtr++; + LibAmdMsrWrite(msr, &msrdata, &StdHeader); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + LibAmdMsrRead(SYS_CFG, &msrdata, &StdHeader); + msrdata &= ~SYSCFG_MSR_MtrrFixDramModEn; + LibAmdMsrWrite(SYS_CFG, &msrdata, &StdHeader); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msrdata = *msrPtr; + msrPtr++; + LibAmdMsrWrite(msr, &msrdata, &StdHeader); + } + + /* Restore SYSCFG MTRR */ + msrdata = *msrPtr; + msrPtr++; + LibAmdMsrWrite(SYS_CFG, &msrdata, &StdHeader); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void *resume_backup_memory) +{ +#if 0 + u32 *sp, index; + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6], sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif + + memcopy(resume_backup_memory, (void *)BSP_STACK_BASE_ADDR, + (HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (resume_backup_memory - BSP_STACK_BASE_ADDR) + :); + +#if 0 + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6],sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + AMD_CONFIG_PARAMS StdHeader; + u32 spi_address; + UINT64 MsrReg; + PCI_ADDR PciAddress; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 PciValue; + u32 i; + + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 0x14; + PciAddress.Address.Function = 3; + PciAddress.Address.Register = 0xA0; + + LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &StdHeader); + spi_address = PciValue & ~0x1F; + + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + /* Enable access to AMD RdDram and WrDram extension bits */ + LibAmdMsrRead(SYS_CFG, &MsrReg, &StdHeader); + MsrReg |= SYSCFG_MSR_MtrrFixDramModEn; + LibAmdMsrWrite(SYS_CFG, &MsrReg, &StdHeader); + + /* Fixed MTRRs */ + LibAmdMsrRead(0x250, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + + LibAmdMsrRead(0x258, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + + LibAmdMsrRead(0x259, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + LibAmdMsrRead(i, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + LibAmdMsrRead(SYS_CFG, &MsrReg, &StdHeader); + MsrReg &= ~SYSCFG_MSR_MtrrFixDramModEn; + LibAmdMsrWrite(SYS_CFG, &MsrReg, &StdHeader); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + LibAmdMsrRead(i, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + } + + /* SYS_CFG */ + LibAmdMsrRead(0xC0010010, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + + /* TOM */ + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + + /* TOM2 */ + LibAmdMsrRead(0xC001001D, &MsrReg, &StdHeader); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *(u32 *) & MsrReg); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, *((u32 *) & MsrReg + 1)); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + LibAmdMemCopy((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize, &StdHeader); + } +} + +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; + u32 PciValue; +#ifndef __PRE_RAM__ + u32 spi_address, data; + u32 nvram_pos; +#endif + AMD_CONFIG_PARAMS StdHeader; + PCI_ADDR PciAddress; + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + PciAddress.Address.Bus = 0; + PciAddress.Address.Device = 0x14; + PciAddress.Address.Function = 3; + PciAddress.Address.Register = 0xA0; + + LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &StdHeader); + +#ifndef __PRE_RAM__ + spi_address = PciValue & ~0x1F; + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + readSPIID((u8 *) spi_address); + writeSPIStatus((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sectorEraseSPI((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sectorEraseSPI((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } +#endif + + return AGESA_SUCCESS; +} + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..d8150e4 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + + +void inline __attribute__ ((always_inline)) memcopy(void *dest, const void *src, + unsigned long bytes); +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void *resume_backup_memory); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 2ccb38a..59ccff6 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -650,6 +650,10 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif + /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { @@ -664,6 +668,12 @@ void pci_dev_init(struct device *dev) ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return; +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* Don't re-run roms on s3 resume. */ + if (acpi_slp_type == 3) + return; +#endif + rom = pci_rom_probe(dev); if (rom == NULL) return; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..b7207b9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -25,11 +25,16 @@ extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) +#ifdef CONFIG_RESUME_SCRATCH_MEMORY_SIZE +#define HIGH_SCRATCH_MEMORY_SIZE CONFIG_RESUME_SCRATCH_MEMORY_SIZE #else -#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE +#define HIGH_SCRATCH_MEMORY_SIZE 0 #endif +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) +#else /* CONFIG_HAVE_ACPI_RESUME */ +#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..18f05b5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -176,6 +176,8 @@ void *cbmem_find(u32 id) return NULL; for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { + printk(BIOS_SPEW, "CBMEM TOC ID %d is: %x base: %x%x\n", i, + (u32) cbmem_toc[i].id, (u32) (cbmem_toc[i].base >> 32), (u32) cbmem_toc[i].base); if (cbmem_toc[i].id == id) return (void *)(unsigned long)cbmem_toc[i].base; } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b2ca256..759f0c2 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -332,11 +333,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; @@ -691,12 +687,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)high_tables_size, high_tables_base); } #endif @@ -721,17 +717,18 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n",uma_memory_base); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx, ",uma_memory_base); #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024)- HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - } + high_tables_size = HIGH_MEMORY_SIZE; + } #endif } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n",mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); +printk(BIOS_DEBUG, " adsr - high_tables_base=%x%x\n", (u32) (high_tables_base >> 32), (u32) high_tables_base); #if CONFIG_GFXUMA == 1 printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); @@ -746,22 +743,46 @@ printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } +extern u8 acpi_slp_type; static void domain_enable_resources(device_t dev) { u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -795,24 +816,41 @@ static void cpu_bus_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) +static u32 cpu_bus_scan(device_t dev, u32 max) { - struct device_path cpu_path; device_t cpu; - int apic_id; - - initialize_cpus(dev->link_list); + struct device_path cpu_path; + int apic_id, cores_found; + + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); + + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } + } + return max; +} - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - } +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } @@ -858,7 +896,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; From gerrit at coreboot.org Mon Feb 13 11:09:03 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Mon, 13 Feb 2012 11:09:03 +0100 Subject: [coreboot] New patch to review for coreboot: 16d4da3 S3 code in the mainboard. Persimmon is a demo board. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 16d4da3acc42e53e7bef775c5c4e754a1fd43c5d Author: zbao Date: Mon Feb 13 17:34:34 2012 +0800 S3 code in the mainboard. Persimmon is a demo board. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao --- src/mainboard/amd/persimmon/BiosCallOuts.c | 75 +++++---- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 1 + .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 173 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 18 ++- src/mainboard/amd/persimmon/mainboard.c | 15 ++- src/mainboard/amd/persimmon/romstage.c | 90 ++++++++-- 11 files changed, 327 insertions(+), 62 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index c8379ff..df00c7c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS CalloutStatus; UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + /* + * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func); + */ + CalloutStatus = AGESA_UNSUPPORTED; for (i = 0; i < CallOutCount; i++) { @@ -95,28 +99,30 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -224,32 +230,33 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); PrevNodeOffset = AllocNodeOffset; - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { if (AllocNodePtr->NextNodeOffset == 0) { return AGESA_BOUNDS_CHK; } @@ -348,8 +355,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e01e101..01ea3a8 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..2f69e01 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..53ca04c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,12 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include +#include #define FILECODE UNASSIGNED_FILE_FILECODE @@ -243,6 +245,35 @@ agesawrapper_amdinitearly ( return (UINT32)status; } + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrReg; + UINT32 sys_mem, uma_base, uma_size; + + /* TOP_MEM: the top of DRAM below 4G */ + LibAmdMsrRead(TOP_MEM, &MsrReg, StdHeader); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = (UINT32)(MsrReg & 0xFFFFFFFFUL) + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((MsrReg & 0x0000000F00000000) || (sys_mem >= 0x80000000)) { + uma_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_base = (UINT32)(MsrReg & 0xFFFFFFFFUL) - uma_size ; /* TOP_MEM1 */ + return uma_base - BIOS_HEAP_SIZE; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +303,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +527,146 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..0b79e5f 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE //FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE //FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..fef7d60 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..23eea86 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include #include #include -#include #include -//#include +#include +#include #include "chip.h" +#include "BiosCallOuts.h" +#include +#include void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..cc20c36 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(resume_backup_memory + HIGH_MEMORY_SAVE); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcopy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50); From gerrit at coreboot.org Mon Feb 13 11:09:03 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Mon, 13 Feb 2012 11:09:03 +0100 Subject: [coreboot] New patch to review for coreboot: 0bb3bba Whitespaces changes. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/625 -gerrit commit 0bb3bba33f27110e1f6c61bd517822300eca9f3e Author: zbao Date: Mon Feb 13 17:36:29 2012 +0800 Whitespaces changes. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao --- src/mainboard/amd/persimmon/BiosCallOuts.c | 45 +++++++------ src/mainboard/amd/persimmon/PlatformGnbPcie.c | 1 - src/mainboard/amd/persimmon/get_bus_conf.c | 3 +- src/mainboard/amd/persimmon/mainboard.c | 1 + src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 10 ++-- src/vendorcode/amd/agesa/f14/gcccar.inc | 84 ++++++++++++------------ 6 files changed, 74 insertions(+), 70 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index df00c7c..06426c2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -155,8 +155,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. + to the end of the allocated nodes list. */ + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -205,7 +206,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; @@ -290,10 +291,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Clear the BufferSize and NextNodeOffset of the previous first node */ FreedNodePtr->BufferSize = 0; FreedNodePtr->NextNodeOffset = 0; + } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -301,21 +303,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; } else { /* Traverse list of freed nodes to find where the deallocated node - should be place + should be place */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); } /* If deallocated node is adjacent to the next node, - concatenate both nodes + concatenate both nodes */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -329,13 +331,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* If deallocated node is adjacent to the previous node, - concatenate both nodes + concatenate both nodes */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; AllocNodePtr->NextNodeOffset = 0; } else { @@ -405,17 +408,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) // 0xCF9 (Reset Port). // switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: break; - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - default: + default: break; } @@ -562,13 +565,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case 4: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 @@ -578,13 +581,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 6: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 @@ -594,13 +597,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 7: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 2f69e01..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -166,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index fef7d60..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -136,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 23eea86..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -121,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index ac613b1..a48d737 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -25,7 +25,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -33,10 +33,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,7 +47,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 981d976..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1,7 +1,7 @@ /* * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + /****************************************************************************** * AMD Generic Encapsulated Software Architecture * @@ -158,28 +158,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -194,12 +194,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -220,7 +220,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -252,9 +252,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - + mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B _RDMSR bt $APIC_BSC, %eax # Is this the BSC? @@ -263,7 +263,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -291,7 +291,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -324,7 +324,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -347,7 +347,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -371,7 +371,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -427,7 +427,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -589,7 +589,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -893,7 +893,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -973,7 +973,7 @@ fam15_enable_stack_hook_exit: btr $DIS_HW_PF, %eax # Turn on hardware prefetches #.endif # End workaround for erratum 498 0: - _WRMSR + _WRMSR #-------------------------------------------------------------------------- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- @@ -1135,7 +1135,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1240,7 +1240,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1308,7 +1308,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1344,20 +1344,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1428,7 +1428,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1584,7 +1584,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address From svn at coreboot.org Mon Feb 13 16:00:01 2012 From: svn at coreboot.org (coreboot tracker) Date: Mon, 13 Feb 2012 16:00:01 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Mon Feb 13 21:15:22 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 13 Feb 2012 21:15:22 +0100 Subject: [coreboot] New patch to review for coreboot: b23d0dc Intel cpus: Include CAR from socket References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/626 -gerrit commit b23d0dc51cc42e08152e63753ed7e87455f8dd16 Author: Ky?sti M?lkki Date: Mon Feb 13 13:38:27 2012 +0200 Intel cpus: Include CAR from socket It was not obvious which CAR was compiled in. Also build would fail if a socket included two models with both having an include for CAR. Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_6ex/Makefile.inc | 1 - src/cpu/intel/socket_LGA771/Makefile.inc | 1 + src/cpu/intel/socket_mFCPGA478/Makefile.inc | 1 + 3 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 0053ae7..cc4dc7b 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,4 +1,3 @@ driver-y += model_6ex_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc index 319430f..ef520a3 100644 --- a/src/cpu/intel/socket_LGA771/Makefile.inc +++ b/src/cpu/intel/socket_LGA771/Makefile.inc @@ -9,3 +9,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index 74433a2..29973af 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -12,3 +12,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc From gerrit at coreboot.org Mon Feb 13 21:15:22 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 13 Feb 2012 21:15:22 +0100 Subject: [coreboot] Patch set updated for coreboot: e98ccb1 Intel cpus: refactor cache_as_ram code References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit e98ccb15cfbc571481efddbb8f8ee487bbe327b7 Author: Ky?sti M?lkki Date: Mon Feb 13 20:58:43 2012 +0200 Intel cpus: refactor cache_as_ram code Copies a unified model_6ex, 6fx and 106cx cache_as_ram.inc code over the originals for diff and review. Also copies the code as car/cache_as_ram_ht.inc to diff and review changes for hyper-threaded CPU support on 0xf family. Not ready for merge. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 302 ++++++++++++++++++++++++++++ src/cpu/intel/model_106cx/cache_as_ram.inc | 115 ++++++++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 97 ++++++--- src/cpu/intel/model_6fx/cache_as_ram.inc | 93 ++++++--- 4 files changed, 513 insertions(+), 94 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..5388b7d --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1UL << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + +#if CORE2_PREFETCH_DISABLE + /* Disable prefetchers */ + movl $0x01a0, %ecx + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable variable MTRRs. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + +#if CORE_L2CACHE_MSR + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr +#endif + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + invd + + /* Clear the cache memory reagion. */ + cld + xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + rep stosl + +#if SPURIOUS_CACHE_CTRL + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 +#endif + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + +#if SPURIOUS_CACHE_CTRL + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 +#endif + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp +#endif + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call mainboard/romstage.c: main(). */ + call main + addl $4, %esp + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + +#if ENABLE_BOOTROM_CACHE + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + +#if CORE2_PREFETCH_DISABLE + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index eb3d650..5388b7d 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -21,6 +21,27 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1UL << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -32,9 +53,18 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + +#if CORE2_PREFETCH_DISABLE + /* Disable prefetchers */ + movl $0x01a0, %ecx + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr +#endif /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -63,40 +93,44 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax - xorl %edx, %edx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr +#if CORE_L2CACHE_MSR /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if SPURIOUS_CACHE_CTRL /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -112,24 +146,25 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ +#if SPURIOUS_CACHE_CTRL /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -138,8 +173,9 @@ clear_mtrrs: post_code(0x23) - /* Call romstage.c main function. */ + /* Call mainboard/romstage.c: main(). */ call main + addl $4, %esp post_code(0x2f) @@ -155,24 +191,12 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -190,15 +214,29 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + +#if ENABLE_BOOTROM_CACHE + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif post_code(0x39) @@ -212,11 +250,20 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) +#if CORE2_PREFETCH_DISABLE + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + /* Invalidate the cache again. */ invd diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 18ada29..5388b7d 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -21,6 +21,27 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1UL << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -32,9 +53,18 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + +#if CORE2_PREFETCH_DISABLE + /* Disable prefetchers */ + movl $0x01a0, %ecx + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr +#endif /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -64,39 +94,43 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $MTRRdefTypeEn, %eax wrmsr +#if CORE_L2CACHE_MSR /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if SPURIOUS_CACHE_CTRL /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -112,24 +146,25 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ +#if SPURIOUS_CACHE_CTRL /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -138,8 +173,9 @@ clear_mtrrs: post_code(0x23) - /* Call romstage.c main function. */ + /* Call mainboard/romstage.c: main(). */ call main + addl $4, %esp post_code(0x2f) @@ -161,18 +197,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -190,16 +214,19 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif +#if ENABLE_BOOTROM_CACHE /* Enable caching and Speculative Reads for the last 4MB. */ movl $MTRRphysBase_MSR(1), %ecx movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax @@ -207,8 +234,9 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) @@ -227,6 +255,15 @@ clear_mtrrs: post_code(0x3b) +#if CORE2_PREFETCH_DISABLE + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + /* Invalidate the cache again. */ invd diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index dfc4f3b..5388b7d 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -21,6 +21,27 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1UL << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -32,16 +53,18 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) +#if CORE2_PREFETCH_DISABLE /* Disable prefetchers */ movl $0x01a0, %ecx rdmsr orl $((1 << 9) | (1 << 19)), %eax orl $((1 << 5) | (1 << 7)), %edx wrmsr +#endif /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -71,39 +94,43 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $MTRRdefTypeEn, %eax wrmsr +#if CORE_L2CACHE_MSR /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if SPURIOUS_CACHE_CTRL /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -119,24 +146,25 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ +#if SPURIOUS_CACHE_CTRL /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -145,8 +173,9 @@ clear_mtrrs: post_code(0x23) - /* Call romstage.c main function. */ + /* Call mainboard/romstage.c: main(). */ call main + addl $4, %esp post_code(0x2f) @@ -168,18 +197,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -197,15 +214,29 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif + +#if ENABLE_BOOTROM_CACHE + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif post_code(0x39) @@ -224,12 +255,14 @@ clear_mtrrs: post_code(0x3b) +#if CORE2_PREFETCH_DISABLE /* Enable prefetchers */ movl $0x01a0, %ecx rdmsr andl $~((1 << 9) | (1 << 19)), %eax andl $~((1 << 5) | (1 << 7)), %edx wrmsr +#endif /* Invalidate the cache again. */ invd From gerrit at coreboot.org Mon Feb 13 21:54:23 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 13 Feb 2012 21:54:23 +0100 Subject: [coreboot] Patch merged into coreboot/master: 26ddf1e libpayload: code cosmetics References: Message-ID: the following patch was just integrated into master: commit 26ddf1e0580b4b31a4576760bdbe6f640eb8fd72 Author: Mathias Krause Date: Wed Feb 8 10:32:57 2012 +0100 libpayload: code cosmetics Be consistend with coding style at least within a function -- don't mix sizeof with plain values. Change-Id: Iefb5b7fe4f54977f5505fc9cea65c9c4af3e7f3a Signed-off-by: Mathias Krause Build-Tested: build bot (Jenkins) at Fri Feb 10 12:03:32 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 10 23:37:19 2012, giving +2 See http://review.coreboot.org/617 for details. -gerrit From gerrit at coreboot.org Mon Feb 13 21:56:40 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 13 Feb 2012 21:56:40 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1a82de2 AMD Geode cpus: apply un-written naming rules References: Message-ID: the following patch was just integrated into master: commit 1a82de2b58c285fed98ced2af76a61b02afba3ed Author: Ky?sti M?lkki Date: Thu Feb 9 16:07:41 2012 +0200 AMD Geode cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Rename directories and Kconfig as follows: model_lx -> geode_lx model_gx1 -> geode_gx1 model_gx2 -> geode_gx2 Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Thu Feb 9 15:24:18 2012, giving +1 Reviewed-By: Stefan Reinauer at Thu Feb 9 19:45:31 2012, giving +2 See http://review.coreboot.org/613 for details. -gerrit From gerrit at coreboot.org Mon Feb 13 22:54:51 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Mon, 13 Feb 2012 22:54:51 +0100 Subject: [coreboot] Patch set updated for coreboot: 00fc118 Intel cpus: refactor cache_as_ram code References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 00fc118095f4760390bcac8ff8c6261291e0e05f Author: Ky?sti M?lkki Date: Mon Feb 13 23:38:51 2012 +0200 Intel cpus: refactor cache_as_ram code Copies a unified model_6ex, 6fx and 106cx cache_as_ram.inc code over the originals for diff and review. Also copies the code as car/cache_as_ram_ht.inc to diff and review changes for hyper-threaded CPU support on 0xf family. Not ready for merge. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 302 ++++++++++++++++++++++++++++ src/cpu/intel/model_106cx/cache_as_ram.inc | 115 ++++++++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 97 ++++++--- src/cpu/intel/model_6fx/cache_as_ram.inc | 93 ++++++--- 4 files changed, 513 insertions(+), 94 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..2ed1e60 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,302 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + +#if CORE2_PREFETCH_DISABLE + /* Disable prefetchers */ + movl $0x01a0, %ecx + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable variable MTRRs. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + +#if CORE_L2CACHE_MSR + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr +#endif + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + invd + + /* Clear the cache memory reagion. */ + cld + xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + rep stosl + +#if SPURIOUS_CACHE_CTRL + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 +#endif + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + +#if SPURIOUS_CACHE_CTRL + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 +#endif + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp +#endif + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call mainboard/romstage.c: main(). */ + call main + addl $4, %esp + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + +#if ENABLE_BOOTROM_CACHE + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + +#if CORE2_PREFETCH_DISABLE + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index eb3d650..2ed1e60 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -21,6 +21,27 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -32,9 +53,18 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + +#if CORE2_PREFETCH_DISABLE + /* Disable prefetchers */ + movl $0x01a0, %ecx + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr +#endif /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -63,40 +93,44 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax - xorl %edx, %edx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr +#if CORE_L2CACHE_MSR /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if SPURIOUS_CACHE_CTRL /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -112,24 +146,25 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ +#if SPURIOUS_CACHE_CTRL /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -138,8 +173,9 @@ clear_mtrrs: post_code(0x23) - /* Call romstage.c main function. */ + /* Call mainboard/romstage.c: main(). */ call main + addl $4, %esp post_code(0x2f) @@ -155,24 +191,12 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -190,15 +214,29 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + +#if ENABLE_BOOTROM_CACHE + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif post_code(0x39) @@ -212,11 +250,20 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) +#if CORE2_PREFETCH_DISABLE + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + /* Invalidate the cache again. */ invd diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 18ada29..2ed1e60 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -21,6 +21,27 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -32,9 +53,18 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + +#if CORE2_PREFETCH_DISABLE + /* Disable prefetchers */ + movl $0x01a0, %ecx + rdmsr + orl $((1 << 9) | (1 << 19)), %eax + orl $((1 << 5) | (1 << 7)), %edx + wrmsr +#endif /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -64,39 +94,43 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $MTRRdefTypeEn, %eax wrmsr +#if CORE_L2CACHE_MSR /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if SPURIOUS_CACHE_CTRL /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -112,24 +146,25 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ +#if SPURIOUS_CACHE_CTRL /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -138,8 +173,9 @@ clear_mtrrs: post_code(0x23) - /* Call romstage.c main function. */ + /* Call mainboard/romstage.c: main(). */ call main + addl $4, %esp post_code(0x2f) @@ -161,18 +197,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -190,16 +214,19 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif +#if ENABLE_BOOTROM_CACHE /* Enable caching and Speculative Reads for the last 4MB. */ movl $MTRRphysBase_MSR(1), %ecx movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax @@ -207,8 +234,9 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif post_code(0x39) @@ -227,6 +255,15 @@ clear_mtrrs: post_code(0x3b) +#if CORE2_PREFETCH_DISABLE + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr +#endif + /* Invalidate the cache again. */ invd diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index dfc4f3b..2ed1e60 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -21,6 +21,27 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +/* Code for CORE (from model_6ex), not for family<6? */ +#define CORE_L2CACHE_MSR 1 + +/* Code for CORE2 (from model_6fx), not built. */ +#define CORE2_PREFETCH_DISABLE 0 + +/* MAXPHYADDR for Atom (model_106cx) is 32. */ +#if CONFIG_CPU_INTEL_MODEL_106CX +#define CPU_MAXPHYADDR 32 +#else +#define CPU_MAXPHYADDR 36 +#endif +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + +#define ENABLE_BOOTROM_CACHE 1 +#define SPURIOUS_CACHE_CTRL 1 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -32,16 +53,18 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) +#if CORE2_PREFETCH_DISABLE /* Disable prefetchers */ movl $0x01a0, %ecx rdmsr orl $((1 << 9) | (1 << 19)), %eax orl $((1 << 5) | (1 << 7)), %edx wrmsr +#endif /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -71,39 +94,43 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $MTRRdefTypeEn, %eax wrmsr +#if CORE_L2CACHE_MSR /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if SPURIOUS_CACHE_CTRL /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -119,24 +146,25 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ +#if SPURIOUS_CACHE_CTRL /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -145,8 +173,9 @@ clear_mtrrs: post_code(0x23) - /* Call romstage.c main function. */ + /* Call mainboard/romstage.c: main(). */ call main + addl $4, %esp post_code(0x2f) @@ -168,18 +197,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -197,15 +214,29 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ +#if CONFIG_RAMTOP + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx wrmsr +#endif + +#if ENABLE_BOOTROM_CACHE + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif post_code(0x39) @@ -224,12 +255,14 @@ clear_mtrrs: post_code(0x3b) +#if CORE2_PREFETCH_DISABLE /* Enable prefetchers */ movl $0x01a0, %ecx rdmsr andl $~((1 << 9) | (1 << 19)), %eax andl $~((1 << 5) | (1 << 7)), %edx wrmsr +#endif /* Invalidate the cache again. */ invd From gerrit at coreboot.org Tue Feb 14 00:52:47 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 00:52:47 +0100 Subject: [coreboot] New patch to review for coreboot: f299de3 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/627 -gerrit commit f299de3e00821ddbbe8682c302497228eca968df Author: Marc Jones Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones --- src/cpu/amd/mtrr/amd_mtrr.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index c5e01b1..2348b22 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -114,8 +114,9 @@ void amd_setup_mtrrs(void) msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later const int cpu_id = cpuid_eax(0x80000001); + printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); const int has_tom2wb = - (((cpu_id>>8 )&0xf) > 0xf) || // Family > 0F + (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables if(has_tom2wb) From gerrit at coreboot.org Tue Feb 14 00:59:41 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 00:59:41 +0100 Subject: [coreboot] New patch to review for coreboot: 41897bc IEI Kino Fam10 ACPI table fixes. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/628 -gerrit commit 41897bc521632641b9b9053a73caa9d828019bba Author: Dave Frodin Date: Thu Feb 2 14:07:43 2012 -0700 IEI Kino Fam10 ACPI table fixes. Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup. Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def Signed-off-by: Marc Jones --- .../iei/kino-780am2-fam10/acpi/routing.asl | 80 +++++++---- src/mainboard/iei/kino-780am2-fam10/acpi_tables.c | 153 ++++++++------------ src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 34 ++++- 3 files changed, 139 insertions(+), 128 deletions(-) diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl index 7b581b4..76a9bfa 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/routing.asl @@ -31,6 +31,8 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -57,22 +59,45 @@ Scope(\_SB) { Package(){0x0007FFFF, 1, INTA, 0 }, Package(){0x0007FFFF, 2, INTB, 0 }, Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices */ /* Bus 0, Dev 17 - SATA controller #2 */ /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTA, 0 }, + Package(){0x0011FFFF, 0, INTG, 0 }, /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; * EHCI, dev 18, 19 func 2 */ Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, Package(){0x0012FFFF, 2, INTC, 0 }, + Package(){0x0012FFFF, 3, INTD, 0 }, Package(){0x0013FFFF, 0, INTC, 0 }, Package(){0x0013FFFF, 1, INTD, 0 }, Package(){0x0013FFFF, 2, INTA, 0 }, + Package(){0x0013FFFF, 3, INTB, 0 }, /* Package(){0x0014FFFF, 1, INTA, 0 }, */ @@ -81,6 +106,12 @@ Scope(\_SB) { Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, Package(){0x0014FFFF, 3, INTD, 0 }, + +/* Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, +*/ }) Name(APR0, Package(){ @@ -129,11 +160,13 @@ Scope(\_SB) { /* Package(){0x0009FFFF, 1, 0, 16 }, */ /* Package(){0x0009FFFF, 2, 0, 17 }, */ /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, /* Package(){0x000AFFFF, 1, 0, 16 }, */ /* Package(){0x000AFFFF, 2, 0, 17 }, */ /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ @@ -146,41 +179,34 @@ Scope(\_SB) { Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 1, 0, 17 }, Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0012FFFF, 3, 0, 19 }, Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 19 }, Package(){0x0013FFFF, 2, 0, 16 }, - - /* Package(){0x00140000, 0, 0, 16 }, */ - - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ + Package(){0x0013FFFF, 3, 0, 17 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ }) Name(PR1, Package(){ /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, + Package(){0x0005FFFF, 0, INTC, 0 }, + Package(){0x0005FFFF, 1, INTD, 0 }, + Package(){0x0005FFFF, 2, INTA, 0 }, + Package(){0x0005FFFF, 3, INTB, 0 }, }) Name(APR1, Package(){ /* Internal graphics - RS780 VGA, Bus1, Dev5 */ Package(){0x0005FFFF, 0, 0, 18 }, Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ + Package(){0x0005FFFF, 2, 0, 16 }, + Package(){0x0005FFFF, 3, 0, 17 }, }) Name(PS2, Package(){ @@ -201,10 +227,10 @@ Scope(\_SB) { Name(PS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS4, Package(){ @@ -272,10 +298,10 @@ Scope(\_SB) { Name(APS9, Package(){ /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, }) Name(PSa, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ @@ -288,9 +314,9 @@ Scope(\_SB) { Name(APSa, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, }) Name(PCIB, Package(){ diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c index 1b2ea6e..8e3656d 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c +++ b/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,13 +20,13 @@ #include #include #include +#include #include #include #include #include #include #include - #include "mb_sysconf.h" #define DUMP_ACPI_TABLES 0 @@ -50,12 +50,33 @@ static void dump_mem(u32 start, u32 end) extern const unsigned char AmlCode[]; extern const unsigned char AmlCode_ssdt[]; -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + + /* TODO: More HT and other tables need to go into this table generation. + * This should also be moved out to the silicon level if it can. + */ + + return (unsigned long) (acpigen_get_current()); +} unsigned long acpi_fill_mcfg(unsigned long current) { @@ -69,8 +90,8 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -101,11 +122,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -127,6 +143,31 @@ unsigned long write_acpi_tables(unsigned long start) acpi_write_rsdp(rsdp, rsdt, NULL); acpi_write_rsdt(rsdt); + /* DSDT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); + dsdt = (acpi_header_t *)current; // it will used by fadt + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + /* FACS */ // it needs 64 bit alignment + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); + facs = (acpi_facs_t *) current; // it will be used by fadt + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* FADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + /* * We explicitly add these tables later on: */ @@ -162,87 +203,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); + ssdt = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;ilength; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); - - /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); - facs = (acpi_facs_t *) current; // it will be used by fadt - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - - /* FADT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); - fadt = (acpi_fadt_t *) current; - current += sizeof(acpi_fadt_t); - - acpi_create_fadt(fadt, facs, dsdt); - acpi_add_table(rsdp, fadt); #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 8dd0e21..7ae6bd5 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1168,7 +1168,7 @@ DefinitionBlock ( /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) /* ( >> 20) to make it fit into 32 bit for XP */ + External (TOM2) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1421,7 +1421,7 @@ DefinitionBlock ( IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - +#if 0 /* defined by HPET table? */ Device(HPTM) { Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { @@ -1436,6 +1436,7 @@ DefinitionBlock ( Return(CRS) } } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif } /* end LIBR */ Device(HPBR) { @@ -1450,7 +1451,7 @@ DefinitionBlock ( Name(_ADR, 0x00140006) } /* end Ac97modem */ - /* SIO Support */ + /* f71859 Support */ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { @@ -1546,6 +1547,7 @@ DefinitionBlock ( Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1585,12 +1587,14 @@ DefinitionBlock ( ,, PEBM ) - +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - +#if 0 CreateDWordField(CRES, ^EMM1._BAS, EM1B) CreateDWordField(CRES, ^EMM1._LEN, EM1L) CreateDWordField(CRES, ^DMLO._BAS, DMLB) @@ -1614,8 +1618,7 @@ DefinitionBlock ( /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) + * Subtract(TOM2, 0x100000000, DMHL) * } */ @@ -1628,6 +1631,21 @@ DefinitionBlock ( ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ Store(PBLN,EBML) } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ From gerrit at coreboot.org Tue Feb 14 00:59:42 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 00:59:42 +0100 Subject: [coreboot] New patch to review for coreboot: 25ccaa5 IEI-Kino Fam10 MPtable fix. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/629 -gerrit commit 25ccaa54982ced9c697f58dc978a0d252763e766 Author: Dave Frodin Date: Thu Feb 2 13:38:50 2012 -0700 IEI-Kino Fam10 MPtable fix. Make changes to MPtable to match the ACPI tables. Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1 Signed-off-by: Marc Jones --- src/mainboard/iei/kino-780am2-fam10/mptable.c | 39 ++++++++++++++++++++---- 1 files changed, 32 insertions(+), 7 deletions(-) diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 4bf3480..66423e5 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -107,8 +107,30 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* changes added to match acpi tables */ + PCI_INT(0x0, 0x02, 0x0, 0x12); + PCI_INT(0x0, 0x03, 0x0, 0x13); + PCI_INT(0x0, 0x04, 0x0, 0x10); + PCI_INT(0x0, 0x09, 0x0, 0x11); + PCI_INT(0x0, 0x0A, 0x0, 0x12); + PCI_INT(0x0, 0x12, 0x2, 0x12); + PCI_INT(0x0, 0x12, 0x3, 0x13); + PCI_INT(0x0, 0x13, 0x2, 0x10); + PCI_INT(0x0, 0x13, 0x2, 0x11); + PCI_INT(0x0, 0x14, 0x1, 0x11); + PCI_INT(0x0, 0x14, 0x3, 0x13); + PCI_INT(0x1, 0x05, 0x2, 0x10); + PCI_INT(0x1, 0x05, 0x3, 0x11); + PCI_INT(0x2, 0x00, 0x0, 0x12); + PCI_INT(0x2, 0x00, 0x1, 0x13); + PCI_INT(0x2, 0x00, 0x2, 0x10); + PCI_INT(0x2, 0x00, 0x3, 0x11); + + /* RS780 PCI to PCI bridge (PCIE port 4) */ + PCI_INT(0x0, 0x09, 0x0, 0x11); + /* usb */ - PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ PCI_INT(0x0, 0x12, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x0, 0x12); PCI_INT(0x0, 0x13, 0x1, 0x13); @@ -118,22 +140,25 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + PCI_INT(0x0, 0x14, 0x2, 0x12); /* on board NIC & Slot PCIE. */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ -/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ - PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ + /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ + PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */ + PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */ + /* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); */ /* Dev 2, external GFX */ /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ - PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); + /* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */ /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); */ - PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); - PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ + /* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */ + PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */ + /* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */ /* PCI slots */ /* PCI_SLOT 0. */ From gerrit at coreboot.org Tue Feb 14 01:11:21 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 01:11:21 +0100 Subject: [coreboot] New patch to review for coreboot: 213eb80 Force SB800 bootblock to use I/O for PCI config References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/630 -gerrit commit 213eb80a8a071403ca9448dc08b8e00b95f31e67 Author: Dave Frodin Date: Thu Feb 2 14:56:23 2012 -0700 Force SB800 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O. Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0 Signed-off-by: Marc Jones --- src/southbridge/amd/sb800/bootblock.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 18eae24..30d6ac6 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -39,15 +39,15 @@ static void sb800_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -57,9 +57,9 @@ static void sb800_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void) From gerrit at coreboot.org Tue Feb 14 01:11:24 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 01:11:24 +0100 Subject: [coreboot] New patch to review for coreboot: 3a72344 Force SB700 bootblock code to use I/O for PCI config cycles. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/631 -gerrit commit 3a7234421e81fa4a5b86be12de07c220ac0ccf5b Author: Dave Frodin Date: Wed Feb 1 16:15:08 2012 -0700 Force SB700 bootblock code to use I/O for PCI config cycles. If PCI config cycles use MMIO instead of I/O in the SB700 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is specified by the mainboards Kconfig. Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672 Signed-off-by: Marc Jones --- src/southbridge/amd/sb700/bootblock.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 377bffc..370cff9 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -41,15 +41,15 @@ static void sb700_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -59,9 +59,9 @@ static void sb700_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void) From gerrit at coreboot.org Tue Feb 14 01:11:26 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 01:11:26 +0100 Subject: [coreboot] New patch to review for coreboot: 0d7d667 Force SB600 bootblock to use I/O for PCI config References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/632 -gerrit commit 0d7d6676e9c1def4d26432aa481752dbbabd3bec Author: Dave Frodin Date: Thu Feb 2 14:50:02 2012 -0700 Force SB600 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the SB600 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is defined by the mainboards Kconfig. Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd Signed-off-by: Marc Jones --- src/southbridge/amd/sb600/bootblock.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 7007622..45991ee 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -37,19 +37,19 @@ static void sb600_enable_rom(void) u8 reg8; device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB600_LPC), 0); + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB600_LPC), 0); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -59,9 +59,9 @@ static void sb600_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* 4 MB */ /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void) From gerrit at coreboot.org Tue Feb 14 01:21:34 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 01:21:34 +0100 Subject: [coreboot] New patch to review for coreboot: 95aad86 Fixes Fam10/SR5650 cpu not recognized message. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/633 -gerrit commit 95aad867212c87fde722934a536e14ca78f0c9f9 Author: Dave Frodin Date: Thu Feb 2 15:08:22 2012 -0700 Fixes Fam10/SR5650 cpu not recognized message. Extend the Family10 revisions checked byt the printk message. Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44 Signed-off-by: Marc Jones --- src/southbridge/amd/sr5650/early_setup.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 50f836e..32bdd7f 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -91,7 +91,7 @@ static void get_cpu_rev(void) printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); - else if (eax <= 0x100f00) + else if (eax <= 0x100fa0) printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); else printk(BIOS_INFO, "CPU Rev is not recognized.\n"); From gerrit at coreboot.org Tue Feb 14 09:41:16 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 14 Feb 2012 09:41:16 +0100 Subject: [coreboot] Patch set updated for coreboot: 7a8a868 Add support for RAM-less multi-processor init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 7a8a868d369166d2f9821c1d61bfe54bfc28b92b Author: Ky?sti M?lkki Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..0bdef34 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -31,6 +31,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help From GNUtoo at no-log.org Tue Feb 14 13:23:20 2012 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Tue, 14 Feb 2012 13:23:20 +0100 Subject: [coreboot] New patch to review for coreboot: f299de3 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. In-Reply-To: References: Message-ID: <201202141323.20839.GNUtoo@no-log.org> hi, I've tried this patch, here's what it produce as log: From the linux kernel: [ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) And: [ 0.308271] mtrr: your CPUs had inconsistent variable MTRR settings [ 0.308272] mtrr: probably your BIOS does not setup all CPUs. [ 0.308273] mtrr: corrected configuration. And I think my CPU is covered by your patch: CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB Also, without pci=nocrs Xorg don't initialize. I've attached the full log(compressed with xz) Thanks a lot for working on this. Denis. -------------- next part -------------- A non-text attachment was scrubbed... Name: coreboot.xz Type: application/x-xz Size: 20108 bytes Desc: not available URL: From GNUtoo at no-log.org Tue Feb 14 13:31:35 2012 From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli) Date: Tue, 14 Feb 2012 13:31:35 +0100 Subject: [coreboot] "Fix multipleVGA cards resource conflict on Windows" broke my vga Message-ID: <201202141331.35029.GNUtoo@no-log.org> hi, I've an M4A785T-M which contains one onboard graphic card, but it has 2 VGA extension roms. one seem to be for HDMI, and the other for VGA. reverting the commit makes VGA appear on my monitor. I've tried to add one option rom only, as usual, and nothing appeared on my monitor with that comit. Then I removed the VGA rom and with cbfstool I added both VGA rom. Nothing appeared on my monitor either... Should I give some logs(it's quite long to get since I've to reflash with an external programmer). Denis. From r.marek at assembler.cz Tue Feb 14 18:04:06 2012 From: r.marek at assembler.cz (Rudolf Marek) Date: Tue, 14 Feb 2012 18:04:06 +0100 Subject: [coreboot] Asus M2V-MX problems In-Reply-To: <4F2F58EE.1030408@gmail.com> References: <4F285EF6.4010604@assembler.cz> <4F2F58EE.1030408@gmail.com> Message-ID: <4F3A9406.1070804@assembler.cz> > I also got that error while trying to program the latest factory BIOS file using > flashrom; flashrom was able to erase and program the new chip with no problems. > My original problem of creating a proper image for this board still remains. > Superiotool found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e. Any help would be > appreciated. Hi sorry for delay. Please run it with -d please. Thanks Rudolf > > On 1/31/2012 4:36 PM, Rudolf Marek wrote: >> Hi, >> >>> I was hoping to use the board above to experiment with Coreboot. The board has >>> the same northbridge as the Asus M2V-MX SE (VIA K8M890) and the same southbridge >>> as the Asus M2V (VIA 8237A). Both of those chipsets are fully supported. >>> Thinking that maybe I can at least get the board to boot ASAP, I built Coreboot >>> for the Asus M2V board to get the southbridge functionality. I also didn't use >>> the M2V-MX SE profile because it has the SPI chip, while the M2V-MX board has a >>> PLCC-32 chip. >> >> OK >> >> >>> The board booted fine, except I have no video, serial port or ability to write >>> to the BIOS chip. >> >> No video -> you need to include the extracted VGA bios from original BIOS. No >> serial port looks like wrong superio setup. No ability to write to the chip >> sounds interesting ? What do you mean by that. Flashrom cannot no-long >> overwrite the chip content? Maybe just some GPIO needs to be raised. Do you >> have more PLCC chips or other boards so you can hotswap them? >> >>> I know the board booted fine because I was able to SSH into >>> the box using a PCI network card. Considering that both the M2V and M2V-MX have >>> the same southbridge chip, I don't understand why there was not serial port or >>> write access to the BIOS chip. Can someone shed some light on that for me, >>> please. >> >> Yep see above. I would suggest to run the superiotool (see utils dir) and >> check what kind of superio is really there. Or even better provide >> ./superiotool -d dump best with original bios running if possible. >> >> Then you just need to change few lines and you should get serial back. I can >> even help with that but we need to know not only the chip there but also how >> the chip is configured. >> >> For the VGA you need to use bios_extract and extract the VGA bios from orig >> bios image and tell coreboot via menu to include that (you need just pci ID >> lspci -n will tell) >> >>> My other problem is I would like to create a build profile for the M2V-MX using >>> the code from the M2V for the southbridge and the code from the M2V-MX SE for >>> the northbridge. Is that a good idea or would I have to do some other things? >>> I learned C programming in 1993 and used it only until 1998; I am a little >>> rusty. >> >> Well C is simple you will got it back soon. >> >>> My ability to make sense of low-level chipset stuff is also very >>> narrow. >> >> If you ask good questions you will get answers. >> >>> However, I am a fast learner and I am desperate to get something >>> accomplished for a homebrew thin client project that I have spent way too much >>> time working on. >>> >>> My goal is to extend the life of boards that people send in for recycling by >>> turning them into more reliable diskless information terminals. >> >> A nice coreboot use! >> >> Thanks >> Rudolf > From greenfreedom10 at gmail.com Tue Feb 14 17:38:51 2012 From: greenfreedom10 at gmail.com (green) Date: Tue, 14 Feb 2012 10:38:51 -0600 Subject: [coreboot] recommend mini-itx motherboard Message-ID: <20120214163850.GP3711@swansys> I am looking for a fanless mini-pc for running Debian and would like, if possible, to run 100% free software on it. So I followed all the OK links in the v4 section of http://www.coreboot.org/Supported_Motherboards and read the support tables and only found 2: http://www.coreboot.org/Avalue_EAX_785E http://www.coreboot.org/GIGABYTE_GA-M57SLI-S4 that are actually close to being fully tested and supported. Now I am surprised about the claim on the main page that coreboot supports "over 230 different mainboards". That seems to be false...? I do not mean to insult, and acknowledge coreboot's accomplishments regardless. Anyway, is there any recommendation for a mini-itx for desktop use? I would like something fully supported by Linux, and perhaps which could run coreboot also; at least would like to put money on a supportive vendor. Thanks -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: Digital signature URL: From peter at stuge.se Tue Feb 14 18:16:53 2012 From: peter at stuge.se (Peter Stuge) Date: Tue, 14 Feb 2012 18:16:53 +0100 Subject: [coreboot] recommend mini-itx motherboard In-Reply-To: <20120214163850.GP3711@swansys> References: <20120214163850.GP3711@swansys> Message-ID: <20120214171653.23700.qmail@stuge.se> green wrote: > Now I am surprised about the claim on the main page that coreboot > supports "over 230 different mainboards". That seems to be false...? Things might work even if they have not been tested. And other things might need more work before they work. Of course it would be nice to have more 100% mainboards. Your contributions toward achieving this will be most welcome. > Anyway, is there any recommendation for a mini-itx for desktop use? Have a look at the ASRock E350M1. > I would like something fully supported by Linux, and perhaps which > could run coreboot also; at least would like to put money on a > supportive vendor. Then you'll want to buy AMD. Note that you will generally be stuck with an unfree VGA BIOS almost regardless of what you buy. Supergreen. //Peter -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 190 bytes Desc: not available URL: From hagigatali at gmail.com Tue Feb 14 18:48:48 2012 From: hagigatali at gmail.com (ali hagigat) Date: Tue, 14 Feb 2012 21:18:48 +0330 Subject: [coreboot] porting Coreboot to a new motherboard.... Message-ID: I have initialized Intel 82815 SDRAM controller but for a special type of RAM without reading SPD registers. I know that DRP register is : 0xCC. I added the code to Coreboot. I tested much and concluded that RAM has a problem in a way as you guys told me before. When i change the hardwaremain() , even adding some code which are bypassed, the results of the post code numbers become different! I do not know what to do! c_start.S is OK and it is executed and the program starts executing hardwaremain() but adding code to the hardwaremain() any where seems to disorder printed post code values. Is there any interrupt or timer set immediately after hardwaremain()? I checked coreboot_ram in build/. The assembly code of hardwaremian() seems OK. void sdram_enable(void) { asm("pushal"); asm("push %eax"); asm("push %ebx"); asm("push %ecx"); asm("push %edx"); asm("push %esi"); asm("push %edi"); asm("push %esp"); asm("push %ebp"); asm("pushfl"); asm("jmp firstlbl"); asm("mov %ax, %ax"); asm("nop"); /* Cache disable */ asm("firstlbl:"); asm("mov %cr0, %eax"); asm("and $0x9fffffff, %eax"); asm("or $0x40000000, %eax"); asm("mov %eax, %cr0"); /* Configure the RAM command. */ asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("movw $0x0CFC, %dx"); asm("in %dx, %eax"); asm("and $0x1fffffff, %eax"); asm("or $0x05000000, %eax"); asm("movw $0x0CFC, %dx"); asm("out %eax, %dx"); //general initialization //50-53************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //Res mask asm("and $0x0000F823, %eax"); //Bios => cas 2clk asm("or $0x2fcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //70,72-73************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000070, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("movb $0xc0, %al"); asm("out %al, %dx"); asm("mov $0x0cfe, %dx"); asm("inw %dx, %ax"); //Res mask asm("and $0x7704, %ax"); //Bios asm("or $0x0012, %ax"); asm("mov $0x0cfe, %dx"); asm("out %ax, %dx"); //92-93**************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000090, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfe, %dx"); asm("movw $0xff5c, %ax"); asm("out %ax, %dx"); //#94-95***************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000094, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfe, %dx"); asm("inw %dx, %ax"); //#Res mask asm("and $0xffc0, %ax"); //#Bios asm("or $0x001c, %ax"); asm("mov $0x0cfe, %dx"); asm("out %ax, %dx"); //#98-9B***************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000098, %eax"); asm("out %eax, %dx"); asm("movw $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x7F887F88, %eax"); //#Bios asm("or $0x80238023, %eax"); asm("movw $0x0cfc, %dx"); asm("out %eax, %dx"); //#9c-9f*************************** asm("mov $0x0cf8, %dx"); asm("mov $0x8000009c, %eax"); asm("out %eax, %dx"); asm(" movw $0x0CFC, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0xFFFF7FFF, %eax"); //#Bios asm("or $0x00008000, %eax"); asm("movw $0x0CFC, %dx"); asm("out %eax, %dx"); //#2c-2f*************************** asm("mov $0x0cf8, %dx"); asm("mov $0x8000002c, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("mov $0x80271043, %eax"); asm("out %eax, %dx"); //58-5b************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000058, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); asm("and $0xcccccf7f, %eax"); asm("or $0x33333000, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //5c-5f************************** asm("mov $0x0cf8, %dx"); asm("mov $0x8000005c, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); asm("and $0xcccccccc, %eax"); asm("or $0x33333333, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#;-------------------------------------------------- //#NOP /* 1. Apply NOP. */ //#display 1 asm("mov $1, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0x8fcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov (%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov (%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov (%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov (%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%% asm("mov $1, %di"); asm("delay11:"); asm("mov $200000, %ecx"); asm("delay1:"); asm("dec %ecx"); asm("jnz delay1"); asm("dec %di"); asm("jnz delay11"); //#;-------------------------------------------------- //#precharge /* 2. Precharge all. Wait tRP. */ //#display 2 asm("mov $2, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0xafcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay21:"); asm("mov $1000, %ecx"); asm("delay2:"); asm("dec %ecx"); asm("jnz delay2"); asm("dec %di"); asm("jnz delay21 "); //#;-------------------------------------------------- //#CBR cycle /* 3. Perform 8 refresh cycles. Wait tRC each time. */ //#display 3 asm("mov $3, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $8, %esi"); asm("refreshcycle:"); asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0xefcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay31:"); asm("mov $1000, %ecx"); asm("delay3:"); asm("dec %ecx"); asm("jnz delay3"); asm("dec %di"); asm("jnz delay31"); asm("dec %esi"); asm("jnz refreshcycle"); //#;-------------------------------------------------- //#mode register set /* 4. Mode register set. Wait two memory cycles. */ //#display 4 asm("mov $4, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0xcfcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%%%% //#1d0 =>150 => 03a //#650 => 650 => 0ca asm("mov $0x0000003a, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x0800003a, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x100000ca, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x180000ca, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay41:"); asm("mov $1000, %ecx"); asm("delay4:"); asm("dec %ecx"); asm("jnz delay4"); asm("dec %di"); asm("jnz delay41"); //#;-------------------------------------------------- //#normal operation /* 5. Normal operation (enables refresh at 15.6usec). */ //#display 5 asm("mov $5, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0x2fcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay51:"); asm("mov $1000, %ecx"); asm("delay5:"); asm("dec %ecx"); asm("jnz delay5"); asm("dec %di"); asm("jnz delay51"); //#;-------------------------------------------------- asm("mov $10, %al"); asm("out %al, $0x80"); //#;-------------------------------------------------- asm("mov $0xffff, %cx"); asm("delayea1:"); asm("dec %cx"); asm("jnz delayea1"); //asm("mov %cr0, %eax"); //asm("and $0x9fffffff, %eax"); //asm("mov %eax, %cr0"); asm("popfl"); asm("pop %ebp"); asm("pop %esp"); asm("pop %edi"); asm("pop %esi"); asm("pop %edx"); asm("pop %ecx"); asm("pop %ebx"); asm("pop %eax"); asm("popal"); } From marcj303 at gmail.com Tue Feb 14 19:28:15 2012 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 14 Feb 2012 11:28:15 -0700 Subject: [coreboot] New patch to review for coreboot: f299de3 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. In-Reply-To: <201202141323.20839.GNUtoo@no-log.org> References: <201202141323.20839.GNUtoo@no-log.org> Message-ID: Hi Denis, On Tue, Feb 14, 2012 at 5:23 AM, Denis 'GNUtoo' Carikli wrote: > hi, > I've tried this patch, here's what it produce as log: > From the linux kernel: > [ ? ?0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND > (20110112/psargs-359) > [ ? ?0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND > (20110112/psargs-359) > [ ? ?0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND > (20110112/psargs-359) This is a problem in the ACPI SSDT tables and not directly related to this change. Take a look at this change for a solution for your mainboard. http://review.coreboot.org/#change,574 > And: > [ ? ?0.308271] mtrr: your CPUs had inconsistent variable MTRR settings > [ ? ?0.308272] mtrr: probably your BIOS does not setup all CPUs. > [ ? ?0.308273] mtrr: corrected configuration. Yes, we let linux fix it up. i don't think that the AP cores are setup, only core0 is. This saves time and effort in coreboot. Let the OS do what it is going to do anyway. > And I think my CPU is covered by your patch: > CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB The message is a little deceiving. It takes the TOM2WB path, but you don't seem to have enough memory to cause the condition for TOM2WB to be required. It requires are least 4GB and I only see 2GB your output. I will adjust the message to be more accurate. > > Also, without pci=nocrs Xorg don't initialize. > This is probably IRQ routing in the APCI tables. See the above patch. Note that this is specific to each mainboard. You will need to implement your own version. > I've attached the full log(compressed with xz) I see this in the log: microcode: equivalent rev id = 0x1062, current patch id = 0x00000000 microcode: rev id (1081) does not match this patch. microcode: Not updated! Fix microcode_updates[] You should fix this up. See the table in src/cpu/amd/model_10xxx/update_microcode.c and update your mainboard Kconfig with the correct microcode file. > > Thanks a lot for working on this. You are welcome. Thanks for testing it. Marc > > Denis. -- http://se-eng.com From greenfreedom10 at gmail.com Tue Feb 14 21:31:37 2012 From: greenfreedom10 at gmail.com (green) Date: Tue, 14 Feb 2012 14:31:37 -0600 Subject: [coreboot] recommend mini-itx motherboard In-Reply-To: <20120214171653.23700.qmail@stuge.se> References: <20120214163850.GP3711@swansys> <20120214171653.23700.qmail@stuge.se> Message-ID: <20120214203137.GT3711@swansys> Peter Stuge wrote at 2012-02-14 11:16 -0600: > > Anyway, is there any recommendation for a mini-itx for desktop use? > > Have a look at the ASRock E350M1. > > I would like something fully supported by Linux, and perhaps which > > could run coreboot also; at least would like to put money on a > > supportive vendor. > > Then you'll want to buy AMD. Note that you will generally be stuck > with an unfree VGA BIOS almost regardless of what you buy. Thanks for the suggestions! -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: Digital signature URL: From gerrit at coreboot.org Tue Feb 14 21:52:41 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 21:52:41 +0100 Subject: [coreboot] Patch set updated for coreboot: ee068e8 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/627 -gerrit commit ee068e84d951b1d198007371d767b920e82ba149 Author: Marc Jones Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones --- src/cpu/amd/mtrr/amd_mtrr.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index c5e01b1..54a70e2 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -114,12 +114,13 @@ void amd_setup_mtrrs(void) msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later const int cpu_id = cpuid_eax(0x80000001); + printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); const int has_tom2wb = - (((cpu_id>>8 )&0xf) > 0xf) || // Family > 0F + (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables if(has_tom2wb) - printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB\n"); + printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n"); /* Enable the access to AMD RdDram and WrDram extension bits */ disable_cache(); From stefan.reinauer at coreboot.org Tue Feb 14 21:52:58 2012 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Tue, 14 Feb 2012 21:52:58 +0100 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: References: Message-ID: <20120214205258.GA26278@coreboot.org> * ali hagigat [120214 18:48]: > I have initialized Intel 82815 SDRAM controller but for a special type > of RAM without reading SPD registers. I know that DRP register is : > 0xCC. I added the code to Coreboot. > > I tested much and concluded that RAM has a problem in a way as you > guys told me before. When i change the hardwaremain() , even adding > some code which are bypassed, the results of the post code numbers > become different! > > I do not know what to do! c_start.S is OK and it is executed and the > program starts executing hardwaremain() but adding code to the > hardwaremain() any where seems to disorder printed post code values. > > Is there any interrupt or timer set immediately after hardwaremain()? > > I checked coreboot_ram in build/. The assembly code of hardwaremian() seems OK. > > > void sdram_enable(void) > { > asm("pushal"); > asm("push %eax"); > asm("push %ebx"); > asm("push %ecx"); > asm("push %edx"); > asm("push %esi"); > asm("push %edi"); > asm("push %esp"); > asm("push %ebp"); > asm("pushfl"); > asm("jmp firstlbl"); > asm("mov %ax, %ax"); > asm("nop"); [..] There's a number of things wrong with this approach: * if you don't use asm volatile instead of asm, gcc is free to reorder any of those statements as it sees fit. * you need to put all of the code in one asm volatile statement, or gcc will attempt to clean up after each of the statements or overwrite registers as it sees fit. But generally, I suggest you rewrite this in C, so it's a lot more readable... Stefan From rminnich at gmail.com Tue Feb 14 21:56:01 2012 From: rminnich at gmail.com (ron minnich) Date: Tue, 14 Feb 2012 12:56:01 -0800 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: References: <20120214205258.GA26278@coreboot.org> Message-ID: reading your note leads me to believe you are not familiar with how sdram startup works. It's a lot more than just setting one register. ron From gerrit at coreboot.org Tue Feb 14 22:22:48 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 14 Feb 2012 22:22:48 +0100 Subject: [coreboot] New patch to review for coreboot: b1443cb Torpedo mainboard changes to fix warnings. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/634 -gerrit commit b1443cb4c25f6efa6d0ffc388dbfb8f36c8f15f4 Author: Martin Roth Date: Tue Feb 14 10:50:11 2012 -0700 Torpedo mainboard changes to fix warnings. Fixes the warnings generated in the torpedo mainboard build. Most of these changes are similar to fixes already implemented in the persimmon mainboard. Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5 Signed-off-by: Martin L Roth Signed-off-by: Marc Jones --- src/mainboard/amd/torpedo/Oem.h | 5 ++- src/mainboard/amd/torpedo/acpi_tables.c | 12 +++++--- src/mainboard/amd/torpedo/fadt.c | 40 +++++++++++++++-------------- src/mainboard/amd/torpedo/gpio.c | 5 +-- src/mainboard/amd/torpedo/irq_tables.c | 2 +- src/mainboard/amd/torpedo/mainboard.c | 20 ++++++++------ src/mainboard/amd/torpedo/mptable.c | 20 ++++++++------ src/mainboard/amd/torpedo/platform_cfg.h | 3 ++ src/mainboard/amd/torpedo/romstage.c | 1 + 9 files changed, 60 insertions(+), 48 deletions(-) diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index a7109dc..037ce94 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,8 +16,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define BIOS_SIZE 0x04 //04 - 1MB +#ifndef BIOS_SIZE + #define BIOS_SIZE 0x04 //04 - 1MB +#endif #define LEGACY_FREE 0x00 #if CONFIG_ONBOARD_USB30 == 0 #define XHCI_SUPPORT 0x01 diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 4710b57..3ba789d 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -25,9 +25,9 @@ #include #include #include -#include - #include "agesawrapper.h" +#include +#include #define DUMP_ACPI_TABLES 0 extern u32 apicid_sb900; @@ -110,7 +110,9 @@ unsigned long write_acpi_tables(unsigned long start) unsigned long current; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; +#if 0 // Don't need HPET table. acpi_hpet_t *hpet; +#endif acpi_madt_t *madt; acpi_srat_t *srat; acpi_slit_t *slit; @@ -164,7 +166,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); if (srat != NULL) { - memcpy(current, srat, srat->header.length); + memcpy((void *)current, srat, srat->header.length); srat = (acpi_srat_t *) current; //acpi_create_srat(srat); current += srat->header.length; @@ -176,7 +178,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); if (slit != NULL) { - memcpy(current, slit, slit->header.length); + memcpy((void *)current, slit, slit->header.length); slit = (acpi_slit_t *) current; //acpi_create_slit(slit); current += slit->header.length; @@ -188,7 +190,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; current += ssdt->length; } diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 5701dab..a4cb1b9 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -28,7 +28,7 @@ #include #include #include -//#include "../../../southbridge/amd/sb900/sb900.h" +#include "SbPlatform.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ @@ -44,6 +44,7 @@ #define ACPI_CPU_CONTORL (pm_base + 0x10) /* 6 bytes */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { + u16 val = 0; acpi_header_t *header = &(fadt->header); pm_base &= 0xFFFF; @@ -71,29 +72,30 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8); + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ + val = ACPI_PM2_CNT_BLK; + WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val); - pm_iowrite(0x6E, ACPI_PM2_CNT_BLK & 0xFF); - pm_iowrite(0x6F, ACPI_PM2_CNT_BLK >> 8); + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn */ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 2633fb5..3e49cb1 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -23,9 +23,9 @@ */ #include "Filecode.h" -#include "Hudson-2.h" -#include "AmdSbLib.h" +#include "SbPlatform.h" #include "gpio.h" +#include "vendorcode/amd/cimx/sb900/AmdSbLib.h" #define FILECODE UNASSIGNED_FILE_FILECODE @@ -62,7 +62,6 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - void gpioEarlyInit (void); /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c index f61f1e8..595e09b 100644 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ b/src/mainboard/amd/torpedo/irq_tables.c @@ -23,7 +23,7 @@ #include #include #include -//#include +#include diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 288798f..2152153 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -31,6 +31,9 @@ #define ONE_MB 0x100000 //#define SMBUS_IO_BASE 0x6000 +void set_pcie_reset(void); +void set_pcie_dereset(void); + /** * TODO * SB CIMx callback @@ -54,7 +57,7 @@ uint64_t uma_memory_base, uma_memory_size; *************************************************/ static void torpedo_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard Torpedo Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -79,14 +82,13 @@ static void torpedo_enable(device_t dev) * >=1G 256M * <1G 64M */ - sys_mem = msr.lo; - sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size - if (sys_mem >= 2048 * ONE_MB) { - uma_memory_size = 512 * ONE_MB; - } else if (sys_mem >= 1024 * ONE_MB) { - uma_memory_size = 256 * ONE_MB; + sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ + } else if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ } else { - uma_memory_size = 64 * ONE_MB; + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", @@ -114,6 +116,6 @@ int add_mainboard_resources(struct lb_memory *mem) return 0; } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TORPEDO Mainboard") + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = torpedo_enable, }; diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 2e171a1..97db2b9 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include "SbPlatform.h" //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS @@ -113,15 +115,11 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ - device_t dev; u32 dword; u8 byte; - dword = 0; - dword = pm_ioread(0x34) & 0xF0; - dword |= (pm_ioread(0x35) & 0xFF) << 8; - dword |= (pm_ioread(0x36) & 0xFF) << 16; - dword |= (pm_ioread(0x37) & 0xFF) << 24; + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); + dword &= 0xFFFFFFF0; /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); @@ -166,8 +164,12 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, int_sign, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -214,9 +216,9 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15); - PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14); + PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12); + PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13); + PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 532d83f..d97d034 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -1237,4 +1237,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); */ u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg); +// definition for function in gpio.c +void gpioEarlyInit (void); + #endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 2e1d8fc..74365e6 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -37,6 +37,7 @@ #include "SbEarly.h" #include "SbPlatform.h" #include +#include "platform_cfg.h" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); From rminnich at gmail.com Tue Feb 14 21:54:56 2012 From: rminnich at gmail.com (ron minnich) Date: Tue, 14 Feb 2012 12:54:56 -0800 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: <20120214205258.GA26278@coreboot.org> References: <20120214205258.GA26278@coreboot.org> Message-ID: we worked a few years back to remove all __asm__ stuff from coreboot because it has so many tricky parts to making it work. If you're going to write assembly, put it in a .s. a .c file should have C. ron From marcj303 at gmail.com Tue Feb 14 21:47:14 2012 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 14 Feb 2012 13:47:14 -0700 Subject: [coreboot] "Fix multipleVGA cards resource conflict on Windows" broke my vga In-Reply-To: <201202141331.35029.GNUtoo@no-log.org> References: <201202141331.35029.GNUtoo@no-log.org> Message-ID: Hi Denis, On Tue, Feb 14, 2012 at 5:31 AM, Denis 'GNUtoo' Carikli wrote: > hi, > > I've an M4A785T-M which contains one onboard graphic card, > but it has 2 VGA extension roms. > one seem to be for HDMI, and the other for VGA. That sounds strange. I think that they are basicly the same output and should have a single rom. Are there two device IDs? If there are two devices, it seems that there is a problem selecting the default and allocating the decode correctly. > > reverting the commit makes VGA appear on my monitor. > > I've tried to add one option rom only, as usual, and nothing appeared on my > monitor with that comit. > Then I removed the VGA rom and with cbfstool I added both VGA rom. > Nothing appeared on my monitor either... > > Should I give some logs(it's quite long to get since I've to reflash with an > external programmer). > > Denis. > Logs would help, but you could some analysis about what setting is making the device work or not. Marc > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com From gerrit at coreboot.org Tue Feb 14 23:42:12 2012 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Tue, 14 Feb 2012 23:42:12 +0100 Subject: [coreboot] New patch to review for coreboot: ae96aef M4A785T-M: fix TOM2. This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/635 -gerrit commit ae96aefb5f26968c95a41f3be7e912448cd402fd Author: Denis 'GNUtoo' Carikli Date: Tue Feb 14 22:11:23 2012 +0100 M4A785T-M: fix TOM2. This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) With commit permit to boot without pci=nocrs on the M4A785T-M board. Before the fix dmesg contained the following: [ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) Now it only contains: [ 0.312102] TOM: 0000000080000000 aka 2048M Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/dsdt.asl | 107 +++++---------------------------- 1 files changed, 15 insertions(+), 92 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index d6a4355..fe2bfa5 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA,CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1421,21 +1421,6 @@ DefinitionBlock ( IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ } /* end LIBR */ Device(HPBR) { @@ -1546,88 +1531,26 @@ DefinitionBlock ( Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ From gerrit at coreboot.org Tue Feb 14 23:42:13 2012 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Tue, 14 Feb 2012 23:42:13 +0100 Subject: [coreboot] New patch to review for coreboot: 535a7d2 M4A785-M, M4A785T-M: fix SSDT tables References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/636 -gerrit commit 535a7d2f9f89f07f85750d33444eab4b5a7c802c Author: Denis 'GNUtoo' Carikli Date: Tue Feb 14 22:38:01 2012 +0100 M4A785-M,M4A785T-M: fix SSDT tables This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785-m/acpi_tables.c | 103 ++++++++++------------------- 1 files changed, 36 insertions(+), 67 deletions(-) diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index 1cb39ad..0d28314 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -49,12 +50,35 @@ static void dump_mem(u32 start, u32 end) extern const unsigned char AmlCode[]; extern const unsigned char AmlCode_ssdt[]; -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + + /* TODO: More HT and other tables need to go into this table generation. + * This should also be moved out to the silicon level if it can. + */ + + return (unsigned long) (acpigen_get_current()); +} + + unsigned long acpi_fill_mcfg(unsigned long current) { @@ -68,8 +92,8 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -100,11 +124,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -161,63 +180,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); + ssdt = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;ilength; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - /* DSDT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); From gerrit at coreboot.org Tue Feb 14 23:43:30 2012 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Tue, 14 Feb 2012 23:43:30 +0100 Subject: [coreboot] Patch set updated for coreboot: 3887beb M4A785T-M: fix TOM2. References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/635 -gerrit commit 3887beb6955df88880b1a6d359b2f2bbc69117e0 Author: Denis 'GNUtoo' Carikli Date: Tue Feb 14 22:11:23 2012 +0100 M4A785T-M: fix TOM2. This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) With commit permit to boot without pci=nocrs on the M4A785T-M board. Before the fix dmesg contained the following: [ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) Now it only contains: [ 0.312102] TOM: 0000000080000000 aka 2048M Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/dsdt.asl | 107 +++++---------------------------- 1 files changed, 15 insertions(+), 92 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index d6a4355..fe2bfa5 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA,CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1421,21 +1421,6 @@ DefinitionBlock ( IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device(HPTM) { - Name(_HID,EISAID("PNP0103")) - Name(CRS,ResourceTemplate() { - Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ - }) - Method(_STA, 0) { - Return(0x0F) /* sata is visible */ - } - Method(_CRS, 0) { - CreateDwordField(CRS, ^HPT._BAS, HPBA) - Store(HPBA, HPBA) - Return(CRS) - } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ } /* end LIBR */ Device(HPBR) { @@ -1546,88 +1531,26 @@ DefinitionBlock ( Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ From gerrit at coreboot.org Tue Feb 14 23:43:30 2012 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Tue, 14 Feb 2012 23:43:30 +0100 Subject: [coreboot] Patch set updated for coreboot: be7d415 M4A785-M, M4A785T-M: fix SSDT tables References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/636 -gerrit commit be7d4152144497b7318564ef92ae96c16b522305 Author: Denis 'GNUtoo' Carikli Date: Tue Feb 14 22:38:01 2012 +0100 M4A785-M,M4A785T-M: fix SSDT tables This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785-m/acpi_tables.c | 103 ++++++++++------------------- 1 files changed, 36 insertions(+), 67 deletions(-) diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index 1cb39ad..0d28314 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -49,12 +50,35 @@ static void dump_mem(u32 start, u32 end) extern const unsigned char AmlCode[]; extern const unsigned char AmlCode_ssdt[]; -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + + /* TODO: More HT and other tables need to go into this table generation. + * This should also be moved out to the silicon level if it can. + */ + + return (unsigned long) (acpigen_get_current()); +} + + unsigned long acpi_fill_mcfg(unsigned long current) { @@ -68,8 +92,8 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -100,11 +124,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -161,63 +180,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); + ssdt = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;ilength; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif - /* DSDT */ current = ( current + 0x07) & -0x08; printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); From gerrit at coreboot.org Wed Feb 15 03:32:35 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 03:32:35 +0100 Subject: [coreboot] Patch set updated for coreboot: fdb7c59 S3 code whitespaces changes. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/625 -gerrit commit fdb7c5974555626e2726e7888c8917c1c06cac4a Author: zbao Date: Tue Feb 14 19:00:17 2012 +0800 S3 code whitespaces changes. some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/persimmon/BiosCallOuts.c | 45 +++++++------ src/mainboard/amd/persimmon/get_bus_conf.c | 3 +- src/mainboard/amd/persimmon/mainboard.c | 1 + src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 10 ++-- src/vendorcode/amd/agesa/f14/gcccar.inc | 84 ++++++++++++------------ 5 files changed, 74 insertions(+), 69 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index df00c7c..06426c2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -155,8 +155,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. + to the end of the allocated nodes list. */ + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -205,7 +206,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; @@ -290,10 +291,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Clear the BufferSize and NextNodeOffset of the previous first node */ FreedNodePtr->BufferSize = 0; FreedNodePtr->NextNodeOffset = 0; + } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -301,21 +303,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; } else { /* Traverse list of freed nodes to find where the deallocated node - should be place + should be place */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); } /* If deallocated node is adjacent to the next node, - concatenate both nodes + concatenate both nodes */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -329,13 +331,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* If deallocated node is adjacent to the previous node, - concatenate both nodes + concatenate both nodes */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; AllocNodePtr->NextNodeOffset = 0; } else { @@ -405,17 +408,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) // 0xCF9 (Reset Port). // switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: break; - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - default: + default: break; } @@ -562,13 +565,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case 4: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 @@ -578,13 +581,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 6: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 @@ -594,13 +597,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 7: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index fef7d60..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -136,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 23eea86..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -121,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index ac613b1..a48d737 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -25,7 +25,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -33,10 +33,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,7 +47,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 981d976..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1,7 +1,7 @@ /* * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + /****************************************************************************** * AMD Generic Encapsulated Software Architecture * @@ -158,28 +158,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -194,12 +194,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -220,7 +220,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -252,9 +252,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - + mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B _RDMSR bt $APIC_BSC, %eax # Is this the BSC? @@ -263,7 +263,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -291,7 +291,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -324,7 +324,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -347,7 +347,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -371,7 +371,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -427,7 +427,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -589,7 +589,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -893,7 +893,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -973,7 +973,7 @@ fam15_enable_stack_hook_exit: btr $DIS_HW_PF, %eax # Turn on hardware prefetches #.endif # End workaround for erratum 498 0: - _WRMSR + _WRMSR #-------------------------------------------------------------------------- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- @@ -1135,7 +1135,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1240,7 +1240,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1308,7 +1308,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1344,20 +1344,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1428,7 +1428,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1584,7 +1584,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address From gerrit at coreboot.org Wed Feb 15 03:32:35 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 03:32:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 58b649d S3 code in the mainboard. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 58b649df7457e8e4eddeef5d9202042eb8c3744a Author: zbao Date: Tue Feb 14 18:57:25 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/persimmon/BiosCallOuts.c | 75 +++++---- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 173 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 18 ++- src/mainboard/amd/persimmon/mainboard.c | 15 ++- src/mainboard/amd/persimmon/romstage.c | 90 ++++++++-- 11 files changed, 327 insertions(+), 63 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index c8379ff..df00c7c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS CalloutStatus; UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + /* + * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func); + */ + CalloutStatus = AGESA_UNSUPPORTED; for (i = 0; i < CallOutCount; i++) { @@ -95,28 +99,30 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -224,32 +230,33 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); PrevNodeOffset = AllocNodeOffset; - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { if (AllocNodePtr->NextNodeOffset == 0) { return AGESA_BOUNDS_CHK; } @@ -348,8 +355,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e01e101..01ea3a8 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..53ca04c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,12 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include +#include #define FILECODE UNASSIGNED_FILE_FILECODE @@ -243,6 +245,35 @@ agesawrapper_amdinitearly ( return (UINT32)status; } + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrReg; + UINT32 sys_mem, uma_base, uma_size; + + /* TOP_MEM: the top of DRAM below 4G */ + LibAmdMsrRead(TOP_MEM, &MsrReg, StdHeader); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = (UINT32)(MsrReg & 0xFFFFFFFFUL) + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((MsrReg & 0x0000000F00000000) || (sys_mem >= 0x80000000)) { + uma_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_base = (UINT32)(MsrReg & 0xFFFFFFFFUL) - uma_size ; /* TOP_MEM1 */ + return uma_base - BIOS_HEAP_SIZE; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +303,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +527,146 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..0b79e5f 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE //FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE //FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..fef7d60 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..23eea86 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include #include #include -#include #include -//#include +#include +#include #include "chip.h" +#include "BiosCallOuts.h" +#include +#include void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..52756ff 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(resume_backup_memory + HIGH_MEMORY_SAVE); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcopy_fast(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50); From gerrit at coreboot.org Wed Feb 15 03:32:36 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 03:32:36 +0100 Subject: [coreboot] Patch set updated for coreboot: 74abd8b S3 code in vendorcode folder. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622 -gerrit commit 74abd8b63dcd2c4f3a6004f5be702b72788863ef Author: zbao Date: Tue Feb 14 18:37:00 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 10 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 158 ++--------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 204 +++++++++++++++++++++ src/vendorcode/amd/agesa/f14/gcccar.inc | 192 +++++++++++--------- 5 files changed, 329 insertions(+), 236 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 774d401..b08ceeb 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 58438b9..5ce3ee3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=a" (value) + : + : "memory"); return value; } @@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D "mov %%eax, %%cr0" : : "a" (Data) + : "memory" ); } @@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void) __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); } - static __inline__ __attribute__((always_inline)) void __lidt(void *Source) { __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index c4c3892..ac613b1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -66,196 +66,64 @@ *---------------------------------------------------------------------------------------- */ -// typedef unsigned int uintptr_t; +// typedef unsigned int uintptr_t; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - + +/* VOID ExecuteFinalHltInstruction ( IN UINT32 SharedCore, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ); - +*/ VOID SetIdtr ( IN IDT_BASE_LIMIT *IdtInfo, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID GetCsSelector ( IN UINT16 *Selector, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID NmiHandler ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteHltInstruction ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteWbinvdInstruction ( IN AMD_CONFIG_PARAMS *StdHeader ); - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahalt.s VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..509e962 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f14/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: +/* AMD- TODO - check these stack access are correct */ + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ + +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* restore variable MTTR6 and MTTR7 to default states */ + movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $10, %ecx /* .while (cl < 010h) */ + jge 6f + wrmsr + inc %ecx + 6: /* .endw */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 63f3ea9..981d976 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -37,99 +37,113 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized From gerrit at coreboot.org Wed Feb 15 03:32:36 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 03:32:36 +0100 Subject: [coreboot] Patch set updated for coreboot: ff18431 S3 code in coreboot public folder. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit ff18431547606654d8530d4c9bd0b0514a1125b8 Author: zbao Date: Tue Feb 14 18:51:46 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to hig memory. 2. Restore the MTRR before cb jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/arch/x86/Makefile.inc | 10 + src/arch/x86/boot/acpi.c | 2 + src/arch/x86/boot/tables.c | 3 +- src/boot/hardwaremain.c | 5 +- src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/Kconfig | 8 + src/cpu/amd/agesa/family14/model_14_init.c | 165 ++++++----- src/cpu/amd/agesa/s3_resume.c | 348 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 42 +++ src/cpu/amd/car/post_cache_as_ram.c | 18 +- src/devices/pci_device.c | 10 + src/include/cbmem.h | 11 +- src/include/string.h | 1 + src/lib/cbmem.c | 2 + src/lib/memcpy.c | 15 + src/northbridge/amd/agesa/family14/northbridge.c | 104 +++++-- 17 files changed, 622 insertions(+), 131 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..31de1e3 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -107,6 +107,16 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi endif +ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) +# This S3 storage area in flash is a bit tricky. The location is set and used +# by the southbridge ROM access functions. This should probably be +# connected with the #define somehow... + @printf " S3 NVRAM 0xffff0000 (S3 storage area)\n" + rm -f $(obj)/s3.rom + dd if=/dev/zero of=$(obj)/fill.rom bs=20k count=1 2> /dev/null + $(CBFSTOOL) $@.tmp add $(obj)/fill.rom "s3nv" raw 0xffff0000 + rm -f $(obj)/s3.rom +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..077f47c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -474,6 +474,8 @@ void suspend_resume(void) wake_vec = acpi_find_wakeup_vector(); if (wake_vec) acpi_jump_to_wakeup(wake_vec); + else + die("Error: No Wake Vector Found!\n Reset for normal boot path."); } /* This is to be filled by SB code - startup value what was found. */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 29d2ec0..ba5cdf3 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -230,13 +230,12 @@ struct lb_memory *write_tables(void) } post_code(0x9e); - #if CONFIG_HAVE_ACPI_RESUME /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..56a5f0c 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -35,7 +35,7 @@ it with the version available from LANL. #include #include #include -#if CONFIG_HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME == 1 #include #endif #if CONFIG_WRITE_HIGH_TABLES @@ -94,7 +94,8 @@ void hardwaremain(int boot_complete) cbmem_initialize(); #endif #if CONFIG_HAVE_ACPI_RESUME == 1 - suspend_resume(); + if (acpi_slp_type == 3) + suspend_resume(); post_code(0x8a); #endif diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..cfe6a43 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -20,5 +20,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 702270c..d1140f3 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,3 +67,11 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 +config RESUME_SCRATCH_MEMORY_SIZE +# This is derived from AGESA gccar.inc +# BSP_STACK_SIZE + CORE0_STACK_SIZE * 8 + CORE1_STACK_SIZE * 64 + HEAP_SIZE +# For 2 core Fam14: BSP_STACK_SIZE + CORE1_STACK_SIZE + HEAP_SIZE +# 0x10000 + 0x1000 + 20000 + hex + default 0x31000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 6f697cf..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,109 +32,126 @@ #include #include #include +#include +#include #define MCI_STATUS 0x401 msr_t rdmsr_amd(u32 index) { - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; } void wrmsr_amd(u32 index, msr_t msr) { - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); } static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { - .init = model_14_init, + .init = model_14_init, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ - { 0, 0 }, + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { 0, 0 }, }; static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, + .ops = &cpu_dev_ops, + .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..d67bf80 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,348 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include +#include +#include +#include +#include +#if CONFIG_WRITE_HIGH_TABLES +#include +#endif +#include +#include +#include +#include +#include +#include +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +void restore_mtrr(void) +{ + u32 msr; + volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS; + msr_t msr_data; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYS_CFG, msr_data); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void *resume_backup_memory) +{ +#if 0 + u32 *sp, index; + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6], sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif + + memcopy_fast(resume_backup_memory, (void *)BSP_STACK_BASE_ADDR, + (HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (resume_backup_memory - BSP_STACK_BASE_ADDR) + :); + +#if 0 + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6],sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + u32 spi_address; + msr_t msr_data; + device_t dev; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 i; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Fixed MTRRs */ + msr_data = rdmsr(0x250); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x258); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x259); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + msr_data = rdmsr(i); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + msr_data = rdmsr(i); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* SYS_CFG */ + msr_data = rdmsr(0xC0010010); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM */ + msr_data = rdmsr(0xC001001A); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM2 */ + msr_data = rdmsr(0xC001001D); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + memcopy_fast((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize); + } +} + +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; +#ifndef __PRE_RAM__ + u32 spi_address, data; + u32 nvram_pos; + device_t dev; +#endif + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + +#ifndef __PRE_RAM__ + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + readSPIID((u8 *) spi_address); + writeSPIStatus((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sectorEraseSPI((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sectorEraseSPI((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } +#endif + + return AGESA_SUCCESS; +} + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..a62f90e --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void *resume_backup_memory); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 270c542..74423f2 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -13,22 +13,6 @@ static inline void print_debug_pcar(const char *strval, uint32_t val) printk(BIOS_DEBUG, "%s%08x\n", strval, val); } -/* from linux kernel 2.6.32 asm/string_32.h */ - -static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes) -{ - int d0, d1, d2; - asm volatile("cld ; rep ; movsl\n\t" - "movl %4,%%ecx\n\t" - "andl $3,%%ecx\n\t" - "jz 1f\n\t" - "rep ; movsb\n\t" - "1:" - : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) - : "memory", "cc"); -} - #if CONFIG_HAVE_ACPI_RESUME == 1 static inline void *backup_resume(void) { @@ -58,7 +42,7 @@ static inline void *backup_resume(void) { if (resume_backup_memory) { print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory); /* copy only backup only memory used for CAR */ - memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, + memcopy_fast(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, (void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), CONFIG_DCACHE_RAM_SIZE); //inline } diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 2ccb38a..59ccff6 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -650,6 +650,10 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif + /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { @@ -664,6 +668,12 @@ void pci_dev_init(struct device *dev) ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return; +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* Don't re-run roms on s3 resume. */ + if (acpi_slp_type == 3) + return; +#endif + rom = pci_rom_probe(dev); if (rom == NULL) return; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..b7207b9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -25,11 +25,16 @@ extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) +#ifdef CONFIG_RESUME_SCRATCH_MEMORY_SIZE +#define HIGH_SCRATCH_MEMORY_SIZE CONFIG_RESUME_SCRATCH_MEMORY_SIZE #else -#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE +#define HIGH_SCRATCH_MEMORY_SIZE 0 #endif +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) +#else /* CONFIG_HAVE_ACPI_RESUME */ +#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/include/string.h b/src/include/string.h index 2168947..234f848 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -8,6 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); +void inline __attribute__((always_inline)) memcopy_fast(void *dest, const void *src, unsigned long bytes); #if !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..18f05b5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -176,6 +176,8 @@ void *cbmem_find(u32 id) return NULL; for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { + printk(BIOS_SPEW, "CBMEM TOC ID %d is: %x base: %x%x\n", i, + (u32) cbmem_toc[i].id, (u32) (cbmem_toc[i].base >> 32), (u32) cbmem_toc[i].base); if (cbmem_toc[i].id == id) return (void *)(unsigned long)cbmem_toc[i].base; } diff --git a/src/lib/memcpy.c b/src/lib/memcpy.c index 1053a53..217f73b 100644 --- a/src/lib/memcpy.c +++ b/src/lib/memcpy.c @@ -10,3 +10,18 @@ void *memcpy(void *vdest, const void *vsrc, size_t bytes) return vdest; } + +/* from linux kernel 2.6.32 asm/string_32.h */ +void inline __attribute__((always_inline)) memcopy_fast(void *dest, const void *src, unsigned long bytes) +{ + int d0, d1, d2; + asm volatile("cld ; rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" + "jz 1f\n\t" + "rep ; movsb\n\t" + "1:" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) + : "memory", "cc"); +} diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b2ca256..759f0c2 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -332,11 +333,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; @@ -691,12 +687,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)high_tables_size, high_tables_base); } #endif @@ -721,17 +717,18 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n",uma_memory_base); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx, ",uma_memory_base); #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024)- HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - } + high_tables_size = HIGH_MEMORY_SIZE; + } #endif } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n",mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); +printk(BIOS_DEBUG, " adsr - high_tables_base=%x%x\n", (u32) (high_tables_base >> 32), (u32) high_tables_base); #if CONFIG_GFXUMA == 1 printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); @@ -746,22 +743,46 @@ printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } +extern u8 acpi_slp_type; static void domain_enable_resources(device_t dev) { u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -795,24 +816,41 @@ static void cpu_bus_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) +static u32 cpu_bus_scan(device_t dev, u32 max) { - struct device_path cpu_path; device_t cpu; - int apic_id; - - initialize_cpus(dev->link_list); + struct device_path cpu_path; + int apic_id, cores_found; + + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); + + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } + } + return max; +} - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - } +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } @@ -858,7 +896,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; From gerrit at coreboot.org Wed Feb 15 03:32:37 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 03:32:37 +0100 Subject: [coreboot] Patch set updated for coreboot: d07ab6a Add sb800 spi support. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/620 -gerrit commit d07ab6aa159b848a1b420d4601947efd9450c812 Author: zbao Date: Tue Feb 14 18:22:04 2012 +0800 Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 + src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 4 + src/southbridge/amd/cimx/sb800/spi.c | 210 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/spi.h | 42 ++++++ 4 files changed, 258 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30d2133..2b55fee 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -27,6 +27,8 @@ romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c + driver-y += smbus.c driver-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index db5343d..25aba95 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -158,4 +158,8 @@ typedef union _PCI_ADDR { #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#if CONFIG_HAVE_ACPI_RESUME == 1 +#include "spi.h" +#endif + #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c new file mode 100644 index 0000000..ed8f51d --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include "SBPLATFORM.h" + + +void executeCommand(volatile u8 * spi_address) +{ + *(spi_address + 2) |= 1; +} + +void wait4CommandComplete(volatile u8 * spi_address) +{ + while (*(spi_address + 2) & 1) + printk(BIOS_DEBUG, "wait4CommandComplete\n"); +} + +void resetInternalFIFOPointer(volatile u8 * spi_address) +{ + u8 val; + + do { + *(spi_address + 2) |= 0x10; + val = *(spi_address + 0xd); + } while (val & 0x7); +} + +u8 readSPIStatus(volatile u8 * spi_address) +{ + u8 val; + *spi_address = 0x05; + *(spi_address + 1) = 0x11; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = 0x0; /* dummy */ + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + resetInternalFIFOPointer(spi_address); + val = *(spi_address + 0xC); + val = *(spi_address + 0xC); + return val; +} + +void wait4FlashPartReady(volatile u8 * spi_address) +{ + while (readSPIStatus(spi_address) & 1) ; +} + +void writeSPIStatus(volatile u8 * spi_address, u8 status) +{ + *spi_address = 0x50; /* EWSR */ + *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ + executeCommand(spi_address); + wait4CommandComplete(spi_address); + + *spi_address = 0x01; /* WRSR */ + *(spi_address + 1) = 0x01; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = status; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); + + readSPIStatus(spi_address); +} + +void readSPIID(volatile u8 * spi_address) +{ + u8 mid = 0, did = 0; + *spi_address = 0x90; + *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + resetInternalFIFOPointer(spi_address); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + + mid = *(spi_address + 0xC); + did = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); +} + +void SPIWriteEnable(volatile u8 * spi_address) +{ + *spi_address = 0x06; /* Write Enable */ + *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ + executeCommand(spi_address); + wait4CommandComplete(spi_address); + //wait4FlashPartReady(spi_address); +} + +void sectorEraseSPI(volatile u8 * spi_address, u32 address) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x20; + *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ + + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void chipEraseSPI(volatile u8 * spi_address) +{ + SPIWriteEnable(spi_address); + *spi_address = 0xC7; + *(spi_address + 1) = 0x00; + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void byteProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void dwordnoneAAIProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + u8 i; + /* + * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); + */ + for (i = 0; i < 4; i++) { + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + data >>= 8; + address++; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); + } +} + +void dwordProgram(volatile u8 * spi_address, u32 address, u32 data) +{ + SPIWriteEnable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 7; + resetInternalFIFOPointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + *(spi_address + 0xC) = (data >> 8) & 0xFF; + *(spi_address + 0xC) = (data >> 16) & 0xFF; + *(spi_address + 0xC) = (data >> 24) & 0xFF; + resetInternalFIFOPointer(spi_address); + executeCommand(spi_address); + wait4CommandComplete(spi_address); + wait4FlashPartReady(spi_address); +} + +void directByteProgram(volatile u8 * spi_address, volatile u32 * address, u32 data) +{ + SPIWriteEnable(spi_address); + *address = data; + wait4FlashPartReady(spi_address); +} diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h new file mode 100644 index 0000000..1e781f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.h @@ -0,0 +1,42 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _SB800_CIMX_SPI_H_ +#define _SB800_CIMX_SPI_H_ + +void executeCommand(volatile u8 * spi_address); +void wait4CommandComplete(volatile u8 * spi_address); +void resetInternalFIFOPointer(volatile u8 * spi_address); +u8 readSPIStatus(volatile u8 * spi_address); +void wait4FlashPartReady(volatile u8 * spi_address); +void writeSPIStatus(volatile u8 * spi_address, u8 status); +void readSPIID(volatile u8 * spi_address); +void SPIWriteEnable(volatile u8 * spi_address); +void sectorEraseSPI(volatile u8 * spi_address, u32 address); +void chipEraseSPI(volatile u8 * spi_address); +void byteProgram(volatile u8 * spi_address, u32 address, u32 data); +void dwordnoneAAIProgram(volatile u8 * spi_address, u32 address, u32 data); +void dwordProgram(volatile u8 * spi_address, u32 address, u32 data); +void directByteProgram(volatile u8 * spi_address, volatile u32 * address, u32 data); + +#endif From gerrit at coreboot.org Wed Feb 15 03:32:38 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 03:32:38 +0100 Subject: [coreboot] Patch set updated for coreboot: 605fcbb Add Southbridge support for S3. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621 -gerrit commit 605fcbb1b4d32249ceac27dcee2648bf3af1b31c Author: zbao Date: Tue Feb 14 18:28:51 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/southbridge/amd/cimx/sb800/cfg.c | 33 +++++++++++++++++++++++++---- src/southbridge/amd/cimx/sb800/early.c | 21 +++++++++++++++++++ src/southbridge/amd/cimx/sb800/late.c | 19 +++++++++++++++++ src/southbridge/amd/cimx/sb800/lpc.c | 18 ++++++++++++++++ src/southbridge/amd/cimx/sb800/lpc.h | 3 ++ src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 +++ 6 files changed, 93 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a9e35bc..32c28cc 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,10 +17,31 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include #include "SBPLATFORM.h" #include "cfg.h" +#include +#include + +#define SB800_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0E) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + return (int)tmp; +} +#endif /** * @brief South Bridge CIMx configuration @@ -30,10 +51,13 @@ */ void sb800_cimx_config(AMDSBCFG *sb_config) { - if (!sb_config) { + if (!sb_config) return; - } - //memset(sb_config, 0, sizeof(AMDSBCFG)); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_get_sleep_type() == 3) + sb_config->S3Resume = 1; +#endif /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; @@ -132,4 +156,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config) } #endif //!__PRE_RAM__ } - diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52..5e9d2b4 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include #include /* inl, outl */ #include /* device_t */ +#include #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,22 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +struct cbmem_entry *get_cbmem_toc(void) +{ + uint32_t xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, /* BIOSRAM_INDEX */0xCD4); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(/* BIOSRAM_DATA */0xCD5) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8c7abdb..c69782b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,7 @@ #include #include /* smbus_bus_operations */ #include /* printk */ +#include #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ @@ -351,6 +352,17 @@ void sb_Late_Post(void) AmdSbDispatcher(sb_config); } +void sb_Before_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} /** * @brief SB Cimx entry point sbBeforePciInit wrapper @@ -468,7 +480,14 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) + sb_Before_Pci_Init(); + else + sb_Before_Pci_Restore_Init(); +#else sb_Before_Pci_Init(); +#endif break; default: diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..08f1ee5 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,25 @@ #include #include #include "lpc.h" +#include +#include +#include +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xf8, i; /* temp */ + printk(BIOS_DEBUG, "dword=%x\n", dword); + for (i = 0; i<4; i++) { + printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8..f6ffd53 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -21,6 +21,9 @@ #define _SB800_LPC_H_ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 42a7ba9..5e510de 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); void sb_Mid_Post_Init(void); void sb_Late_Post(void); +void sb_Before_Pci_Restore_Init(void); +void sb_After_Pci_Restore_Init(void); + +int acpi_is_wakeup_early(void); /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, From gerrit at coreboot.org Wed Feb 15 05:23:33 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 05:23:33 +0100 Subject: [coreboot] Patch set updated for coreboot: aee5ce6 S3 code whitespaces changes. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/625 -gerrit commit aee5ce655a9638135943e8a12e01727430126636 Author: zbao Date: Wed Feb 15 13:21:37 2012 +0800 S3 code whitespaces changes. some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/persimmon/BiosCallOuts.c | 45 +++++++------ src/mainboard/amd/persimmon/get_bus_conf.c | 3 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 10 ++-- src/vendorcode/amd/agesa/f14/gcccar.inc | 84 ++++++++++++------------ 4 files changed, 73 insertions(+), 69 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index df00c7c..06426c2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -155,8 +155,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. + to the end of the allocated nodes list. */ + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -205,7 +206,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; @@ -290,10 +291,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Clear the BufferSize and NextNodeOffset of the previous first node */ FreedNodePtr->BufferSize = 0; FreedNodePtr->NextNodeOffset = 0; + } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -301,21 +303,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; } else { /* Traverse list of freed nodes to find where the deallocated node - should be place + should be place */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); } /* If deallocated node is adjacent to the next node, - concatenate both nodes + concatenate both nodes */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -329,13 +331,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* If deallocated node is adjacent to the previous node, - concatenate both nodes + concatenate both nodes */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; AllocNodePtr->NextNodeOffset = 0; } else { @@ -405,17 +408,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) // 0xCF9 (Reset Port). // switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: break; - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - default: + default: break; } @@ -562,13 +565,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case 4: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 @@ -578,13 +581,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 6: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 @@ -594,13 +597,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 7: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index fef7d60..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -136,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index ac613b1..a48d737 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -25,7 +25,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -33,10 +33,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,7 +47,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 981d976..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1,7 +1,7 @@ /* * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + /****************************************************************************** * AMD Generic Encapsulated Software Architecture * @@ -158,28 +158,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -194,12 +194,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -220,7 +220,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -252,9 +252,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - + mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B _RDMSR bt $APIC_BSC, %eax # Is this the BSC? @@ -263,7 +263,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -291,7 +291,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -324,7 +324,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -347,7 +347,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -371,7 +371,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -427,7 +427,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -589,7 +589,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -893,7 +893,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -973,7 +973,7 @@ fam15_enable_stack_hook_exit: btr $DIS_HW_PF, %eax # Turn on hardware prefetches #.endif # End workaround for erratum 498 0: - _WRMSR + _WRMSR #-------------------------------------------------------------------------- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- @@ -1135,7 +1135,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1240,7 +1240,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1308,7 +1308,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1344,20 +1344,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1428,7 +1428,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1584,7 +1584,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address From gerrit at coreboot.org Wed Feb 15 05:23:33 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 05:23:33 +0100 Subject: [coreboot] Patch set updated for coreboot: 8856afb S3 code in the mainboard. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 8856afbe841195bff70cab07b49e0a4534e9f71f Author: zbao Date: Wed Feb 15 13:18:20 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/mainboard/amd/persimmon/BiosCallOuts.c | 75 +++++---- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 173 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 18 ++- src/mainboard/amd/persimmon/mainboard.c | 16 ++- src/mainboard/amd/persimmon/romstage.c | 90 ++++++++-- 11 files changed, 328 insertions(+), 63 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index c8379ff..df00c7c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS CalloutStatus; UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + /* + * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func); + */ + CalloutStatus = AGESA_UNSUPPORTED; for (i = 0; i < CallOutCount; i++) { @@ -95,28 +99,30 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -224,32 +230,33 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); PrevNodeOffset = AllocNodeOffset; - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { if (AllocNodePtr->NextNodeOffset == 0) { return AGESA_BOUNDS_CHK; } @@ -348,8 +355,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e01e101..01ea3a8 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..53ca04c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,12 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include +#include #define FILECODE UNASSIGNED_FILE_FILECODE @@ -243,6 +245,35 @@ agesawrapper_amdinitearly ( return (UINT32)status; } + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrReg; + UINT32 sys_mem, uma_base, uma_size; + + /* TOP_MEM: the top of DRAM below 4G */ + LibAmdMsrRead(TOP_MEM, &MsrReg, StdHeader); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = (UINT32)(MsrReg & 0xFFFFFFFFUL) + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((MsrReg & 0x0000000F00000000) || (sys_mem >= 0x80000000)) { + uma_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_base = (UINT32)(MsrReg & 0xFFFFFFFFUL) - uma_size ; /* TOP_MEM1 */ + return uma_base - BIOS_HEAP_SIZE; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +303,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +527,146 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..0b79e5f 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE //FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE //FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..fef7d60 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include #include #include -#include #include -//#include +#include +#include #include "chip.h" +#include "BiosCallOuts.h" +#include +#include void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..52756ff 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(resume_backup_memory + HIGH_MEMORY_SAVE); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcopy_fast(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50); From gerrit at coreboot.org Wed Feb 15 05:23:33 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Wed, 15 Feb 2012 05:23:33 +0100 Subject: [coreboot] Patch set updated for coreboot: cb3a033 S3 code in coreboot public folder. References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit cb3a0331a22bc19e8c95924db25c2242b7980a32 Author: zbao Date: Wed Feb 15 13:12:58 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to hig memory. 2. Restore the MTRR before cb jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/arch/x86/Makefile.inc | 10 + src/arch/x86/boot/acpi.c | 2 + src/arch/x86/boot/tables.c | 3 +- src/boot/hardwaremain.c | 5 +- src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/Kconfig | 8 + src/cpu/amd/agesa/family14/model_14_init.c | 165 ++++++----- src/cpu/amd/agesa/s3_resume.c | 348 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 42 +++ src/devices/pci_device.c | 10 + src/include/cbmem.h | 11 +- src/include/string.h | 1 + src/lib/cbmem.c | 2 + src/lib/memcpy.c | 15 + src/northbridge/amd/agesa/family14/northbridge.c | 104 +++++-- 16 files changed, 621 insertions(+), 114 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..31de1e3 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -107,6 +107,16 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi endif +ifeq ($(CONFIG_HAVE_ACPI_RESUME),y) +# This S3 storage area in flash is a bit tricky. The location is set and used +# by the southbridge ROM access functions. This should probably be +# connected with the #define somehow... + @printf " S3 NVRAM 0xffff0000 (S3 storage area)\n" + rm -f $(obj)/s3.rom + dd if=/dev/zero of=$(obj)/fill.rom bs=20k count=1 2> /dev/null + $(CBFSTOOL) $@.tmp add $(obj)/fill.rom "s3nv" raw 0xffff0000 + rm -f $(obj)/s3.rom +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..077f47c 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -474,6 +474,8 @@ void suspend_resume(void) wake_vec = acpi_find_wakeup_vector(); if (wake_vec) acpi_jump_to_wakeup(wake_vec); + else + die("Error: No Wake Vector Found!\n Reset for normal boot path."); } /* This is to be filled by SB code - startup value what was found. */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 29d2ec0..ba5cdf3 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -230,13 +230,12 @@ struct lb_memory *write_tables(void) } post_code(0x9e); - #if CONFIG_HAVE_ACPI_RESUME /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..56a5f0c 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -35,7 +35,7 @@ it with the version available from LANL. #include #include #include -#if CONFIG_HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME == 1 #include #endif #if CONFIG_WRITE_HIGH_TABLES @@ -94,7 +94,8 @@ void hardwaremain(int boot_complete) cbmem_initialize(); #endif #if CONFIG_HAVE_ACPI_RESUME == 1 - suspend_resume(); + if (acpi_slp_type == 3) + suspend_resume(); post_code(0x8a); #endif diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..cfe6a43 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -20,5 +20,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 702270c..d1140f3 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,3 +67,11 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 +config RESUME_SCRATCH_MEMORY_SIZE +# This is derived from AGESA gccar.inc +# BSP_STACK_SIZE + CORE0_STACK_SIZE * 8 + CORE1_STACK_SIZE * 64 + HEAP_SIZE +# For 2 core Fam14: BSP_STACK_SIZE + CORE1_STACK_SIZE + HEAP_SIZE +# 0x10000 + 0x1000 + 20000 + hex + default 0x31000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 6f697cf..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,109 +32,126 @@ #include #include #include +#include +#include #define MCI_STATUS 0x401 msr_t rdmsr_amd(u32 index) { - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; } void wrmsr_amd(u32 index, msr_t msr) { - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); } static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { - .init = model_14_init, + .init = model_14_init, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ - { 0, 0 }, + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { 0, 0 }, }; static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, + .ops = &cpu_dev_ops, + .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..d67bf80 --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,348 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include +#include +#include +#include +#include +#if CONFIG_WRITE_HIGH_TABLES +#include +#endif +#include +#include +#include +#include +#include +#include +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +void restore_mtrr(void) +{ + u32 msr; + volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS; + msr_t msr_data; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYS_CFG, msr_data); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void *resume_backup_memory) +{ +#if 0 + u32 *sp, index; + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6], sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif + + memcopy_fast(resume_backup_memory, (void *)BSP_STACK_BASE_ADDR, + (HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (resume_backup_memory - BSP_STACK_BASE_ADDR) + :); + +#if 0 + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6],sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + u32 spi_address; + msr_t msr_data; + device_t dev; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 i; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Fixed MTRRs */ + msr_data = rdmsr(0x250); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x258); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x259); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + msr_data = rdmsr(i); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + msr_data = rdmsr(i); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* SYS_CFG */ + msr_data = rdmsr(0xC0010010); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM */ + msr_data = rdmsr(0xC001001A); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM2 */ + msr_data = rdmsr(0xC001001D); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + memcopy_fast((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize); + } +} + +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; +#ifndef __PRE_RAM__ + u32 spi_address, data; + u32 nvram_pos; + device_t dev; +#endif + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + +#ifndef __PRE_RAM__ + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + readSPIID((u8 *) spi_address); + writeSPIStatus((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sectorEraseSPI((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sectorEraseSPI((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sectorEraseSPI((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dwordnoneAAIProgram((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } +#endif + + return AGESA_SUCCESS; +} + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..a62f90e --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void *resume_backup_memory); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 2ccb38a..59ccff6 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -650,6 +650,10 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif + /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { @@ -664,6 +668,12 @@ void pci_dev_init(struct device *dev) ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) return; +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* Don't re-run roms on s3 resume. */ + if (acpi_slp_type == 3) + return; +#endif + rom = pci_rom_probe(dev); if (rom == NULL) return; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7c5ec07..b7207b9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -25,11 +25,16 @@ extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) +#ifdef CONFIG_RESUME_SCRATCH_MEMORY_SIZE +#define HIGH_SCRATCH_MEMORY_SIZE CONFIG_RESUME_SCRATCH_MEMORY_SIZE #else -#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE +#define HIGH_SCRATCH_MEMORY_SIZE 0 #endif +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) +#else /* CONFIG_HAVE_ACPI_RESUME */ +#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/include/string.h b/src/include/string.h index 2168947..234f848 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -8,6 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); int memcmp(const void *s1, const void *s2, size_t n); +void inline __attribute__((always_inline)) memcopy_fast(void *dest, const void *src, unsigned long bytes); #if !defined(__PRE_RAM__) int sprintf(char * buf, const char *fmt, ...); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 202f521..18f05b5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -176,6 +176,8 @@ void *cbmem_find(u32 id) return NULL; for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { + printk(BIOS_SPEW, "CBMEM TOC ID %d is: %x base: %x%x\n", i, + (u32) cbmem_toc[i].id, (u32) (cbmem_toc[i].base >> 32), (u32) cbmem_toc[i].base); if (cbmem_toc[i].id == id) return (void *)(unsigned long)cbmem_toc[i].base; } diff --git a/src/lib/memcpy.c b/src/lib/memcpy.c index 1053a53..217f73b 100644 --- a/src/lib/memcpy.c +++ b/src/lib/memcpy.c @@ -10,3 +10,18 @@ void *memcpy(void *vdest, const void *vsrc, size_t bytes) return vdest; } + +/* from linux kernel 2.6.32 asm/string_32.h */ +void inline __attribute__((always_inline)) memcopy_fast(void *dest, const void *src, unsigned long bytes) +{ + int d0, d1, d2; + asm volatile("cld ; rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "andl $3,%%ecx\n\t" + "jz 1f\n\t" + "rep ; movsb\n\t" + "1:" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) + : "memory", "cc"); +} diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b2ca256..759f0c2 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -28,6 +28,7 @@ #include #include #include +#include #include @@ -332,11 +333,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; @@ -691,12 +687,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)high_tables_size, high_tables_base); } #endif @@ -721,17 +717,18 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmi if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n",uma_memory_base); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx, ",uma_memory_base); #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024)- HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - } + high_tables_size = HIGH_MEMORY_SIZE; + } #endif } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n",mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); +printk(BIOS_DEBUG, " adsr - high_tables_base=%x%x\n", (u32) (high_tables_base >> 32), (u32) high_tables_base); #if CONFIG_GFXUMA == 1 printk(BIOS_DEBUG, "adsr - adding uma resource.\n"); @@ -746,22 +743,46 @@ printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",high_tables_size); printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } +extern u8 acpi_slp_type; static void domain_enable_resources(device_t dev) { u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid (); - if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -795,24 +816,41 @@ static void cpu_bus_set_resources(device_t dev) pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) +static u32 cpu_bus_scan(device_t dev, u32 max) { - struct device_path cpu_path; device_t cpu; - int apic_id; - - initialize_cpus(dev->link_list); + struct device_path cpu_path; + int apic_id, cores_found; + + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); + + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } + } + return max; +} - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; - } +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } @@ -858,7 +896,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; From russ at ashlandhome.net Wed Feb 15 08:07:50 2012 From: russ at ashlandhome.net (Russell Whitaker) Date: Tue, 14 Feb 2012 23:07:50 -0800 (PST) Subject: [coreboot] "Fix multipleVGA cards resource conflict on Windows" broke my vga In-Reply-To: References: <201202141331.35029.GNUtoo@no-log.org> Message-ID: On Tue, 14 Feb 2012, Marc Jones wrote: > Hi Denis, > > On Tue, Feb 14, 2012 at 5:31 AM, Denis 'GNUtoo' Carikli > wrote: >> hi, >> >> I've an M4A785T-M which contains one onboard graphic card, >> but it has 2 VGA extension roms. >> one seem to be for HDMI, and the other for VGA. > > That sounds strange. I think that they are basicly the same output and > should have a single rom. Are there two device IDs? If there are two > devices, it seems that there is a problem selecting the default and > allocating the decode correctly. >> >> reverting the commit makes VGA appear on my monitor. >> >> I've tried to add one option rom only, as usual, and nothing appeared on my >> monitor with that comit. >> Then I removed the VGA rom and with cbfstool I added both VGA rom. >> Nothing appeared on my monitor either... >> >> Should I give some logs(it's quite long to get since I've to reflash with an >> external programmer). >> >> Denis. >> > > Logs would help, but you could some analysis about what setting is > making the device work or not. > > Marc > Could the two roms be interleaved? If they have 8bit data, then one might be bits 0-7 and the other 8-15. Just a thought. Russ From gerrit at coreboot.org Wed Feb 15 15:25:53 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 15 Feb 2012 15:25:53 +0100 Subject: [coreboot] New patch to review for coreboot: e8a4832 Intel model_106cx: Use symbolic names for MTRR bits References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/637 -gerrit commit e8a4832907c4ff5d126c32acde22a00ad35b6395 Author: Ky?sti M?lkki Date: Wed Feb 15 15:55:03 2012 +0200 Intel model_106cx: Use symbolic names for MTRR bits Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_106cx/cache_as_ram.inc | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index eb3d650..824e341 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -63,14 +63,14 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax xorl %edx, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -113,7 +113,7 @@ clear_mtrrs: movl $MTRRphysMask_MSR(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -155,7 +155,7 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -196,7 +196,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax xorl %edx, %edx wrmsr @@ -212,7 +212,7 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) From gerrit at coreboot.org Wed Feb 15 15:25:53 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 15 Feb 2012 15:25:53 +0100 Subject: [coreboot] New patch to review for coreboot: f548d59 Intel cpus: use CPU_PHYSMASK_HI define in CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/638 -gerrit commit f548d593f020bd56c1bb7fa75ea8d6cb11cb0428 Author: Ky?sti M?lkki Date: Wed Feb 15 15:55:57 2012 +0200 Intel cpus: use CPU_PHYSMASK_HI define in CAR Unifies models 6ex, 6fx and 106cx. Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_106cx/cache_as_ram.inc | 9 ++++++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 11 +++++++---- src/cpu/intel/model_6fx/cache_as_ram.inc | 9 ++++++--- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 824e341..caf5d03 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -22,6 +22,9 @@ #include #include +#define CPU_MAXPHYADDR 32 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -64,7 +67,7 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - xorl %edx, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ @@ -112,7 +115,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - xorl %edx, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -197,7 +200,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(0), %ecx movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - xorl %edx, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x39) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 18ada29..08f5b11 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -22,6 +22,9 @@ #include #include +#define CPU_MAXPHYADDR 36 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -64,7 +67,7 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ @@ -112,7 +115,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -197,7 +200,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(0), %ecx movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable caching and Speculative Reads for the last 4MB. */ @@ -207,7 +210,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x39) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index dfc4f3b..25d8de2 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -22,6 +22,9 @@ #include #include +#define CPU_MAXPHYADDR 36 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -71,7 +74,7 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ @@ -119,7 +122,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx + movl $CPU_PHYSMASK_HI, %edx movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -204,7 +207,7 @@ clear_mtrrs: wrmsr movl $MTRRphysMask_MSR(0), %ecx movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $0x0000000f, %edx // 36bit address space + movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x39) From vidwer at gmail.com Wed Feb 15 17:33:45 2012 From: vidwer at gmail.com (Idwer Vollering) Date: Wed, 15 Feb 2012 17:33:45 +0100 Subject: [coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)? Message-ID: Or: how to start a multicore (hyperthreading) processor as if it were a singlecore (non-hyperthreading) processor. Would it be necessary to configure APIC/IPI in serialice' mainboard specific code? See these message [1] [2] [3]. This is the output from two processors with hyperthreading disabled and enabled: $ diff cpu_intel_p4_model_f29_msr_with_ht_disabled.txt cpu_intel_p4_model_f29_msr_with_ht_enabled.txt2 41c41 < MSR 0x00000300 = 0x000000FD:0x8E129919 (MSR_BPU_COUNTER0) --- > MSR 0x00000300 = 0x000000FC:0xEB7BD6C3 (MSR_BPU_COUNTER0) 43c43 < MSR 0x00000302 = 0x00000000:0x00000000 (MSR_BPU_COUNTER2) --- > MSR 0x00000302 = 0x000000FB:0x75D2A276 (MSR_BPU_COUNTER2) 61c61 < MSR 0x00000362 = 0x00000000:0x00000000 (MSR_BPU_CCCR2) --- > MSR 0x00000362 = 0x00000000:0x0803D000 (MSR_BPU_CCCR2) 80c80 < MSR 0x000003A3 = 0x00000000:0x00000000 (MSR_FSB_ESCR1) --- > MSR 0x000003A3 = 0x00000000:0x26000203 (MSR_FSB_ESCR1) 147c147 < MSR 0x00000010 = 0x0000003A:0x8FB50494 (IA32_TIME_STAMP_COUNTER) --- > MSR 0x00000010 = 0x00000045:0x41DA8FAC (IA32_TIME_STAMP_COUNTER) 179a180,222 > MSR 0x000001D8 = 0x00000000:0x00000000 (MSR_LER_TO_LIP) > MSR 0x000001D9 = 0x00000000:0x00000000 (MSR_DEBUGCTLA) > MSR 0x000001DA = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS) > MSR 0x000001DB = 0x00000000:0x00000000 (MSR_LASTBRANCH_0) > MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LASTBRANCH_2) > MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LASTBRANCH_3) > MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT) > MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA) > > ====================== UNIQUE MSRs (core 1) ====================== > MSR 0x00000010 = 0x00000045:0x41DE63F4 (IA32_TIME_STAMP_COUNTER) > MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE) > MSR 0x0000008B = 0x0000002E:0x00000000 (IA32_BIOS_SIGN_ID) > MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP) > MSR 0x00000174 = 0x00000000:0x00000060 (IA32_SYSENTER_CS) > MSR 0x00000175 = 0x00000000:0xF6606FC0 (IA32_SYSENTER_ESP) > MSR 0x00000176 = 0x00000000:0xC047C31C (IA32_SYSENTER_EIP) > MSR 0x00000179 = 0x00000000:0x000C0204 (IA32_MCG_CAP) > MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) > (*) MSR 0x0000017B = 0xFFFFFFFF:0xFFFFFFFF (IA32_MCG_CTL) > MSR 0x00000180 = 0x00000000:0x00000000 (MSR_MCG_RAX) > MSR 0x00000181 = 0x00000000:0x00000000 (MSR_MCG_RBX) > MSR 0x00000182 = 0x00000000:0x00000000 (MSR_MCG_RCX) > MSR 0x00000183 = 0x00000000:0x00000000 (MSR_MCG_RDX) > MSR 0x00000184 = 0x00000000:0x00000000 (MSR_MCG_RSI) > MSR 0x00000185 = 0x00000000:0x00000000 (MSR_MCG_RDI) > MSR 0x00000186 = 0x00000000:0x00000000 (MSR_MCG_RBP) > MSR 0x00000187 = 0x00000000:0x00000000 (MSR_MCG_RSP) > MSR 0x00000188 = 0x00000000:0x00000000 (MSR_MCG_RFLAGS) > MSR 0x00000189 = 0x00000000:0x00000000 (MSR_MCG_RIP) > MSR 0x0000018A = 0x00000000:0x00000000 (MSR_MCG_MISC) > (*) MSR 0x00000190 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R8) > (*) MSR 0x00000191 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R9) > (*) MSR 0x00000192 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R10) > (*) MSR 0x00000193 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R11) > (*) MSR 0x00000194 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R12) > (*) MSR 0x00000195 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R13) > (*) MSR 0x00000196 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R14) > (*) MSR 0x00000197 = 0xFFFFFFFF:0xFFFFFFFF (MSR_MCG_R15) > MSR 0x0000019A = 0x00000000:0x00000002 (IA32_CLOCK_MODULATION) > MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) > MSR 0x000001A0 = 0x00000000:0x00000089 (IA32_MISC_ENABLE) > MSR 0x000001D7 = 0x00000000:0xFFFFE066 (MSR_LER_FROM_LIP) And: $ diff cpu_intel_p4_model_f49_msr_with_ht_enabled.txt cpu_intel_p4_model_f49_msr_with_ht_dis abled.txt 45c45 < MSR 0x00000300 = 0x000000FC:0x2C774AC9 (MSR_BPU_COUNTER0) --- > MSR 0x00000300 = 0x000000FC:0xF2106B69 (MSR_BPU_COUNTER0) 47c47 < MSR 0x00000302 = 0x000000FA:0xF37E6A39 (MSR_BPU_COUNTER2) --- > MSR 0x00000302 = 0x00000000:0x00000000 (MSR_BPU_COUNTER2) 71c71 < MSR 0x00000010 = 0x0000004C:0x69A3BC78 (IA32_TIME_STAMP_COUNTER) --- > MSR 0x00000010 = 0x0000002E:0xD3FA1647 (IA32_TIME_STAMP_COUNTER) 79,121d78 < MSR 0x00000176 = 0x00000000:0xC047C31C (IA32_SYSENTER_EIP) < MSR 0x00000179 = 0x00000000:0x00180204 (IA32_MCG_CAP) < MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS) < MSR 0x00000180 = 0x00000000:0x00000000 (MSR_MCG_RAX) < MSR 0x00000181 = 0x00000000:0x00000000 (MSR_MCG_RBX) < MSR 0x00000182 = 0x00000000:0x00000000 (MSR_MCG_RCX) < MSR 0x00000183 = 0x00000000:0x00000000 (MSR_MCG_RDX) < MSR 0x00000184 = 0x00000000:0x00000000 (MSR_MCG_RSI) < MSR 0x00000185 = 0x00000000:0x00000000 (MSR_MCG_RDI) < MSR 0x00000186 = 0x00000000:0x00000000 (MSR_MCG_RBP) < MSR 0x00000187 = 0x00000000:0x00000000 (MSR_MCG_RSP) < MSR 0x00000188 = 0x00000000:0x00000000 (MSR_MCG_RFLAGS) < MSR 0x00000189 = 0x00000000:0x00000000 (MSR_MCG_RIP) < MSR 0x0000018A = 0x00000000:0x00000000 (MSR_MCG_MISC) < MSR 0x00000190 = 0x00000000:0x00000000 (MSR_MCG_R8) < MSR 0x00000191 = 0x00000000:0x00000000 (MSR_MCG_R9) < MSR 0x00000192 = 0x00000000:0x00000000 (MSR_MCG_R10) < MSR 0x00000193 = 0x00000000:0x00000000 (MSR_MCG_R11) < MSR 0x00000194 = 0x00000000:0x00000000 (MSR_MCG_R12) < MSR 0x00000195 = 0x00000000:0x00000000 (MSR_MCG_R13) < MSR 0x00000196 = 0x00000000:0x00000000 (MSR_MCG_R14) < MSR 0x00000197 = 0x00000000:0x00000000 (MSR_MCG_R15) < MSR 0x00000198 = 0x00000F2D:0x00000F2D (IA32_PERF_STATUS) < MSR 0x00000199 = 0x00000000:0x00000F2D (IA32_PERF_CTL) < MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION) < MSR 0x0000019B = 0x00000000:0x00000003 (IA32_THERM_INTERRUPT) < MSR 0x000001A0 = 0x00000004:0x20840489 (IA32_MISC_ENABLE) < MSR 0x000001D7 = 0x00000000:0x00000000 (MSR_LER_FROM_LIP) < MSR 0x000001D8 = 0x00000000:0x00000000 (MSR_LER_TO_LIP) < MSR 0x000001D9 = 0x00000000:0x00000000 (MSR_DEBUGCTLA) < MSR 0x000001DA = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS) < MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT) < MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA) < < ====================== UNIQUE MSRs (core 1) ====================== < MSR 0x00000010 = 0x0000004C:0x69AE1BD2 (IA32_TIME_STAMP_COUNTER) < MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE) < (*) MSR 0x0000003A = 0xFFFFFFFF:0xFFFFFFFF (IA32_FEATURE_CONTROL) < MSR 0x0000008B = 0x00000003:0x00000000 (IA32_BIOS_SIGN_ID) < (*) MSR 0x0000009B = 0xFFFFFFFF:0xFFFFFFFF (IA32_SMM_MONITOR_CTL) < MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP) < MSR 0x00000174 = 0x00000000:0x00000060 (IA32_SYSENTER_CS) < MSR 0x00000175 = 0x00000000:0xF6106FC0 (IA32_SYSENTER_ESP) [1] http://serialice.com/pipermail/serialice/2011-December/000305.html [2] http://serialice.com/pipermail/serialice/2009-December/000068.html [3] http://www.serialice.com/trac/serialice/changeset/82 From gerrit at coreboot.org Wed Feb 15 18:04:35 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 15 Feb 2012 18:04:35 +0100 Subject: [coreboot] Patch merged into coreboot/master: e8a4832 Intel model_106cx: Use symbolic names for MTRR bits References: Message-ID: the following patch was just integrated into master: commit e8a4832907c4ff5d126c32acde22a00ad35b6395 Author: Ky?sti M?lkki Date: Wed Feb 15 15:55:03 2012 +0200 Intel model_106cx: Use symbolic names for MTRR bits Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Wed Feb 15 15:48:21 2012, giving +1 Reviewed-By: Stefan Reinauer at Wed Feb 15 18:04:32 2012, giving +2 See http://review.coreboot.org/637 for details. -gerrit From stefan.reinauer at coreboot.org Wed Feb 15 18:05:26 2012 From: stefan.reinauer at coreboot.org (Stefan Reinauer) Date: Wed, 15 Feb 2012 18:05:26 +0100 Subject: [coreboot] [SerialICE] Which MSR disables hyperthreading (all non-BSP/AP cores)? In-Reply-To: References: Message-ID: <20120215170526.GA21626@coreboot.org> * Idwer Vollering [120215 17:33]: > Or: how to start a multicore (hyperthreading) processor as if it were > a singlecore (non-hyperthreading) processor. > > Would it be necessary to configure APIC/IPI in serialice' mainboard > specific code? You probably need something like: /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax movl $0xFEE00300, %esi movl %eax, (%esi) (Taken from cache_as_ram.inc on model_6ex) Stefan From kyosti.malkki at gmail.com Wed Feb 15 20:19:22 2012 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Wed, 15 Feb 2012 21:19:22 +0200 Subject: [coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)? In-Reply-To: References: Message-ID: <1329333562.5785.320.camel@obelix> On Wed, 2012-02-15 at 17:33 +0100, Idwer Vollering wrote: > Or: how to start a multicore (hyperthreading) processor as if it were > a singlecore (non-hyperthreading) processor. > To my knowledge, there is no such MSR for P4 Hyper-Threaded CPUs using the NetBurst Architecture. So SerialICE may need a patch for hyper-threaded CPUs to enable Cache-As-Ram, like coreboot does. You've seen my cache-as-ram code with SIPIs for model f25 (P4 Xeon on socket 604), to enable cache on HT-enabled CPU. >From your responses (on e-mail) so far, I cannot determine where (if) it stops with P4 models f29 and f49 on socket 478 (?). You have actual POST code PCI device, make wise use of it. Thanks, KM From GNUtoo at no-log.org Wed Feb 15 23:57:12 2012 From: GNUtoo at no-log.org (Denis 'GNUto' Carikli) Date: Wed, 15 Feb 2012 23:57:12 +0100 Subject: [coreboot] "Fix multipleVGA cards resource conflict on Windows" broke my vga In-Reply-To: References: <201202141331.35029.GNUtoo@no-log.org> Message-ID: <1329346632.2637.0.camel@gnutoo-TOSHIBA-NB550D> On Tue, 2012-02-14 at 13:47 -0700, Marc Jones wrote: > Logs would help, but you could some analysis about what setting is > making the device work or not. Searching for pci1002,9710.rom Check cmos_layout.bin Check pci1002,9710.rom In CBFS, ROM address for PCI: 01:05.0 = fff00778 PCI expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 9710, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fff00778 to 0xc0000, 0xec00 bytes [hangs here] here are the logs. Denis. From gerrit at coreboot.org Thu Feb 16 01:55:51 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 01:55:51 +0100 Subject: [coreboot] Patch merged into coreboot/master: f548d59 Intel cpus: use CPU_PHYSMASK_HI define in CAR References: Message-ID: the following patch was just integrated into master: commit f548d593f020bd56c1bb7fa75ea8d6cb11cb0428 Author: Ky?sti M?lkki Date: Wed Feb 15 15:55:57 2012 +0200 Intel cpus: use CPU_PHYSMASK_HI define in CAR Unifies models 6ex, 6fx and 106cx. Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Wed Feb 15 16:00:27 2012, giving +1 Reviewed-By: Stefan Reinauer at Thu Feb 16 01:55:49 2012, giving +2 See http://review.coreboot.org/638 for details. -gerrit From oliver at schinagl.nl Thu Feb 16 02:00:44 2012 From: oliver at schinagl.nl (Oliver Schinagl) Date: Thu, 16 Feb 2012 02:00:44 +0100 Subject: [coreboot] flash-chip (and compatibles) In-Reply-To: <4E4D2C9C.8050704@schinagl.nl> References: <4E4D2BC4.1010607@schinagl.nl> <4E4D2C9C.8050704@schinagl.nl> Message-ID: <4F3C553C.6060509@schinagl.nl> I was pointed to this one: A25L032-F (There's also a Q version, which I don't think is what I'd want). http://nl.farnell.com/jsp/search/browse.jsp?N=202454+110164787+110184599&No=0&getResults=true&appliedparametrics=true&locale=nl_NL&divisionLocale=nl_NL&catalogId=&skipManufacturer=false&skipParametricAttributeId=&prevNValues=202454+110164787&mm=1001723||,1001917||,&filtersHidden=false&appliedHidden=false&autoApply=false&originalQueryURL=%2Fjsp%2Fsearch%2Fbrowse.jsp%3FN%3D202454%26No%3D0%26getResults%3Dtrue%26appliedparametrics%3Dtrue%26locale%3Dnl_NL%26divisionLocale%3Dnl_NL%26catalogId%3D%26skipManufacturer%3Dfalse%26skipParametricAttributeId%3D%26prevNValues%3D202454 Are these good to order a few for? > If you plan to use big payloads (anything involving a Linux kernel), > you should get 4MB or 8MB parts. I haven't found a 64Mbit chip yet, so I hope I could use a linux kernel as payload using a 4MB one (the current 32Mbit) > On Thu, 18 Aug 2011 17:15:40 +0200 > Oliver Schinagl> wrote: > > >/ I did find a pdf that was somewhat interesting: > />/ > />/ http://www.msc-ge.com/download/pcn/macronix/pcn-10-037.pdf > />/ > />/ it basically mentions/confirms it's an SPI/serial based 32Mb flash, > />/ dunno if that can help me find a pin-compatible chip :S > / > hello oliver > > MX25L3206EPI-12G > > that chip is not special at all and can be replaced by (almost?) any > 25-series flash chip with the same package (300mil 8-PDIP) and voltage > rating (2.7 - 3.6V). > of course there are corner cases, but in general there should not be a > big problem with other vendors. if you have found an offer that suits > you, you could ask us again... > -- > Kind regards/Mit freundlichen Gr??en, Stefan Tauner -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Thu Feb 16 02:44:02 2012 From: peter at stuge.se (Peter Stuge) Date: Thu, 16 Feb 2012 02:44:02 +0100 Subject: [coreboot] flash-chip (and compatibles) In-Reply-To: <4F3C553C.6060509@schinagl.nl> References: <4E4D2BC4.1010607@schinagl.nl> <4E4D2C9C.8050704@schinagl.nl> <4F3C553C.6060509@schinagl.nl> Message-ID: <20120216014402.29039.qmail@stuge.se> Oliver Schinagl wrote: > I was pointed to this one: A25L032-F > http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085 > > (There's also a Q version, which I don't think is what I'd want). Correct. Q is a WSON package which does not fit at all. Make sure you buy farnell nr. 1907085 and nothing else. A25L032-F is indeed the accurate manufacturer's part number, if you order somewhere else. > I haven't found a 64Mbit chip yet, so I hope I could use a linux > kernel as payload using a 4MB one (the current 32Mbit) Winbond W25Q64CV But Winbond's distributors AVNET and Digi-Key, http://www.winbond-usa.com/winbondcms/Application/member/Distributors.aspx?partno=W25Q64CV only have SO-8 in stock, and you wanted DIP. You could look for adapters, but then you must do some soldering. http://search.digikey.com/scripts/DkSearch/dksus.dll?site=us&lang=en&v=256&WT.z_supplier_id=256&WT.z_page_type=SP&WT.z_page_sub_type=SS&WT.z_oss_type=View+All&chp=0 AVNET only have SO-8 stock in Asia. You'll have to pay import fees and tax. Digi-Keys f-ing website barfs some idiotic error at me whenever I try to use it nowadays. You can buy DIP from bios-repair.co.uk, but they only have the older revision W25Q64BVAIG. For once they don't charge more than AVNET&co in single quantity. http://bios-repair.co.uk/Products/EEPROM/SPI-SerialFlash-EEPROM.html Click Winbond, then there's W25Q64BVAIG 64Mb PDIP top left in the product listing. //Peter From gerrit at coreboot.org Thu Feb 16 13:43:19 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 16 Feb 2012 13:43:19 +0100 Subject: [coreboot] New patch to review for coreboot: 1e27bae Intel cpus: use MAXPHYADDR from Kconfig during CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/639 -gerrit commit 1e27bae2f43c4ac137bc1b7cb4e9848f2981a45f Author: Ky?sti M?lkki Date: Thu Feb 16 11:05:55 2012 +0200 Intel cpus: use MAXPHYADDR from Kconfig during CAR This config determines the high 32 bits of MTRR mask registers as used during Cache-As-Ram. Run-time check in asm would be sort-of messy, but can be implemented at later time if found necessary. Default is MAXPHYADDR=36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Ky?sti M?lkki --- src/cpu/Kconfig | 7 +++++++ src/cpu/intel/model_106cx/Kconfig | 11 +++++++++++ src/cpu/intel/model_106cx/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 3 +-- 5 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..d576873 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -19,6 +19,13 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x0 +config CPU_MAXPHYADDR + int + default 36 + help + Static CPU MAXPHYADDR used for MTRR mask during Cache-As-Ram. + Later MTRR setup uses run-time check with CPUID. + config MAX_PHYSICAL_CPUS int default 1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09449cb..fa6ebfd 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,6 +1,17 @@ config CPU_INTEL_MODEL_106CX bool + +if CPU_INTEL_MODEL_106CX + +config CPU_SPECIFIC_OPTIONS # dummy + def_bool y select SMP select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + +config CPU_MAXPHYADDR + int + default 32 + +endif # CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..1e5ee64 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -22,8 +22,7 @@ #include #include -#define CPU_MAXPHYADDR 32 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..a603472 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -22,8 +22,7 @@ #include #include -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..9e3942b 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -22,8 +22,7 @@ #include #include -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE From gerrit at coreboot.org Thu Feb 16 13:43:19 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 16 Feb 2012 13:43:19 +0100 Subject: [coreboot] New patch to review for coreboot: a56cd13 Intel cpus: delete dead CAR code and whitespace fixes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/640 -gerrit commit a56cd135813643e54707900e25b55726546984f1 Author: Ky?sti M?lkki Date: Thu Feb 16 13:08:31 2012 +0200 Intel cpus: delete dead CAR code and whitespace fixes A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_106cx/cache_as_ram.inc | 14 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 16 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 271 ---------------------------- 3 files changed, 3 insertions(+), 298 deletions(-) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 1e5ee64..605bd70 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -82,7 +82,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 @@ -163,18 +163,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index a603472..8f2b1bd 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -82,7 +82,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 @@ -163,18 +163,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -192,7 +180,7 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc deleted file mode 100644 index 9e3942b..0000000 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ /dev/null @@ -1,271 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Disable prefetchers */ - movl $0x01a0, %ecx - rdmsr - orl $((1 << 9) | (1 << 19)), %eax - orl $((1 << 5) | (1 << 7)), %edx - wrmsr - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Enable prefetchers */ - movl $0x01a0, %ecx - rdmsr - andl $~((1 << 9) | (1 << 19)), %eax - andl $~((1 << 5) | (1 << 7)), %edx - wrmsr - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: - From gerrit at coreboot.org Thu Feb 16 19:26:34 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 19:26:34 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3354884 AGESA F15: AGESA family15 model 00-0fh cpu wrapper References: Message-ID: the following patch was just integrated into master: commit 33548842f15fb467b28a0a899b4ff84ceccf5116 Author: Kerry Sheh Date: Tue Feb 7 20:31:35 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 13:16:42 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 19:26:31 2012, giving +2 See http://review.coreboot.org/555 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 19:27:31 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 19:27:31 +0100 Subject: [coreboot] Patch merged into coreboot/master: d59002f pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids References: Message-ID: the following patch was just integrated into master: commit d59002f19e9dc56bd94c61f055b26bef62943540 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 13:29:49 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 19:27:28 2012, giving +2 See http://review.coreboot.org/609 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 19:36:44 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 19:36:44 +0100 Subject: [coreboot] Patch merged into coreboot/master: c8657a8 RD890: AMD RD890/SR56X0 CIMX wrapper References: Message-ID: the following patch was just integrated into master: commit c8657a8bf8e98a9e19db9f248fd44a72e747632d Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 14:52:04 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 19:33:45 2012, giving +2 See http://review.coreboot.org/559 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 21:08:52 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 21:08:52 +0100 Subject: [coreboot] Patch merged into coreboot/master: b6bebf4 SIO: Winbond w83627dhg update References: Message-ID: the following patch was just integrated into master: commit b6bebf4968019fd38a7086cbf350a9c26b4451a3 Author: Kerry Sheh Date: Tue Feb 7 20:32:37 2012 +0800 SIO: Winbond w83627dhg update 1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 15:23:23 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 21:08:49 2012, giving +2 See http://review.coreboot.org/565 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 21:19:17 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 21:19:17 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7078147 Mainboard: Supermicro/h8qgi mainboard update References: Message-ID: the following patch was just integrated into master: commit 70781479459d047979d698685b7f1393e9178e95 Author: Kerry Sheh Date: Tue Feb 7 20:32:38 2012 +0800 Mainboard: Supermicro/h8qgi mainboard update 1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 15:09:08 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 21:16:49 2012, giving +2 See http://review.coreboot.org/567 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 21:22:46 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 21:22:46 +0100 Subject: [coreboot] Patch merged into coreboot/master: b0eef97 HWM: Nuvoton W83795G/ADG HWM support References: Message-ID: the following patch was just integrated into master: commit b0eef97a218291d9efa44891b67f7ab74e434e51 Author: Kerry Sheh Date: Tue Feb 7 20:33:21 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 15:52:01 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 21:22:30 2012, giving +2 See http://review.coreboot.org/569 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 21:26:47 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 21:26:47 +0100 Subject: [coreboot] Patch merged into coreboot/master: 9bf1cc6 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper References: Message-ID: the following patch was just integrated into master: commit 9bf1cc623520b43d95ff7e55770fa30590f3b953 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 13:47:44 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 19:31:09 2012, giving +2 See http://review.coreboot.org/556 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 22:31:54 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 22:31:54 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3904286 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper References: Message-ID: the following patch was just integrated into master: commit 3904286e9ec165e90eab5466ef6f1fe6482ce4ef Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Tue Feb 7 14:37:16 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 19:41:55 2012, giving +2 See http://review.coreboot.org/561 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 22:37:07 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 22:37:07 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3887beb M4A785T-M: fix TOM2. References: Message-ID: the following patch was just integrated into master: commit 3887beb6955df88880b1a6d359b2f2bbc69117e0 Author: Denis 'GNUtoo' Carikli Date: Tue Feb 14 22:11:23 2012 +0100 M4A785T-M: fix TOM2. This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) With commit permit to boot without pci=nocrs on the M4A785T-M board. Before the fix dmesg contained the following: [ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) Now it only contains: [ 0.312102] TOM: 0000000080000000 aka 2048M Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd Signed-off-by: Denis 'GNUtoo' Carikli Build-Tested: build bot (Jenkins) at Wed Feb 15 00:16:43 2012, giving +1 Reviewed-By: Kerry Sheh at Thu Feb 16 01:37:04 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 22:35:39 2012, giving +2 See http://review.coreboot.org/635 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 22:41:30 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 16 Feb 2012 22:41:30 +0100 Subject: [coreboot] Patch merged into coreboot/master: be7d415 M4A785-M, M4A785T-M: fix SSDT tables References: Message-ID: the following patch was just integrated into master: commit be7d4152144497b7318564ef92ae96c16b522305 Author: Denis 'GNUtoo' Carikli Date: Tue Feb 14 22:38:01 2012 +0100 M4A785-M,M4A785T-M: fix SSDT tables This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4 Signed-off-by: Denis 'GNUtoo' Carikli Build-Tested: build bot (Jenkins) at Wed Feb 15 00:27:00 2012, giving +1 Reviewed-By: Kerry Sheh at Thu Feb 16 01:38:38 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 16 22:41:24 2012, giving +2 See http://review.coreboot.org/636 for details. -gerrit From gerrit at coreboot.org Thu Feb 16 22:54:32 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 16 Feb 2012 22:54:32 +0100 Subject: [coreboot] New patch to review for coreboot: 3eb82eb Intel cpus: cache actual size of the Flash ROM device References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/641 -gerrit commit 3eb82ebe06369ad6f278319989c3c574a3c9264a Author: Ky?sti M?lkki Date: Thu Feb 16 20:11:31 2012 +0200 Intel cpus: cache actual size of the Flash ROM device Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded using model_6ex CAR implementation. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_6ex/cache_as_ram.inc | 9 ++++++--- src/mainboard/Kconfig | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 8f2b1bd..cbfa4f8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -24,6 +24,9 @@ #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -190,13 +193,13 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a34bd85 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -285,6 +285,10 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 +config CACHE_ROM_SIZE + hex + default ROM_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE From gerrit at coreboot.org Thu Feb 16 22:54:32 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 16 Feb 2012 22:54:32 +0100 Subject: [coreboot] New patch to review for coreboot: 1a339d8 Intel model_106cx: change CAR to model_6ex References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/642 -gerrit commit 1a339d88a24946a8ca238f739b0f652e932dd382 Author: Ky?sti M?lkki Date: Thu Feb 16 20:28:30 2012 +0200 Intel model_106cx: change CAR to model_6ex Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 245 ---------------------------- 2 files changed, 1 insertions(+), 246 deletions(-) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index edcd01c..018febc 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc deleted file mode 100644 index 605bd70..0000000 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: - From gerrit at coreboot.org Thu Feb 16 22:54:33 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 16 Feb 2012 22:54:33 +0100 Subject: [coreboot] New patch to review for coreboot: 69dcef7 Intel model_6ex: minor CAR fixes References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643 -gerrit commit 69dcef76380deb90f2dca58a086393c00b15e6c3 Author: Ky?sti M?lkki Date: Thu Feb 16 22:38:16 2012 +0200 Intel model_6ex: minor CAR fixes Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_6ex/cache_as_ram.inc | 23 +++++++++++++---------- 1 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index cbfa4f8..5a29744 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -21,6 +21,10 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) @@ -37,9 +41,9 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -91,11 +95,10 @@ clear_mtrrs: movl %eax, %cr0 /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ @@ -130,11 +133,10 @@ clear_mtrrs: /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -145,6 +147,7 @@ clear_mtrrs: /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f) From gerrit at coreboot.org Thu Feb 16 22:54:33 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 16 Feb 2012 22:54:33 +0100 Subject: [coreboot] New patch to review for coreboot: 2e3c13a Intel cpus: add NetBurst compatibility to model_6ex CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/644 -gerrit commit 2e3c13a0b9ee6dde5a2db7b25ba3019107790f51 Author: Ky?sti M?lkki Date: Thu Feb 16 23:12:04 2012 +0200 Intel cpus: add NetBurst compatibility to model_6ex CAR P4 CPUs with NetBurst architecture have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/Kconfig | 8 ++++++++ src/cpu/intel/model_6ex/cache_as_ram.inc | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 81a834c..4e4e2ee 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -1,3 +1,11 @@ + +config INTEL_NETBURST + bool + default n + help + Select Y to bypass MSR 0x11e during CAR. + FIXME: Runtime CPUID check instead. + # CPU models source src/cpu/intel/model_6xx/Kconfig source src/cpu/intel/model_67x/Kconfig diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 5a29744..4505e0e 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -82,11 +82,19 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr - /* Enable L2 cache. */ +#if !CONFIG_INTEL_NETBURST + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). + * This MSR does not exist on NetBurst architecture. + * + * Description says this bit enables use of WBINVD and FLUSH#. + * Should this be set only after the system bus and/or memory + * controller can successfully handle write cycles? + */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax From gerrit at coreboot.org Fri Feb 17 09:10:04 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 17 Feb 2012 09:10:04 +0100 Subject: [coreboot] Patch set updated for coreboot: d1946d5 Mainboard: Add AMD dinar mainboard. References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/564 -gerrit commit d1946d5dca690404bdde13f317f2fac862f7d88f Author: Kerry Sheh Date: Tue Feb 7 20:32:34 2012 +0800 Mainboard: Add AMD dinar mainboard. Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/dinar/BiosCallOuts.c | 563 ++++++++ src/mainboard/amd/dinar/BiosCallOuts.h | 79 + src/mainboard/amd/dinar/Kconfig | 203 +++ src/mainboard/amd/dinar/Makefile.inc | 38 + src/mainboard/amd/dinar/Oem.h | 79 + src/mainboard/amd/dinar/OptionsIds.h | 64 + src/mainboard/amd/dinar/acpi/cpstate.asl | 74 + src/mainboard/amd/dinar/acpi/ide.asl | 244 ++++ src/mainboard/amd/dinar/acpi/routing.asl | 311 ++++ src/mainboard/amd/dinar/acpi/sata.asl | 149 ++ src/mainboard/amd/dinar/acpi_tables.c | 320 ++++ src/mainboard/amd/dinar/agesawrapper.c | 624 ++++++++ src/mainboard/amd/dinar/agesawrapper.h | 136 ++ src/mainboard/amd/dinar/buildOpts.c | 483 +++++++ src/mainboard/amd/dinar/chip.h | 23 + src/mainboard/amd/dinar/cmos.layout | 118 ++ src/mainboard/amd/dinar/devicetree.cb | 104 ++ src/mainboard/amd/dinar/dimmSpd.c | 333 +++++ src/mainboard/amd/dinar/dsdt.asl | 1148 +++++++++++++++ src/mainboard/amd/dinar/fadt.c | 173 +++ src/mainboard/amd/dinar/get_bus_conf.c | 156 ++ src/mainboard/amd/dinar/gpio.c | 482 ++++++ src/mainboard/amd/dinar/gpio.h | 2329 ++++++++++++++++++++++++++++++ src/mainboard/amd/dinar/irq_tables.c | 122 ++ src/mainboard/amd/dinar/mainboard.c | 138 ++ src/mainboard/amd/dinar/mptable.c | 180 +++ src/mainboard/amd/dinar/platform_cfg.h | 54 + src/mainboard/amd/dinar/rd890_cfg.c | 274 ++++ src/mainboard/amd/dinar/rd890_cfg.h | 175 +++ src/mainboard/amd/dinar/reset.c | 66 + src/mainboard/amd/dinar/romstage.c | 162 +++ src/mainboard/amd/dinar/sb700_cfg.c | 142 ++ src/mainboard/amd/dinar/sb700_cfg.h | 237 +++ 34 files changed, 9786 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 62ae584..c6de048 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -7,6 +7,8 @@ config BOARD_AMD_DB800 bool "DB800 (Salsa)" config BOARD_AMD_DBM690T bool "DBM690T (Herring)" +config BOARD_AMD_DINAR + bool "Dinar" config BOARD_AMD_MAHOGANY bool "Mahogany" config BOARD_AMD_MAHOGANY_FAM10 @@ -39,6 +41,7 @@ endchoice source "src/mainboard/amd/db800/Kconfig" source "src/mainboard/amd/dbm690t/Kconfig" +source "src/mainboard/amd/dinar/Kconfig" source "src/mainboard/amd/mahogany/Kconfig" source "src/mainboard/amd/mahogany_fam10/Kconfig" source "src/mainboard/amd/norwich/Kconfig" diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c new file mode 100644 index 0000000..39e1d13 --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -0,0 +1,563 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "SB700.h" + +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG24 +#define SB_GPIO_REG24 24 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + break; + } + } + + if(i >= CallOutCount) + { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = AGESA_SUCCESS; + return Status; +} diff --git a/src/mainboard/amd/dinar/BiosCallOuts.h b/src/mainboard/amd/dinar/BiosCallOuts.h new file mode 100644 index 0000000..22451aa --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig new file mode 100644 index 0000000..d354a49 --- /dev/null +++ b/src/mainboard/amd/dinar/Kconfig @@ -0,0 +1,203 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_DINAR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SCH4037 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select BOARD_ROMSIZE_KB_2048 + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select HAVE_ACPI_TABLES + #TODO select HAVE_ACPI_RESUME + select ENABLE_APIC_EXT_ID + select TINY_BOOTBLOCK + select GFXUMA + +config MAINBOARD_DIR + string + default amd/dinar + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Dinar" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 64 + +config MAX_PHYSICAL_CPUS + int + default 16 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x2e + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + depends on VGA_BIOS + default "1002,515e" + +config AHCI_BIOS + bool + default y + +config AHCI_BIOS_FILE + string "AHCI ROM path and filename" + depends on AHCI_BIOS + default "site-local/ahci/sb700.bin" + +config AHCI_BIOS_ID + string "AHCI device PCI IDs" + depends on AHCI_BIOS + default "1002,4391" + +config XHC_BIOS + bool + default n + +config XHC_BIOS_FILE + string "XHC BIOS path and filename" + depends on XHC_BIOS + default "site-local/xhc/Xhc.rom" + +config XHC_BIOS_ID + string "XHC device PCI IDs" + depends on XHC_BIOS + default "1022,7812" + +config CONSOLE_POST + bool + depends on !NO_POST + default n + +config SATA_CONTROLLER_MODE + hex + default 0x0 + depends on SOUTHBRIDGE_AMD_CIMX_SB700 + +config ONBOARD_LAN + bool + default y + +config ONBOARD_1394 + bool + default y + +config ONBOARD_USB30 + bool + default n + +config ONBOARD_BLUETOOTH + bool + default y + +config ONBOARD_WEBCAM + bool + default y + +config ONBOARD_TRAVIS + bool + default y + +config ONBOARD_LIGHTSENSOR + bool + default n + +config PCI_ROM_RUN + bool + default n + +config UDELAY_IO + bool + default n + +config REDIRECT_CIMX_TRACE_TO_SERIAL + bool "Redirect CIMX Trace to serial console" + default y + +endif # BOARD_AMD_DINAR diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc new file mode 100644 index 0000000..e078df7 --- /dev/null +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -0,0 +1,38 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += sb700_cfg.c +romstage-y += rd890_cfg.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += sb700_cfg.c +ramstage-y += rd890_cfg.c + +ramstage-y += reset.c + +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ + echo `wrong configuration`) diff --git a/src/mainboard/amd/dinar/Oem.h b/src/mainboard/amd/dinar/Oem.h new file mode 100644 index 0000000..67b1314 --- /dev/null +++ b/src/mainboard/amd/dinar/Oem.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define MOVE_PCIEBAR_TO_F0000000 + +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF8000000 +#else +#define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h new file mode 100644 index 0000000..e1d397e --- /dev/null +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl new file mode 100644 index 0000000..64b3f16 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/cpstate.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl new file mode 100644 index 0000000..765a67e --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/dinar/acpi/routing.asl b/src/mainboard/amd/dinar/acpi/routing.asl new file mode 100644 index 0000000..c7a9165 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/routing.asl @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + /* Bus 0, Dev 2 */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + /* Bus 0, Dev 3 */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0010FFFF, 0, 0, 18 }, + Package(){0x0010FFFF, 1, 0, 17 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, 0, 19 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* For Device(PBR2) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* For Device(PBR2) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS3, Package(){ + /* For Device(PBR3) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS3, Package(){ + /* For Device(PBR3) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS4, Package(){ + /* For Device(PBR4) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* For Device(PBR4) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* For Device(PBR5) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* For Device(PBR5) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* For Device(PBR6) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* For Device(PBR6) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* For Device(PBR7) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* For Device(PBR7) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* For Device(PE20) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APE0, Package(){ + /* For Device(PE20) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* For Device(PE21) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APE1, Package(){ + /* For Device(PE21) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* For Device(PE22) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APE2, Package(){ + /* For Device(PE22) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* For Device(PE23) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APE3, Package(){ + /* For Device(PE23) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) +} diff --git a/src/mainboard/amd/dinar/acpi/sata.asl b/src/mainboard/amd/dinar/acpi/sata.asl new file mode 100644 index 0000000..32b9cd9 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c new file mode 100644 index 0000000..ee00e81 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -0,0 +1,320 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + u32 dword; + u32 gsi_base = 0; + u32 apicid_sb700; + u32 apicid_rd890; + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write sb700 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_sb700, + IO_APIC_ADDR, + 0 + ); + + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* sb700 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_rd890, + dword, + gsi_base + ); + } + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, + 0, //BUS + 0, //SOURCE + 2, //gsirq + 0 //flags + ); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + //acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ +#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); +#endif + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); +#endif + + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c new file mode 100644 index 0000000..171deb8 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -0,0 +1,624 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include +#include +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Filecode.h" +#include + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ +/* +BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the +MMIO configuration space range. The size of the MMIO configuration space range varies with this +field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows: +Bits Buses Bits Buses +0h 1 5h 32 +1h 2 6h 64 +2h 4 7h 128 +3h 8 8h 256 +4h 16 Fh-9h Reserved +*/ +UINT8 +GetEndBusNum ( + VOID + ) +{ + UINT64 BusNum; + UINT8 Index; + for (Index = 1; Index <= 8; Index ++ ) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1 ) { + break; + } + } + return Index; +} + +static UINT32 amdinitcpuio(VOID) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 TopMem; + UINT32 NodeCnt; + UINT32 Node; + UINT32 SbLink; + UINT32 Index; + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4] + /* Find out the Link ID of Node0 that connects to the + * Southbridge (system IO hub). e.g. family10 MCM Processor, + * SbLink is Processor0 Link2, internal Node0 Link3 + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + SbLink = (PciData >> 8) & 3; //assume ganged + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ + for (Node = 0; Node < NodeCnt; Node ++) { + /* clear all MMIO Mapped Base/Limit Registers */ + for (Index = 0; Index < 8; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + /* clear all IO Space Base/Limit Registers */ + for (Index = 0; Index < 4; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* Enable MMIO on AMD CPU Address Map Controller */ + + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80); + PciData = (0xA0000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84); + PciData = 0xB0000 >> 8; + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set UMA MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + TopMem = (UINT32)MsrReg; + MsrReg = (MsrReg >> 8) | 3; + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c); + if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { + PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; + } + else { + PciData = (0x100000000ull - 1) >> 8; + } + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set XAPIC MMIO. 24K */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98); + PciData = (0xFEC00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c); + PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0); + PciData = (0xFEE00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8); + PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0); + PciData = 0x13; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4); + PciData = 0x00FFF000; + PciData &= (~0x7F); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | BIT46; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90); + + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Enable memory access */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); + + PciData |= BIT1; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); +#endif + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; +} + +VOID +OemCustomizeInitPost ( + IN AMD_POST_PARAMS *InitPost + ) +{ + InitPost->MemConfig.UmaMode = UMA_AUTO; + InitPost->MemConfig.BottomIo = 0xE0; + InitPost->MemConfig.UmaSize = 0xE0-0xC0; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + /* OEM Should Customize the defaults through this hook */ + OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + + case PICK_PSTATE: + return AcpiPstate; + + case PICK_SRAT: + return AcpiSrat; + + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + printk(BIOS_DEBUG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + /* Enable MMIO on AMD CPU Address Map Controller */ + amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate(VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); + if (Status != AGESA_SUCCESS) { + //agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdLateRunApTask (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h new file mode 100644 index 0000000..6571525 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MMIO_NP_BIT BIT7 + +/* Hudson-2 ACPI PmIO Space Define */ +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +//void brazos_platform_stage(void); +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +void sb_After_Pci_Init (void); +void sb_Mid_Post_Init (void); +void sb_Late_Post (void); +UINT32 agesawrapper_amdreadeventlog (void); +UINT32 agesawrapper_amdinitmmio (void); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c new file mode 100644 index 0000000..fd0464d --- /dev/null +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Sabine/Lynx platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ + */ +#include "AGESA.h" +#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ + + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +/* User makes option selections here + * Comment out the items wanted to be included in the build. + * Uncomment those items you with to REMOVE from the build. + */ +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +//#define BLDOPT_REMOVE_SRAT TRUE +//#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +/* Build configuration values here. +*/ +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_PLAT_NUM_IO_APICS 2 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE +#define BLDCFG_ONLINE_SPARE TRUE +#define BLDCFG_MEMORY_PARITY_ENABLE TRUE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION TRUE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 0 +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 +//#define BLDCFG_USE_ATM_MODE TRUE + +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife +//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 + +//#define IDSOPT_IDS_ENABLED TRUE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE +#define BLDCFG_PSTATE_HPC_MODE FALSE + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap +/* + * Agesa entry points used in this implementation. + */ +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "MarG34PI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} + +// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +#define INSTALL_G34_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_10_SUPPORT TRUE +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT +#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE +#undef INSTALL_FAMILY_10_SUPPORT +#define INSTALL_FAMILY_10_SUPPORT FALSE +#endif +#endif + +#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT +#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE +#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE +#endif +#endif + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0xFF) +#define DFLT_SCRUB_L2_RATE (0x10) +#define DFLT_SCRUB_L3_RATE (0x10) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0x12) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define DFLT_VRM_SLEW_RATE (2500) + +/* Process the options... + * This file include MUST occur + AFTER the user option selection settings + */ +CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF +}; + +#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList + +// And another platform specific one ... +//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = +//{ +// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, +// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, +// HT_LIST_TERMINAL +//}; + +CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList + +// A performance-per-watt optimization. +CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, + HT_LIST_TERMINAL, +}; + +// uncomment the line below to make Perf-per-watt enabled by default. +#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt + + +CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList + +CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = +{ + // Source Socket, Link (4-7 are sublink 1), Target Socket + {0, 0, 1}, + {0, 1, 1}, + {0, 3, 1}, + {0, 4, 1}, + {0, 5, 1}, + {0, 7, 1}, +}; + +#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap + +/* + * PCI Bus numbers for Drachma/Peso board + */ +CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = +{ + // Socket, Link, SecBus, SubBus + 0, 2, 0x00, 0xBF, // RD890 of Dinar + 1, 0, 0xC0, 0xFF, // HTX + HT_LIST_TERMINAL +}; + +#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers + +CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = +{ + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, + 0xFF +}; + +#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList +/* + CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = + { +// {socketA, linkA, socketB, linkB} +{0, 0, 1, 1}, +}; + +#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap +*/ + +/* + * Device Capabilities Override for disabling ID Clumping + */ +CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap + + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterfaceStub.h" +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + + // Dinar has the following routing: + // CS0 M[B,A]_CLK_H/L[0] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[1] + // CS3 M[B,A]_CLK_H/L[3] + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//HY Customer table +UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]); +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h new file mode 100644 index 0000000..42630fa --- /dev/null +++ b/src/mainboard/amd/dinar/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout new file mode 100644 index 0000000..f54529a --- /dev/null +++ b/src/mainboard/amd/dinar/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb new file mode 100644 index 0000000..92fe521 --- /dev/null +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -0,0 +1,104 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +chip northbridge/amd/agesa/family15/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on end # Link 0 + device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) + chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 off end # GPP3a Port0 + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 off end # GPP3a Port4 + device pci a.0 off end # GPP3a Port5 + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x2104" + end # northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on # SM + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/smsc/sch4037 # SIO SMSC SCH4037 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + irq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + end #SIO SMSC307 + end #LPC + device pci 14.4 on end # PCI bridge, 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15/root_complex + diff --git a/src/mainboard/amd/dinar/dimmSpd.c b/src/mainboard/amd/dinar/dimmSpd.c new file mode 100644 index 0000000..f26ec20 --- /dev/null +++ b/src/mainboard/amd/dinar/dimmSpd.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define SMBUS_BASE_ADDR 0xB00 +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define LTC4305_SMBUS_ADDR 0x94 + +typedef struct _DIMM_INFO_SMBUS{ + UINT8 SocketId; + UINT8 MemChannelId; + UINT8 DimmId; + UINT8 SmbusAddress; +} DIMM_INFO_SMBUS; +/* + * SPD address table - porting required + */ +STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = +{ + /* Socket, Channel, Dimm, Smbus */ + {0, 0, 0, 0xAC}, + {0, 0, 1, 0xAE}, + {0, 1, 0, 0xA8}, + {0, 1, 1, 0xAA}, + {0, 2, 0, 0xA4}, + {0, 2, 1, 0xA6}, + {0, 3, 0, 0xA0}, + {0, 3, 1, 0xA2}, + {1, 0, 0, 0xAC}, + {1, 0, 1, 0xAE}, + {1, 1, 0, 0xA8}, + {1, 1, 1, 0xAA}, + {1, 2, 0, 0xA4}, + {1, 2, 1, 0xA6}, + {1, 3, 0, 0xA0}, + {1, 3, 1, 0xA2} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +STATIC +VOID +WritePmReg ( + IN UINT8 Reg, + IN UINT8 Data + ) +{ + __outbyte (0xCD6, Reg); + __outbyte (0xCD7, Data); +} +STATIC +VOID +SetupFch ( + IN UINT16 + IN IoBase + ) +{ + + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + /* set SMBus clock to 400 KHz */ + __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4); +} + +/* + * + * ReadSmbusByteData - read a single SPD byte from any offset + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + + Address |= 1; // set read bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and read bit + __outbyte (Iobase + 2, 0x48); // read byte command + + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + *ByteData = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} +/* + * + * WriteSmbusByteData - Write a single SPD byte onto any offset + * + */ +STATIC +AGESA_STATUS +WriteSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + IN UINT8 ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + Address &= 0xFE; // set write bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and write bit + __outbyte (Iobase + 5, ByteData); // offset in byte data // + __outbyte (Iobase + 2, 0x48); // write byte command + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByte ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *Buffer + ) +{ + UINTN Status; + UINT64 Limit; + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + Buffer [0] = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSpd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + * + */ + +STATIC +AGESA_STATUS +ReadSpd ( + IN UINT16 IoBase, + IN UINT8 SmbusSlaveAddress, + OUT UINT8 *Buffer, + IN UINTN Count + ) +{ + UINTN Index, Status; + + /* read the first byte using offset zero */ + Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0); + if (Status) return Status; + + /* read the remaining bytes using auto-increment for speed */ + for (Index = 1; Index < Count; Index++){ + Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]); + if (Status) return Status; + } + return 0; +} + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ) +{ + AGESA_STATUS Status; + UINT8 SmBusAddress = 0; + UINTN Index; + UINTN MaxSocket = DIMENSION (SpdAddrLookup); + + for (Index = 0; Index < MaxSocket; Index ++){ + if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && + (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && + (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { + SmBusAddress = SpdAddrLookup[Index].SmbusAddress; + break; + } + } + + + if (SmBusAddress == 0) return AGESA_ERROR; + + SetupFch (SMBUS_BASE_ADDR); + + Status = WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + + switch (SpdData->SocketId) { + case 0: + /* Switch onto the First CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + break; + case 1: + /* Switch onto the Second CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x40, 0x03); + break; + default: + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + break; + } + Status = ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 256); + + /*Output SPD Debug Message*/ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + printk(BIOS_DEBUG, " Status = %d\n",Status); + printk(BIOS_DEBUG, "SocketId MemChannelId SpdData->DimmId SmBusAddress Buffer\n"); + printk(BIOS_DEBUG, "%x, %x, %x, %x, %x\n", SpdData->SocketId, SpdData->MemChannelId, SpdData->DimmId, SmBusAddress, SpdData->Buffer); + + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + return Status; +} diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl new file mode 100644 index 0000000..1cbb05e --- /dev/null +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -0,0 +1,1148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "DINAR ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSV, Ones) /* Assume nothing */ + Name(GPIC, 0x1) /* Assume PIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) + Field(PIRQ, ByteAcc, NoLock, Preserve) { + PIDX, 0x00000008, + PDAT, 0x00000008, /* Offset: 1h */ + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + Offset(0x10), + PIRS, 0x00000008, + Offset(0x13), + HDAD, 0x00000008, + , 0x00000008, + GEC, 0x00000008, + Offset(0x30), + USB1, 0x00000008, + USB2, 0x00000008, + USB3, 0x00000008, + USB4, 0x00000008, + USB5, 0x00000008, + USB6, 0x00000008, + USB7, 0x00000008, + Offset(0x40), + IDE, 0x00000008, + SATA, 0x00000008, + Offset(0x50), + GPP0, 0x00000008, + GPP1, 0x00000008, + GPP2, 0x00000008, + GPP3, 0x00000008 + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ + OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) + Field(PMRG, ByteAcc, NoLock, Preserve) { + PMRI, 0x00000008, + PMRD, 0x00000008, + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { + Offset(0x24), + MMSO,32, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x50), + HPAD,32, + Offset(0x60), + P1EB,16, + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xC8), + ,2, + SPRE,1, + TPDE,1, + Offset(0xF0), + ,3, + RSTU,1 + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, NoLock, Preserve) { + ,14, + PEWS,1, + WSTA,1, + ,14, + PEWD,1 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + /* Debug Port registers, 80h. */ + OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) + Field(DBBG, ByteAcc, NoLock, Preserve) { + DBG8, 0x00000008, + } + + Method(_PIC, 1) { + Store(Arg0, GPIC) + If (GPIC) { + Store(0xAA, \_SB.DBG8) + \_SB.DSPI() + } else { + Store(0xAC, \_SB.DBG8) + } + } + + Method(DSPI, 0) { + \_SB.GRUA(0x1F) + \_SB.GRUB(0x1F) + \_SB.GRUC(0x1F) + \_SB.GRUD(0x1F) + Store(0x1F, PIRE) + Store(0x1F, PIRF) + Store(0x1F, PIRG) + Store(0x1F, PIRH) + } + + Method(GRUA, 1) { + Store(Arg0, PIRA) + Store(Arg0, HDAD) + Store(Arg0, GEC) + Store(Arg0, GPP0) + Store(Arg0, GPP0) + } + + Method(GRUB, 1) { + Store(Arg0, PIRB) + Store(Arg0, USB2) + Store(Arg0, USB4) + Store(Arg0, USB6) + Store(Arg0, GPP1) + Store(Arg0, IDE) + } + + Method(GRUC, 1) { + Store(Arg0, PIRC) + Store(Arg0, USB1) + Store(Arg0, USB3) + Store(Arg0, USB5) + Store(Arg0, USB7) + Store(Arg0, GPP2) + } + + Method(GRUD, 1) { + Store(Arg0, PIRD) + Store(Arg0, SATA) + Store(Arg0, GPP3) + } + + Name(IRQB, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 15 + }}) + + Name(IRQP, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 3, 4, 5, 7, 10, 11, 12, 14, 15 + }}) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUA(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUA(Local0) + } + } + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUB(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUB(Local0) + } + } + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUC(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUC(Local0) + } + } + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUD(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUD(Local0) + } + } + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRE) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRE) + } + } + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRF) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRF) + } + } + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRG) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRG) + } + } + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRH) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRH) + } + } + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PEWS, PEWS) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + } /* End Scope GPE */ + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + External (TOM3) + External (TOM4) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + Method(_PRT,0) { + If(GPIC){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Method(_STA,0) { + Return(0x0F) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Method(_PRT,0) { + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* The external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Method(_PRT,0) { + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Method(_PRT,0) { + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Method(_PRT,0) { + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Method(_PRT,0) { + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Method(_PRT,0) { + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Method(_PRT,0) { + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Method(_PRT,0) { + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Method(_PRT,0) { + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Method(_PRT,0) { + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* Describe the Southbridge devices */ + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + } + } /* end AZHD */ + + Device(GEC) { + Name(_ADR, 0x00140006) + } /* end GEC */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + } /* end UOH1 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + } /* end UOH3 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + } /* end UEH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + } /* end UOH2 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + } /* end UOH4 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + } /* end UOH5 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + } /* end XHC0 */ + + Device(XHC1) { + Name(_ADR, 0x00100001) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {8} + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {0} + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IRQNoFlags () {12} + }) + Method (_STA, 0) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + } /* end LIBR */ + + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method(_STA, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(0x0F) + } + Return(0x0) + } + Method(_CRS, 0) { + CreateDWordField(CRS, 0x0A, HPEB) + Store(HPAD, Local0) + And(Local0, 0xFFFFFFC0, HPEB) + Return(CRS) + } + } /* End Device(_SB.PCI0.HPET) */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + Store(\_SB.PCI0.TOM1, MM1B) + Subtract(PCBA, MM1B, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ +} +/* End of ASL file */ diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c new file mode 100644 index 0000000..baf0328 --- /dev/null +++ b/src/mainboard/amd/dinar/fadt.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include +#include +#include +#include +#include +#include "Platform.h" /*sb700 platform header*/ + +#ifndef ACPI_BLK_BASE +#define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c new file mode 100644 index 0000000..f66e92c --- /dev/null +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb700[2]; +u8 bus_rd890[14]; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* + * HT Chain device num, actually it is unit id base of every ht device in chain, + * assume every chain only have 4 ht device at most + */ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_sb700; +u32 sbdn_rd890; + +static u32 get_bus_conf_done = 0; + + + + +void get_bus_conf(void) +{ + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); + + sbdn_sb700 = 0; + + for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { + bus_sb700[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) { + bus_rd890[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + + bus_rd890[0] = (pci1234x[0] >> 16) & 0xff; + bus_sb700[0] = bus_rd890[0]; + + /* sb700 */ + dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + + + + if (dev) { + bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb700[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rd890 */ + for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) { + dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0)); + if (dev) { + bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rd890[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rd890[i]] = 1; /* PCI bus. */ + } + } + } + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX +// sb_After_Pci_Init(); +// sb_Late_Post(); +#endif + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); +} diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c new file mode 100644 index 0000000..f18c09d --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.c @@ -0,0 +1,482 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Filecode.h" +#include "Hudson-2.h" +#include "AmdSbLib.h" +#include "gpio.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG07 +#define SB_GPIO_REG07 7 +#endif + +#ifndef SB_GPIO_REG25 +#define SB_GPIO_REG25 25 +#endif + +#ifndef SB_GPIO_REG26 +#define SB_GPIO_REG26 26 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +void gpioEarlyInit (void); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +void +gpioEarlyInit( + void + ) +{ + u8 Flags; + u8 Data8 = 0; + u8 StripInfo = 0; + u8 BoardType = 1; + u8 RegIndex8 = 0; + u8 boardRevC = 0x2; + u16 Data16 = 0; + u32 Index = 0; + u32 AcpiMmioAddr = 0; + u32 GpioMmioAddr = 0; + u32 IoMuxMmioAddr = 0; + u32 MiscMmioAddr = 0; + u32 SmiMmioAddr = 0; + u32 andMask32 = 0; + + // Enable HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + Data8 |= BIT0; + WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + // Get HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); + Data16 = Data8 << 8; + ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); + Data16 |= Data8; + AcpiMmioAddr = (u32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE; + MiscMmioAddr = AcpiMmioAddr + MISC_BASE; + Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); + if ((Data8 & BIT4) == 0) { + BoardType = 0; // external clock board + } + Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); + StripInfo = (Data8 & BIT7) >> 7; + Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); + StripInfo |= (Data8 & BIT7) >> 6; + if (StripInfo < boardRevC) { // for old board. Rev B + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + } + for (Index = 0; Index < MAX_GPIO_NO; Index++) { + if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { + if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { + // Configure multi-funtion + Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); + } + // Configure GPIO + if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { + Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); + Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); + } + if (Index == GPIO_65) { + if ( BoardType == 0 ) { + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + } + } + } + // Configure GEVENT + if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { + SmiMmioAddr = AcpiMmioAddr + SMI_BASE; + + andMask32 = ~(1 << (Index - GEVENT_00)); + + //EventEnable: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); + + //SciTrig: 0-Falling Edge, 1-Rising Edge + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); + + //SciLevl: 0-Edge trigger, 1-Level Trigger + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); + + //SmiSciEn: 0-Not send SMI, 1-Send SMI + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); + + //SciS0En: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); + + //SciMap: 00000b ~ 11111b + RegIndex8=(u8)((Index - GEVENT_00) >> 2); + Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); + + //SmiTrig: 0-Active Low, 1-Active High + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); + + //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + RegIndex8=(u8)((Index - GEVENT_00) >> 4); + Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); + } + } + + // + // config MXM + // GPIO9: Input for MXM_PRESENT2# + // GPIO10: Input for MXM_PRESENT1# + // GPIO28: Input for MXM_PWRGD + // GPIO35: Output for MXM Reset + // GPIO45: Output for MXM Power Enable, active HIGH + // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + // + // set INTE#/GPIO32 as GPO for PCIE_SW + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); + + // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + + // set AD9/GPIO9 as GPI for MXM_PRESENT2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + + // set AD10/GPIO10 as GPI for MXM_PRESENT1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + + // set GNT1#/GPIO44 as GPO for MXM Reset + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + + // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + + // set AD28/GPIO28 as GPI for MXM_PWRGD + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + + // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); + + // + // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). + // + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + + // check if there any GFX card + Flags = 0; + // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); + // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); + ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); + ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + Flags = 1; + } + } + if ( Flags ) + { + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + // WAIT POWER READY: GPIO28 (MXM_PWRGD) + //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + while (!(Data8 && BIT7)) + { + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + } + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset + // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + } + else + { + // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); + } + + // + // APU GPP0: On board LAN + // GPIO25: PCIE_RST#_LAN, LOW active + // GPIO63: LAN_CLKREQ# + // GPIO197: LOM_POWER, HIGH Active + // Clock: GPP_CLK3 + // + // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + + // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 + + // + // APU GPP1: WUSB + // GPIO1: MPCIE_RST2#, LOW active + // GPIO13: WU_DISABLE#, LOW active + // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + // + // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD01/GPIO01 as GPO for MPCIE_RST2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // + // APU GPP2: WWAN + // GPIO0: MPCIE_RST1#, LOW active + // GPIO14: WP_DISABLE#, LOW active + // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + // + // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD00/GPIO00 as GPO for MPCIE_RST1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); + + // + // APU GPP3: 1394 + // GPIO59: Power control, HIGH active + // GPIO27: PCIE_RST#_1394, LOW active + // GPIO41: CLKREQ# + // Clock: GPP_CLK8 + // + // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# + + // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + // To fix glitch issue + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + // + // Enable/Disable OnBoard LAN + // + if (!CONFIG_ONBOARD_LAN) + { // 1 - DISABLED + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); + // } + + + // + // Enable/Disable 1394 + // + if (!CONFIG_ONBOARD_1394) + { // 1 - DISABLED + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); + // + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); + // } + + // + // external USB 3.0 control: + // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO26: PCIE_RST#_USB3.0 + // GPIO46: PCIE_USB30_CLKREQ# + // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + // Clock: GPP_CLK7 + // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { + // disable Onboard NEC USB3.0 controller + if (!CONFIG_ONBOARD_USB30) { + RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + } + // } + + // + // BlueTooth control: BT_ON + // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO07: BT_ON, 0 - OFF, 1 - ON + // + if (!CONFIG_ONBOARD_BLUETOOTH) { + //- if (SystemConfiguration.amdBlueTooth == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); + //- } + } + + // + // WebCam control: + // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + // + if (!CONFIG_ONBOARD_WEBCAM) { + //- if (SystemConfiguration.amdWebCam == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Travis enable: + // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + // + if (!CONFIG_ONBOARD_TRAVIS) { + //- if (SystemConfiguration.amdTravisCtrl == 0) { + RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Disable Light Sensor if needed + // + if (CONFIG_ONBOARD_LIGHTSENSOR) { + //- if (SystemConfiguration.amdLightSensor == 1) { + RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); + //- } + } + +} + + diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h new file mode 100644 index 0000000..c936e50 --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.h @@ -0,0 +1,2329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include +#include + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define Mmio_Address( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) + +#define Mmio32_Ptr( BaseAddr, Register ) \ + ( (volatile u32 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio32_G( BaseAddr, Register ) \ + *Mmio32_Ptr( BaseAddr, Register ) + +#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio32_G( BaseAddr, Register ) = \ +(u32) ( \ + ( Mmio32_G( BaseAddr, Register ) & \ + (u32)(AndData) \ + ) | \ + (u32)(OrData) \ + ) + +#define Mmio8_Ptr( BaseAddr, Register ) \ + ( (volatile u8 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio8_G( BaseAddr, Register ) \ + *Mmio8_Ptr( BaseAddr, Register ) + +#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio8_G( BaseAddr, Register ) = \ +(u8) ( \ + ( Mmio8_G( BaseAddr, Register ) & \ + (u8)(AndData) \ + ) | \ + (u8)(OrData) \ + ) + +#define SMIREG_EVENT_ENABLE 0x04 +#define SMIREG_SCITRIG 0x08 +#define SMIREG_SCILEVEL 0x0C +#define SMIREG_SMISCIEN 0x14 +#define SMIREG_SCIS0EN 0x20 +#define SMIREG_SCIMAP0 0x40 +#define SMIREG_SCIMAP1 0x44 +#define SMIREG_SCIMAP2 0x48 +#define SMIREG_SCIMAP3 0x4C +#define SMIREG_SCIMAP4 0x50 +#define SMIREG_SCIMAP5 0x54 +#define SMIREG_SCIMAP6 0x58 +#define SMIREG_SCIMAP7 0x5C +#define SMIREG_SCIMAP8 0x60 +#define SMIREG_SCIMAP9 0x64 +#define SMIREG_SCIMAP10 0x68 +#define SMIREG_SCIMAP11 0x6C +#define SMIREG_SCIMAP12 0x70 +#define SMIREG_SCIMAP13 0x74 +#define SMIREG_SCIMAP14 0x78 +#define SMIREG_SCIMAP15 0x7C +#define SMIREG_SMITRIG 0x98 +#define SMIREG_SMICONTROL0 0xA0 +#define SMIREG_SMICONTROL1 0xA4 + +#define FUNCTION0 0 +#define FUNCTION1 1 +#define FUNCTION2 2 +#define FUNCTION3 3 +#define NonGpio 0x80 // BIT7 + +// S0-domain General Purpose I/O: GPIO 00~67 +#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT +#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT +#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT +#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED +#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT +#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT +#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED +#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF +#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level +#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 +#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 +#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 +#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default +#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. +#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE +// 1:BATTERY IS FINE(DEFAULT) +// 0:BATTERY IS LOW +#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF +#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default +#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high +#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high +#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high +#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT +#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT +#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 +#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 +// 00 - REVA +// 01 - REVB +// 10 - REVC +// 11 - REVD +#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO +#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. +// 0:USB3.0 I/F in Express CARD +// 1:PCIE I/F in Express CARD detection +#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC +#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. +#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# +#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# +#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF +#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# +#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA +#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ +#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 +#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V +#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 +#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT +#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE +#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE +#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) +// 1:ENABLE; 0:DISABLE +// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 +#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN +#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER +#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER +#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE +#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# +#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 +#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 +#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# +#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 +#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM +#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default +#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +#define GPIO_68_SELECT FUNCTION0+NonGpio +#define GPIO_69_SELECT FUNCTION0+NonGpio +#define GPIO_70_SELECT FUNCTION0+NonGpio +#define GPIO_71_SELECT FUNCTION0+NonGpio +#define GPIO_72_SELECT FUNCTION0+NonGpio +#define GPIO_73_SELECT FUNCTION0+NonGpio +#define GPIO_74_SELECT FUNCTION0+NonGpio +#define GPIO_75_SELECT FUNCTION0+NonGpio +#define GPIO_76_SELECT FUNCTION0+NonGpio +#define GPIO_77_SELECT FUNCTION0+NonGpio +#define GPIO_78_SELECT FUNCTION0+NonGpio +#define GPIO_79_SELECT FUNCTION0+NonGpio +#define GPIO_80_SELECT FUNCTION0+NonGpio +#define GPIO_81_SELECT FUNCTION0+NonGpio +#define GPIO_82_SELECT FUNCTION0+NonGpio +#define GPIO_83_SELECT FUNCTION0+NonGpio +#define GPIO_84_SELECT FUNCTION0+NonGpio +#define GPIO_85_SELECT FUNCTION0+NonGpio +#define GPIO_86_SELECT FUNCTION0+NonGpio +#define GPIO_87_SELECT FUNCTION0+NonGpio +#define GPIO_88_SELECT FUNCTION0+NonGpio +#define GPIO_89_SELECT FUNCTION0+NonGpio +#define GPIO_90_SELECT FUNCTION0+NonGpio +#define GPIO_91_SELECT FUNCTION0+NonGpio +#define GPIO_92_SELECT FUNCTION0+NonGpio +#define GPIO_93_SELECT FUNCTION0+NonGpio +#define GPIO_94_SELECT FUNCTION0+NonGpio +#define GPIO_95_SELECT FUNCTION0+NonGpio +// GEVENT 00~23 are mapped to GPIO 96~119 +#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# +#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# +#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP +#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# +#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# +#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active +#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, +// there is a confliction to IR function when this pin is as a GEVENT. +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, +// special pin difination for SB700 VGA OUTPUT, high active, +// VGA power for Hudson-M2 will be down when it was asserted. +#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active +#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) +#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 +#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 +#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active +// [option for SPI_TPM_CS# in Hudson-M2 A12)] +#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & +// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time +#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, +// plus judge GPIO40 and GPIO19 level,low is assert. +// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) +// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) +#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active +#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, +// low active, when it's low, BIOS will enbale ODD_PWR +#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# +#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK +#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# +#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT +#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +#define GPIO_120_SELECT FUNCTION0+NonGpio +#define GPIO_121_SELECT FUNCTION0+NonGpio +#define GPIO_122_SELECT FUNCTION0+NonGpio +#define GPIO_123_SELECT FUNCTION0+NonGpio +#define GPIO_124_SELECT FUNCTION0+NonGpio +#define GPIO_125_SELECT FUNCTION0+NonGpio +#define GPIO_126_SELECT FUNCTION0+NonGpio +#define GPIO_127_SELECT FUNCTION0+NonGpio +#define GPIO_128_SELECT FUNCTION0+NonGpio +#define GPIO_129_SELECT FUNCTION0+NonGpio +#define GPIO_130_SELECT FUNCTION0+NonGpio +#define GPIO_131_SELECT FUNCTION0+NonGpio +#define GPIO_132_SELECT FUNCTION0+NonGpio +#define GPIO_133_SELECT FUNCTION0+NonGpio +#define GPIO_134_SELECT FUNCTION0+NonGpio +#define GPIO_135_SELECT FUNCTION0+NonGpio +#define GPIO_136_SELECT FUNCTION0+NonGpio +#define GPIO_137_SELECT FUNCTION0+NonGpio +#define GPIO_138_SELECT FUNCTION0+NonGpio +#define GPIO_139_SELECT FUNCTION0+NonGpio +#define GPIO_140_SELECT FUNCTION0+NonGpio +#define GPIO_141_SELECT FUNCTION0+NonGpio +#define GPIO_142_SELECT FUNCTION0+NonGpio +#define GPIO_143_SELECT FUNCTION0+NonGpio +#define GPIO_144_SELECT FUNCTION0+NonGpio +#define GPIO_145_SELECT FUNCTION0+NonGpio +#define GPIO_146_SELECT FUNCTION0+NonGpio +#define GPIO_147_SELECT FUNCTION0+NonGpio +#define GPIO_148_SELECT FUNCTION0+NonGpio +#define GPIO_149_SELECT FUNCTION0+NonGpio +#define GPIO_150_SELECT FUNCTION0+NonGpio +#define GPIO_151_SELECT FUNCTION0+NonGpio +#define GPIO_152_SELECT FUNCTION0+NonGpio +#define GPIO_153_SELECT FUNCTION0+NonGpio +#define GPIO_154_SELECT FUNCTION0+NonGpio +#define GPIO_155_SELECT FUNCTION0+NonGpio +#define GPIO_156_SELECT FUNCTION0+NonGpio +#define GPIO_157_SELECT FUNCTION0+NonGpio +#define GPIO_158_SELECT FUNCTION0+NonGpio +#define GPIO_159_SELECT FUNCTION0+NonGpio +#define GPIO_160_SELECT FUNCTION0+NonGpio + +// S5-domain General Purpose I/O +#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# +#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 +#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 +#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 +#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 +#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. +#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, +#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE +#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 +#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# +#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 +#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 +#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO +#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR +#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 +#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 +#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# +#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE +#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE +// option for HDMI CEC signal OW ACTIVE +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA +#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK +#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active +// RESERVED FOR LCD BACKLIGHT PWM +#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL +#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM +#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF +#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD + +#define TYPE_GPI (1<<5) +#define TYPE_GPO (0<<5) + +#define GPIO_00_TYPE TYPE_GPO +#define GPIO_01_TYPE TYPE_GPO +#define GPIO_02_TYPE TYPE_GPO +#define GPIO_03_TYPE TYPE_GPO +#define GPIO_04_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO +#define GPIO_06_TYPE TYPE_GPO +#define GPIO_07_TYPE TYPE_GPO +#define GPIO_08_TYPE TYPE_GPO +#define GPIO_09_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI +#define GPIO_11_TYPE TYPE_GPO +#define GPIO_12_TYPE TYPE_GPO +#define GPIO_13_TYPE TYPE_GPO +#define GPIO_14_TYPE TYPE_GPO +#define GPIO_15_TYPE TYPE_GPO +#define GPIO_16_TYPE TYPE_GPO +#define GPIO_17_TYPE TYPE_GPO +#define GPIO_18_TYPE TYPE_GPO +#define GPIO_19_TYPE TYPE_GPO +#define GPIO_20_TYPE TYPE_GPO +#define GPIO_21_TYPE TYPE_GPO +#define GPIO_22_TYPE TYPE_GPO +#define GPIO_23_TYPE TYPE_GPO +#define GPIO_24_TYPE TYPE_GPO +#define GPIO_25_TYPE TYPE_GPO +#define GPIO_26_TYPE TYPE_GPO +#define GPIO_27_TYPE TYPE_GPO +#define GPIO_28_TYPE TYPE_GPI +#define GPIO_29_TYPE TYPE_GPO +#define GPIO_30_TYPE TYPE_GPI +#define GPIO_31_TYPE TYPE_GPI +#define GPIO_32_TYPE TYPE_GPO +#define GPIO_33_TYPE TYPE_GPI +#define GPIO_34_TYPE TYPE_GPO +#define GPIO_35_TYPE TYPE_GPO +#define GPIO_36_TYPE TYPE_GPO +#define GPIO_37_TYPE TYPE_GPO +#define GPIO_38_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO +#define GPIO_40_TYPE TYPE_GPO +#define GPIO_41_TYPE TYPE_GPI +#define GPIO_42_TYPE TYPE_GPI +#define GPIO_43_TYPE TYPE_GPO +#define GPIO_44_TYPE TYPE_GPO +#define GPIO_45_TYPE TYPE_GPO +#define GPIO_46_TYPE TYPE_GPI +#define GPIO_47_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO +#define GPIO_50_TYPE TYPE_GPO +#define GPIO_51_TYPE TYPE_GPO +#define GPIO_52_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO +#define GPIO_56_TYPE TYPE_GPI +#define GPIO_57_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO +#define GPIO_59_TYPE TYPE_GPO +#define GPIO_60_TYPE TYPE_GPI +#define GPIO_61_TYPE TYPE_GPI +#define GPIO_62_TYPE TYPE_GPI +#define GPIO_63_TYPE TYPE_GPI +#define GPIO_64_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI +#define GPIO_66_TYPE TYPE_GPO +#define GPIO_67_TYPE TYPE_GPO +#define GPIO_68_TYPE TYPE_GPO +#define GPIO_69_TYPE TYPE_GPO +#define GPIO_70_TYPE TYPE_GPO +#define GPIO_71_TYPE TYPE_GPO +#define GPIO_72_TYPE TYPE_GPO +#define GPIO_73_TYPE TYPE_GPO +#define GPIO_74_TYPE TYPE_GPO +#define GPIO_75_TYPE TYPE_GPO +#define GPIO_76_TYPE TYPE_GPO +#define GPIO_77_TYPE TYPE_GPO +#define GPIO_78_TYPE TYPE_GPO +#define GPIO_79_TYPE TYPE_GPO +#define GPIO_80_TYPE TYPE_GPO +#define GPIO_81_TYPE TYPE_GPO +#define GPIO_82_TYPE TYPE_GPO +#define GPIO_83_TYPE TYPE_GPO +#define GPIO_84_TYPE TYPE_GPO +#define GPIO_85_TYPE TYPE_GPO +#define GPIO_86_TYPE TYPE_GPO +#define GPIO_87_TYPE TYPE_GPO +#define GPIO_88_TYPE TYPE_GPO +#define GPIO_89_TYPE TYPE_GPO +#define GPIO_90_TYPE TYPE_GPO +#define GPIO_91_TYPE TYPE_GPO +#define GPIO_92_TYPE TYPE_GPO +#define GPIO_93_TYPE TYPE_GPO +#define GPIO_94_TYPE TYPE_GPO +#define GPIO_95_TYPE TYPE_GPO + +// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +#define GPIO_96_TYPE TYPE_GPI +#define GPIO_97_TYPE TYPE_GPI +#define GPIO_98_TYPE TYPE_GPI +#define GPIO_99_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI +#define GPIO_101_TYPE TYPE_GPI +#define GPIO_102_TYPE TYPE_GPO +#define GPIO_103_TYPE TYPE_GPO +#define GPIO_104_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI +#define GPIO_106_TYPE TYPE_GPO +#define GPIO_107_TYPE TYPE_GPI +#define GPIO_108_TYPE TYPE_GPI +#define GPIO_109_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI +#define GPIO_111_TYPE TYPE_GPI +#define GPIO_112_TYPE TYPE_GPI +#define GPIO_113_TYPE TYPE_GPI +#define GPIO_114_TYPE TYPE_GPO +#define GPIO_115_TYPE TYPE_GPI +#define GPIO_116_TYPE TYPE_GPI +#define GPIO_117_TYPE TYPE_GPI +#define GPIO_118_TYPE TYPE_GPI +#define GPIO_119_TYPE TYPE_GPI + +#define GPIO_120_TYPE TYPE_GPO +#define GPIO_121_TYPE TYPE_GPO +#define GPIO_122_TYPE TYPE_GPO +#define GPIO_123_TYPE TYPE_GPO +#define GPIO_124_TYPE TYPE_GPO +#define GPIO_125_TYPE TYPE_GPO +#define GPIO_126_TYPE TYPE_GPO +#define GPIO_127_TYPE TYPE_GPO +#define GPIO_128_TYPE TYPE_GPO +#define GPIO_129_TYPE TYPE_GPO +#define GPIO_130_TYPE TYPE_GPO +#define GPIO_131_TYPE TYPE_GPO +#define GPIO_132_TYPE TYPE_GPO +#define GPIO_133_TYPE TYPE_GPO +#define GPIO_134_TYPE TYPE_GPO +#define GPIO_135_TYPE TYPE_GPO +#define GPIO_136_TYPE TYPE_GPO +#define GPIO_137_TYPE TYPE_GPO +#define GPIO_138_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO +#define GPIO_140_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO +#define GPIO_142_TYPE TYPE_GPO +#define GPIO_143_TYPE TYPE_GPO +#define GPIO_144_TYPE TYPE_GPO +#define GPIO_145_TYPE TYPE_GPO +#define GPIO_146_TYPE TYPE_GPO +#define GPIO_147_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO +#define GPIO_150_TYPE TYPE_GPO +#define GPIO_151_TYPE TYPE_GPO +#define GPIO_152_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO +#define GPIO_156_TYPE TYPE_GPO +#define GPIO_157_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO +#define GPIO_159_TYPE TYPE_GPO +#define GPIO_160_TYPE TYPE_GPO +#define GPIO_161_TYPE TYPE_GPO +#define GPIO_162_TYPE TYPE_GPO +#define GPIO_163_TYPE TYPE_GPO +#define GPIO_164_TYPE TYPE_GPI +#define GPIO_165_TYPE TYPE_GPO +#define GPIO_166_TYPE TYPE_GPI +#define GPIO_167_TYPE TYPE_GPI +#define GPIO_168_TYPE TYPE_GPI +#define GPIO_169_TYPE TYPE_GPI +#define GPIO_170_TYPE TYPE_GPO +#define GPIO_171_TYPE TYPE_GPI +#define GPIO_172_TYPE TYPE_GPO +#define GPIO_173_TYPE TYPE_GPI +#define GPIO_174_TYPE TYPE_GPI +#define GPIO_175_TYPE TYPE_GPO +#define GPIO_176_TYPE TYPE_GPO +#define GPIO_177_TYPE TYPE_GPO +#define GPIO_178_TYPE TYPE_GPO +#define GPIO_179_TYPE TYPE_GPO +#define GPIO_180_TYPE TYPE_GPO +#define GPIO_181_TYPE TYPE_GPO +#define GPIO_182_TYPE TYPE_GPO +#define GPIO_183_TYPE TYPE_GPO +#define GPIO_184_TYPE TYPE_GPI +#define GPIO_185_TYPE TYPE_GPO +#define GPIO_186_TYPE TYPE_GPO +#define GPIO_187_TYPE TYPE_GPO +#define GPIO_188_TYPE TYPE_GPO +#define GPIO_189_TYPE TYPE_GPI +#define GPIO_190_TYPE TYPE_GPI +#define GPIO_191_TYPE TYPE_GPO +#define GPIO_192_TYPE TYPE_GPO +#define GPIO_193_TYPE TYPE_GPO +#define GPIO_194_TYPE TYPE_GPO +#define GPIO_195_TYPE TYPE_GPO +#define GPIO_196_TYPE TYPE_GPO +#define GPIO_197_TYPE TYPE_GPO +#define GPIO_198_TYPE TYPE_GPO +#define GPIO_199_TYPE TYPE_GPI +#define GPIO_200_TYPE TYPE_GPO +#define GPIO_201_TYPE TYPE_GPI +#define GPIO_202_TYPE TYPE_GPI +#define GPIO_203_TYPE TYPE_GPI +#define GPIO_204_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI +#define GPIO_206_TYPE TYPE_GPI +#define GPIO_207_TYPE TYPE_GPI +#define GPIO_208_TYPE TYPE_GPI +#define GPIO_209_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO +#define GPIO_211_TYPE TYPE_GPO +#define GPIO_212_TYPE TYPE_GPO +#define GPIO_213_TYPE TYPE_GPO +#define GPIO_214_TYPE TYPE_GPO +#define GPIO_215_TYPE TYPE_GPO +#define GPIO_216_TYPE TYPE_GPO +#define GPIO_217_TYPE TYPE_GPO +#define GPIO_218_TYPE TYPE_GPO +#define GPIO_219_TYPE TYPE_GPO +#define GPIO_220_TYPE TYPE_GPO +#define GPIO_221_TYPE TYPE_GPO +#define GPIO_222_TYPE TYPE_GPO +#define GPIO_223_TYPE TYPE_GPO +#define GPIO_224_TYPE TYPE_GPO +#define GPIO_225_TYPE TYPE_GPO +#define GPIO_226_TYPE TYPE_GPO +#define GPIO_227_TYPE TYPE_GPO +#define GPIO_228_TYPE TYPE_GPO +#define GPIO_229_TYPE TYPE_GPO + +#define GPO_LOW (0<<6) +#define GPO_HI (1<<6) + +#define GPO_00_LEVEL GPO_HI +#define GPO_01_LEVEL GPO_HI +#define GPO_02_LEVEL GPO_HI +#define GPO_03_LEVEL GPO_HI +#define GPO_04_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI +#define GPO_06_LEVEL GPO_HI +#define GPO_07_LEVEL GPO_HI +#define GPO_08_LEVEL GPO_HI +#define GPO_09_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW +#define GPO_11_LEVEL GPO_HI +#define GPO_12_LEVEL GPO_HI +#define GPO_13_LEVEL GPO_HI +#define GPO_14_LEVEL GPO_HI +#define GPO_15_LEVEL GPO_HI +#define GPO_16_LEVEL GPO_HI +#define GPO_17_LEVEL GPO_HI +#define GPO_18_LEVEL GPO_HI +#define GPO_19_LEVEL GPO_LOW +#define GPO_20_LEVEL GPO_LOW +#define GPO_21_LEVEL GPO_LOW +#define GPO_22_LEVEL GPO_HI +#define GPO_23_LEVEL GPO_HI +#define GPO_24_LEVEL GPO_HI +#define GPO_25_LEVEL GPO_HI +#define GPO_26_LEVEL GPO_HI +#define GPO_27_LEVEL GPO_HI +#define GPO_28_LEVEL GPO_LOW +#define GPO_29_LEVEL GPO_HI +#define GPO_30_LEVEL GPO_LOW +#define GPO_31_LEVEL GPO_LOW +#define GPO_32_LEVEL GPO_HI +#define GPO_33_LEVEL GPO_LOW +#define GPO_34_LEVEL GPO_LOW +#define GPO_35_LEVEL GPO_LOW +#define GPO_36_LEVEL GPO_LOW +#define GPO_37_LEVEL GPO_HI +#define GPO_38_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI +#define GPO_40_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW +#define GPO_42_LEVEL GPO_LOW +#define GPO_43_LEVEL GPO_LOW +#define GPO_44_LEVEL GPO_HI +#define GPO_45_LEVEL GPO_HI +#define GPO_46_LEVEL GPO_LOW +#define GPO_47_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW +#define GPO_49_LEVEL GPO_HI +#define GPO_50_LEVEL GPO_HI +#define GPO_51_LEVEL GPO_LOW +#define GPO_52_LEVEL GPO_HI +#define GPO_53_LEVEL GPO_HI +#define GPO_54_LEVEL GPO_LOW +#define GPO_55_LEVEL GPO_LOW +#define GPO_56_LEVEL GPO_LOW +#define GPO_57_LEVEL GPO_HI +#define GPO_58_LEVEL GPO_HI +#define GPO_59_LEVEL GPO_HI +#define GPO_60_LEVEL GPO_LOW +#define GPO_61_LEVEL GPO_LOW +#define GPO_62_LEVEL GPO_LOW +#define GPO_63_LEVEL GPO_LOW +#define GPO_64_LEVEL GPO_LOW +#define GPO_65_LEVEL GPO_LOW +#define GPO_66_LEVEL GPO_LOW +#define GPO_67_LEVEL GPO_LOW +#define GPO_68_LEVEL GPO_LOW +#define GPO_69_LEVEL GPO_LOW +#define GPO_70_LEVEL GPO_LOW +#define GPO_71_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW +#define GPO_73_LEVEL GPO_LOW +#define GPO_74_LEVEL GPO_LOW +#define GPO_75_LEVEL GPO_LOW +#define GPO_76_LEVEL GPO_LOW +#define GPO_77_LEVEL GPO_LOW +#define GPO_78_LEVEL GPO_LOW +#define GPO_79_LEVEL GPO_LOW +#define GPO_80_LEVEL GPO_LOW +#define GPO_81_LEVEL GPO_LOW +#define GPO_82_LEVEL GPO_LOW +#define GPO_83_LEVEL GPO_LOW +#define GPO_84_LEVEL GPO_LOW +#define GPO_85_LEVEL GPO_LOW +#define GPO_86_LEVEL GPO_LOW +#define GPO_87_LEVEL GPO_LOW +#define GPO_88_LEVEL GPO_LOW +#define GPO_89_LEVEL GPO_LOW +#define GPO_90_LEVEL GPO_LOW +#define GPO_91_LEVEL GPO_LOW +#define GPO_92_LEVEL GPO_LOW +#define GPO_93_LEVEL GPO_LOW +#define GPO_94_LEVEL GPO_LOW +#define GPO_95_LEVEL GPO_LOW +#define GPO_96_LEVEL GPO_LOW +#define GPO_97_LEVEL GPO_LOW +#define GPO_98_LEVEL GPO_LOW +#define GPO_99_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW +#define GPO_101_LEVEL GPO_LOW +#define GPO_102_LEVEL GPO_LOW +#define GPO_103_LEVEL GPO_LOW +#define GPO_104_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW +#define GPO_106_LEVEL GPO_LOW +#define GPO_107_LEVEL GPO_LOW +#define GPO_108_LEVEL GPO_HI +#define GPO_109_LEVEL GPO_LOW +#define GPO_110_LEVEL GPO_HI +#define GPO_111_LEVEL GPO_HI +#define GPO_112_LEVEL GPO_HI +#define GPO_113_LEVEL GPO_LOW +#define GPO_114_LEVEL GPO_LOW +#define GPO_115_LEVEL GPO_LOW +#define GPO_116_LEVEL GPO_LOW +#define GPO_117_LEVEL GPO_LOW +#define GPO_118_LEVEL GPO_LOW +#define GPO_119_LEVEL GPO_LOW +#define GPO_120_LEVEL GPO_LOW +#define GPO_121_LEVEL GPO_LOW +#define GPO_122_LEVEL GPO_LOW +#define GPO_123_LEVEL GPO_LOW +#define GPO_124_LEVEL GPO_LOW +#define GPO_125_LEVEL GPO_LOW +#define GPO_126_LEVEL GPO_LOW +#define GPO_127_LEVEL GPO_LOW +#define GPO_128_LEVEL GPO_LOW +#define GPO_129_LEVEL GPO_LOW +#define GPO_130_LEVEL GPO_LOW +#define GPO_131_LEVEL GPO_LOW +#define GPO_132_LEVEL GPO_LOW +#define GPO_133_LEVEL GPO_LOW +#define GPO_134_LEVEL GPO_LOW +#define GPO_135_LEVEL GPO_LOW +#define GPO_136_LEVEL GPO_LOW +#define GPO_137_LEVEL GPO_LOW +#define GPO_138_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW +#define GPO_140_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW +#define GPO_142_LEVEL GPO_LOW +#define GPO_143_LEVEL GPO_LOW +#define GPO_144_LEVEL GPO_LOW +#define GPO_145_LEVEL GPO_LOW +#define GPO_146_LEVEL GPO_LOW +#define GPO_147_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW +#define GPO_149_LEVEL GPO_LOW +#define GPO_150_LEVEL GPO_LOW +#define GPO_151_LEVEL GPO_LOW +#define GPO_152_LEVEL GPO_LOW +#define GPO_153_LEVEL GPO_LOW +#define GPO_154_LEVEL GPO_LOW +#define GPO_155_LEVEL GPO_LOW +#define GPO_156_LEVEL GPO_LOW +#define GPO_157_LEVEL GPO_LOW +#define GPO_158_LEVEL GPO_LOW +#define GPO_159_LEVEL GPO_LOW +#define GPO_160_LEVEL GPO_LOW +#define GPO_161_LEVEL GPO_LOW +#define GPO_162_LEVEL GPO_LOW +#define GPO_163_LEVEL GPO_LOW +#define GPO_164_LEVEL GPO_LOW +#define GPO_165_LEVEL GPO_LOW +#define GPO_166_LEVEL GPO_LOW +#define GPO_167_LEVEL GPO_LOW +#define GPO_168_LEVEL GPO_LOW +#define GPO_169_LEVEL GPO_LOW +#define GPO_170_LEVEL GPO_HI +#define GPO_171_LEVEL GPO_LOW +#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_173_LEVEL GPO_LOW +#define GPO_174_LEVEL GPO_LOW +#define GPO_175_LEVEL GPO_LOW +#define GPO_176_LEVEL GPO_LOW +#define GPO_177_LEVEL GPO_LOW +#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_179_LEVEL GPO_HI +#define GPO_180_LEVEL GPO_HI +#define GPO_181_LEVEL GPO_LOW +#define GPO_182_LEVEL GPO_HI +#define GPO_183_LEVEL GPO_LOW +#define GPO_184_LEVEL GPO_LOW +#define GPO_185_LEVEL GPO_LOW +#define GPO_186_LEVEL GPO_LOW +#define GPO_187_LEVEL GPO_LOW +#define GPO_188_LEVEL GPO_LOW +#define GPO_189_LEVEL GPO_LOW +#define GPO_190_LEVEL GPO_LOW +#define GPO_191_LEVEL GPO_LOW +#define GPO_192_LEVEL GPO_LOW +#define GPO_193_LEVEL GPO_LOW +#define GPO_194_LEVEL GPO_LOW +#define GPO_195_LEVEL GPO_LOW +#define GPO_196_LEVEL GPO_LOW +#define GPO_197_LEVEL GPO_LOW +#define GPO_198_LEVEL GPO_LOW +#define GPO_199_LEVEL GPO_LOW +#define GPO_200_LEVEL GPO_HI +#define GPO_201_LEVEL GPO_LOW +#define GPO_202_LEVEL GPO_LOW +#define GPO_203_LEVEL GPO_LOW +#define GPO_204_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW +#define GPO_206_LEVEL GPO_LOW +#define GPO_207_LEVEL GPO_LOW +#define GPO_208_LEVEL GPO_LOW +#define GPO_209_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW +#define GPO_211_LEVEL GPO_LOW +#define GPO_212_LEVEL GPO_LOW +#define GPO_213_LEVEL GPO_LOW +#define GPO_214_LEVEL GPO_LOW +#define GPO_215_LEVEL GPO_LOW +#define GPO_216_LEVEL GPO_LOW +#define GPO_217_LEVEL GPO_LOW +#define GPO_218_LEVEL GPO_LOW +#define GPO_219_LEVEL GPO_LOW +#define GPO_220_LEVEL GPO_LOW +#define GPO_221_LEVEL GPO_LOW +#define GPO_222_LEVEL GPO_LOW +#define GPO_223_LEVEL GPO_LOW +#define GPO_224_LEVEL GPO_LOW +#define GPO_225_LEVEL GPO_LOW +#define GPO_226_LEVEL GPO_LOW +#define GPO_227_LEVEL GPO_LOW +#define GPO_228_LEVEL GPO_LOW +#define GPO_229_LEVEL GPO_LOW + +#define GPIO_NONSTICKY (0<<2) +#define GPIO_STICKY (1<<2) + +#define GPIO_00_STICKY GPIO_NONSTICKY +#define GPIO_01_STICKY GPIO_NONSTICKY +#define GPIO_02_STICKY GPIO_NONSTICKY +#define GPIO_03_STICKY GPIO_NONSTICKY +#define GPIO_04_STICKY GPIO_NONSTICKY +#define GPIO_05_STICKY GPIO_NONSTICKY +#define GPIO_06_STICKY GPIO_NONSTICKY +#define GPIO_07_STICKY GPIO_NONSTICKY +#define GPIO_08_STICKY GPIO_NONSTICKY +#define GPIO_09_STICKY GPIO_NONSTICKY +#define GPIO_10_STICKY GPIO_NONSTICKY +#define GPIO_11_STICKY GPIO_NONSTICKY +#define GPIO_12_STICKY GPIO_NONSTICKY +#define GPIO_13_STICKY GPIO_NONSTICKY +#define GPIO_14_STICKY GPIO_NONSTICKY +#define GPIO_15_STICKY GPIO_NONSTICKY +#define GPIO_16_STICKY GPIO_NONSTICKY +#define GPIO_17_STICKY GPIO_STICKY +#define GPIO_18_STICKY GPIO_NONSTICKY +#define GPIO_19_STICKY GPIO_NONSTICKY +#define GPIO_20_STICKY GPIO_NONSTICKY +#define GPIO_21_STICKY GPIO_NONSTICKY +#define GPIO_22_STICKY GPIO_NONSTICKY +#define GPIO_23_STICKY GPIO_NONSTICKY +#define GPIO_24_STICKY GPIO_NONSTICKY +#define GPIO_25_STICKY GPIO_NONSTICKY +#define GPIO_26_STICKY GPIO_NONSTICKY +#define GPIO_27_STICKY GPIO_NONSTICKY +#define GPIO_28_STICKY GPIO_NONSTICKY +#define GPIO_29_STICKY GPIO_NONSTICKY +#define GPIO_30_STICKY GPIO_NONSTICKY +#define GPIO_31_STICKY GPIO_NONSTICKY +#define GPIO_32_STICKY GPIO_NONSTICKY +#define GPIO_33_STICKY GPIO_NONSTICKY +#define GPIO_34_STICKY GPIO_NONSTICKY +#define GPIO_35_STICKY GPIO_NONSTICKY +#define GPIO_36_STICKY GPIO_NONSTICKY +#define GPIO_37_STICKY GPIO_NONSTICKY +#define GPIO_38_STICKY GPIO_NONSTICKY +#define GPIO_39_STICKY GPIO_NONSTICKY +#define GPIO_40_STICKY GPIO_NONSTICKY +#define GPIO_41_STICKY GPIO_NONSTICKY +#define GPIO_42_STICKY GPIO_NONSTICKY +#define GPIO_43_STICKY GPIO_NONSTICKY +#define GPIO_44_STICKY GPIO_NONSTICKY +#define GPIO_45_STICKY GPIO_NONSTICKY +#define GPIO_46_STICKY GPIO_NONSTICKY +#define GPIO_47_STICKY GPIO_NONSTICKY +#define GPIO_48_STICKY GPIO_NONSTICKY +#define GPIO_49_STICKY GPIO_NONSTICKY +#define GPIO_50_STICKY GPIO_NONSTICKY +#define GPIO_51_STICKY GPIO_NONSTICKY +#define GPIO_52_STICKY GPIO_NONSTICKY +#define GPIO_53_STICKY GPIO_NONSTICKY +#define GPIO_54_STICKY GPIO_NONSTICKY +#define GPIO_55_STICKY GPIO_NONSTICKY +#define GPIO_56_STICKY GPIO_NONSTICKY +#define GPIO_57_STICKY GPIO_NONSTICKY +#define GPIO_58_STICKY GPIO_NONSTICKY +#define GPIO_59_STICKY GPIO_NONSTICKY +#define GPIO_60_STICKY GPIO_NONSTICKY +#define GPIO_61_STICKY GPIO_NONSTICKY +#define GPIO_62_STICKY GPIO_NONSTICKY +#define GPIO_63_STICKY GPIO_NONSTICKY +#define GPIO_64_STICKY GPIO_NONSTICKY +#define GPIO_65_STICKY GPIO_NONSTICKY +#define GPIO_66_STICKY GPIO_NONSTICKY +#define GPIO_67_STICKY GPIO_NONSTICKY +#define GPIO_68_STICKY GPIO_NONSTICKY +#define GPIO_69_STICKY GPIO_NONSTICKY +#define GPIO_70_STICKY GPIO_NONSTICKY +#define GPIO_71_STICKY GPIO_NONSTICKY +#define GPIO_72_STICKY GPIO_NONSTICKY +#define GPIO_73_STICKY GPIO_NONSTICKY +#define GPIO_74_STICKY GPIO_NONSTICKY +#define GPIO_75_STICKY GPIO_NONSTICKY +#define GPIO_76_STICKY GPIO_NONSTICKY +#define GPIO_77_STICKY GPIO_NONSTICKY +#define GPIO_78_STICKY GPIO_NONSTICKY +#define GPIO_79_STICKY GPIO_NONSTICKY +#define GPIO_80_STICKY GPIO_NONSTICKY +#define GPIO_81_STICKY GPIO_NONSTICKY +#define GPIO_82_STICKY GPIO_NONSTICKY +#define GPIO_83_STICKY GPIO_NONSTICKY +#define GPIO_84_STICKY GPIO_NONSTICKY +#define GPIO_85_STICKY GPIO_NONSTICKY +#define GPIO_86_STICKY GPIO_NONSTICKY +#define GPIO_87_STICKY GPIO_NONSTICKY +#define GPIO_88_STICKY GPIO_NONSTICKY +#define GPIO_89_STICKY GPIO_NONSTICKY +#define GPIO_90_STICKY GPIO_NONSTICKY +#define GPIO_91_STICKY GPIO_NONSTICKY +#define GPIO_92_STICKY GPIO_NONSTICKY +#define GPIO_93_STICKY GPIO_NONSTICKY +#define GPIO_94_STICKY GPIO_NONSTICKY +#define GPIO_95_STICKY GPIO_NONSTICKY +#define GPIO_96_STICKY GPIO_NONSTICKY +#define GPIO_97_STICKY GPIO_NONSTICKY +#define GPIO_98_STICKY GPIO_NONSTICKY +#define GPIO_99_STICKY GPIO_NONSTICKY +#define GPIO_100_STICKY GPIO_NONSTICKY +#define GPIO_101_STICKY GPIO_NONSTICKY +#define GPIO_102_STICKY GPIO_STICKY +#define GPIO_103_STICKY GPIO_STICKY +#define GPIO_104_STICKY GPIO_NONSTICKY +#define GPIO_105_STICKY GPIO_NONSTICKY +#define GPIO_106_STICKY GPIO_NONSTICKY +#define GPIO_107_STICKY GPIO_NONSTICKY +#define GPIO_108_STICKY GPIO_STICKY +#define GPIO_109_STICKY GPIO_NONSTICKY +#define GPIO_110_STICKY GPIO_NONSTICKY +#define GPIO_111_STICKY GPIO_NONSTICKY +#define GPIO_112_STICKY GPIO_NONSTICKY +#define GPIO_113_STICKY GPIO_NONSTICKY +#define GPIO_114_STICKY GPIO_NONSTICKY +#define GPIO_115_STICKY GPIO_NONSTICKY +#define GPIO_116_STICKY GPIO_NONSTICKY +#define GPIO_117_STICKY GPIO_NONSTICKY +#define GPIO_118_STICKY GPIO_NONSTICKY +#define GPIO_119_STICKY GPIO_NONSTICKY +#define GPIO_120_STICKY GPIO_NONSTICKY +#define GPIO_121_STICKY GPIO_NONSTICKY +#define GPIO_122_STICKY GPIO_NONSTICKY +#define GPIO_123_STICKY GPIO_NONSTICKY +#define GPIO_124_STICKY GPIO_NONSTICKY +#define GPIO_125_STICKY GPIO_NONSTICKY +#define GPIO_126_STICKY GPIO_NONSTICKY +#define GPIO_127_STICKY GPIO_NONSTICKY +#define GPIO_128_STICKY GPIO_NONSTICKY +#define GPIO_129_STICKY GPIO_NONSTICKY +#define GPIO_130_STICKY GPIO_NONSTICKY +#define GPIO_131_STICKY GPIO_NONSTICKY +#define GPIO_132_STICKY GPIO_NONSTICKY +#define GPIO_133_STICKY GPIO_NONSTICKY +#define GPIO_134_STICKY GPIO_NONSTICKY +#define GPIO_135_STICKY GPIO_NONSTICKY +#define GPIO_136_STICKY GPIO_NONSTICKY +#define GPIO_137_STICKY GPIO_NONSTICKY +#define GPIO_138_STICKY GPIO_NONSTICKY +#define GPIO_139_STICKY GPIO_NONSTICKY +#define GPIO_140_STICKY GPIO_NONSTICKY +#define GPIO_141_STICKY GPIO_NONSTICKY +#define GPIO_142_STICKY GPIO_NONSTICKY +#define GPIO_143_STICKY GPIO_NONSTICKY +#define GPIO_144_STICKY GPIO_NONSTICKY +#define GPIO_145_STICKY GPIO_NONSTICKY +#define GPIO_146_STICKY GPIO_NONSTICKY +#define GPIO_147_STICKY GPIO_NONSTICKY +#define GPIO_148_STICKY GPIO_NONSTICKY +#define GPIO_149_STICKY GPIO_NONSTICKY +#define GPIO_150_STICKY GPIO_NONSTICKY +#define GPIO_151_STICKY GPIO_NONSTICKY +#define GPIO_152_STICKY GPIO_NONSTICKY +#define GPIO_153_STICKY GPIO_NONSTICKY +#define GPIO_154_STICKY GPIO_NONSTICKY +#define GPIO_155_STICKY GPIO_NONSTICKY +#define GPIO_156_STICKY GPIO_NONSTICKY +#define GPIO_157_STICKY GPIO_NONSTICKY +#define GPIO_158_STICKY GPIO_NONSTICKY +#define GPIO_159_STICKY GPIO_NONSTICKY +#define GPIO_160_STICKY GPIO_NONSTICKY +#define GPIO_161_STICKY GPIO_NONSTICKY +#define GPIO_162_STICKY GPIO_NONSTICKY +#define GPIO_163_STICKY GPIO_NONSTICKY +#define GPIO_164_STICKY GPIO_NONSTICKY +#define GPIO_165_STICKY GPIO_NONSTICKY +#define GPIO_166_STICKY GPIO_NONSTICKY +#define GPIO_167_STICKY GPIO_NONSTICKY +#define GPIO_168_STICKY GPIO_NONSTICKY +#define GPIO_169_STICKY GPIO_NONSTICKY +#define GPIO_170_STICKY GPIO_STICKY +#define GPIO_171_STICKY GPIO_NONSTICKY +#define GPIO_172_STICKY GPIO_STICKY +#define GPIO_173_STICKY GPIO_NONSTICKY +#define GPIO_174_STICKY GPIO_NONSTICKY +#define GPIO_175_STICKY GPIO_NONSTICKY +#define GPIO_176_STICKY GPIO_NONSTICKY +#define GPIO_177_STICKY GPIO_NONSTICKY +#define GPIO_178_STICKY GPIO_NONSTICKY +#define GPIO_179_STICKY GPIO_NONSTICKY +#define GPIO_180_STICKY GPIO_NONSTICKY +#define GPIO_181_STICKY GPIO_NONSTICKY +#define GPIO_182_STICKY GPIO_NONSTICKY +#define GPIO_183_STICKY GPIO_NONSTICKY +#define GPIO_184_STICKY GPIO_NONSTICKY +#define GPIO_185_STICKY GPIO_NONSTICKY +#define GPIO_186_STICKY GPIO_NONSTICKY +#define GPIO_187_STICKY GPIO_NONSTICKY +#define GPIO_188_STICKY GPIO_NONSTICKY +#define GPIO_189_STICKY GPIO_NONSTICKY +#define GPIO_190_STICKY GPIO_NONSTICKY +#define GPIO_191_STICKY GPIO_NONSTICKY +#define GPIO_192_STICKY GPIO_NONSTICKY +#define GPIO_193_STICKY GPIO_NONSTICKY +#define GPIO_194_STICKY GPIO_NONSTICKY +#define GPIO_195_STICKY GPIO_NONSTICKY +#define GPIO_196_STICKY GPIO_NONSTICKY +#define GPIO_197_STICKY GPIO_NONSTICKY +#define GPIO_198_STICKY GPIO_NONSTICKY +#define GPIO_199_STICKY GPIO_NONSTICKY +#define GPIO_200_STICKY GPIO_NONSTICKY +#define GPIO_201_STICKY GPIO_NONSTICKY +#define GPIO_202_STICKY GPIO_NONSTICKY +#define GPIO_203_STICKY GPIO_NONSTICKY +#define GPIO_204_STICKY GPIO_NONSTICKY +#define GPIO_205_STICKY GPIO_NONSTICKY +#define GPIO_206_STICKY GPIO_NONSTICKY +#define GPIO_207_STICKY GPIO_NONSTICKY +#define GPIO_208_STICKY GPIO_NONSTICKY +#define GPIO_209_STICKY GPIO_NONSTICKY +#define GPIO_210_STICKY GPIO_NONSTICKY +#define GPIO_211_STICKY GPIO_NONSTICKY +#define GPIO_212_STICKY GPIO_NONSTICKY +#define GPIO_213_STICKY GPIO_NONSTICKY +#define GPIO_214_STICKY GPIO_NONSTICKY +#define GPIO_215_STICKY GPIO_NONSTICKY +#define GPIO_216_STICKY GPIO_NONSTICKY +#define GPIO_217_STICKY GPIO_NONSTICKY +#define GPIO_218_STICKY GPIO_NONSTICKY +#define GPIO_219_STICKY GPIO_NONSTICKY +#define GPIO_220_STICKY GPIO_NONSTICKY +#define GPIO_221_STICKY GPIO_NONSTICKY +#define GPIO_222_STICKY GPIO_NONSTICKY +#define GPIO_223_STICKY GPIO_NONSTICKY +#define GPIO_224_STICKY GPIO_NONSTICKY +#define GPIO_225_STICKY GPIO_NONSTICKY +#define GPIO_226_STICKY GPIO_NONSTICKY +#define GPIO_227_STICKY GPIO_NONSTICKY +#define GPIO_228_STICKY GPIO_NONSTICKY +#define GPIO_229_STICKY GPIO_NONSTICKY + +#define PULLUP_ENABLE (0<<3) +#define PULLUP_DISABLE (1<<3) + +#define GPIO_00_PULLUP PULLUP_DISABLE +#define GPIO_01_PULLUP PULLUP_DISABLE +#define GPIO_02_PULLUP PULLUP_DISABLE +#define GPIO_03_PULLUP PULLUP_DISABLE +#define GPIO_04_PULLUP PULLUP_DISABLE +#define GPIO_05_PULLUP PULLUP_DISABLE +#define GPIO_06_PULLUP PULLUP_DISABLE +#define GPIO_07_PULLUP PULLUP_DISABLE +#define GPIO_08_PULLUP PULLUP_DISABLE +#define GPIO_09_PULLUP PULLUP_DISABLE +#define GPIO_10_PULLUP PULLUP_DISABLE +#define GPIO_11_PULLUP PULLUP_DISABLE +#define GPIO_12_PULLUP PULLUP_DISABLE +#define GPIO_13_PULLUP PULLUP_DISABLE +#define GPIO_14_PULLUP PULLUP_DISABLE +#define GPIO_15_PULLUP PULLUP_DISABLE +#define GPIO_16_PULLUP PULLUP_DISABLE +#define GPIO_17_PULLUP PULLUP_DISABLE +#define GPIO_18_PULLUP PULLUP_DISABLE +#define GPIO_19_PULLUP PULLUP_DISABLE +#define GPIO_20_PULLUP PULLUP_DISABLE +#define GPIO_21_PULLUP PULLUP_DISABLE +#define GPIO_22_PULLUP PULLUP_DISABLE +#define GPIO_23_PULLUP PULLUP_DISABLE +#define GPIO_24_PULLUP PULLUP_DISABLE +#define GPIO_25_PULLUP PULLUP_DISABLE +#define GPIO_26_PULLUP PULLUP_DISABLE +#define GPIO_27_PULLUP PULLUP_DISABLE +#define GPIO_28_PULLUP PULLUP_DISABLE +#define GPIO_29_PULLUP PULLUP_DISABLE +#define GPIO_30_PULLUP PULLUP_DISABLE +#define GPIO_31_PULLUP PULLUP_DISABLE +#define GPIO_32_PULLUP PULLUP_DISABLE +#define GPIO_33_PULLUP PULLUP_DISABLE +#define GPIO_34_PULLUP PULLUP_DISABLE +#define GPIO_35_PULLUP PULLUP_DISABLE +#define GPIO_36_PULLUP PULLUP_DISABLE +#define GPIO_37_PULLUP PULLUP_DISABLE +#define GPIO_38_PULLUP PULLUP_DISABLE +#define GPIO_39_PULLUP PULLUP_DISABLE +#define GPIO_40_PULLUP PULLUP_DISABLE +#define GPIO_41_PULLUP PULLUP_DISABLE +#define GPIO_42_PULLUP PULLUP_DISABLE +#define GPIO_43_PULLUP PULLUP_DISABLE +#define GPIO_44_PULLUP PULLUP_DISABLE +#define GPIO_45_PULLUP PULLUP_DISABLE +#define GPIO_46_PULLUP PULLUP_DISABLE +#define GPIO_47_PULLUP PULLUP_DISABLE +#define GPIO_48_PULLUP PULLUP_DISABLE +#define GPIO_49_PULLUP PULLUP_DISABLE +#define GPIO_50_PULLUP PULLUP_DISABLE +#define GPIO_51_PULLUP PULLUP_DISABLE +#define GPIO_52_PULLUP PULLUP_DISABLE +#define GPIO_53_PULLUP PULLUP_DISABLE +#define GPIO_54_PULLUP PULLUP_DISABLE +#define GPIO_55_PULLUP PULLUP_DISABLE +#define GPIO_56_PULLUP PULLUP_DISABLE +#define GPIO_57_PULLUP PULLUP_DISABLE +#define GPIO_58_PULLUP PULLUP_DISABLE +#define GPIO_59_PULLUP PULLUP_DISABLE +#define GPIO_60_PULLUP PULLUP_DISABLE +#define GPIO_61_PULLUP PULLUP_DISABLE +#define GPIO_62_PULLUP PULLUP_DISABLE +#define GPIO_63_PULLUP PULLUP_DISABLE +#define GPIO_64_PULLUP PULLUP_DISABLE +#define GPIO_65_PULLUP PULLUP_DISABLE +#define GPIO_66_PULLUP PULLUP_DISABLE +#define GPIO_67_PULLUP PULLUP_DISABLE +#define GPIO_68_PULLUP PULLUP_DISABLE +#define GPIO_69_PULLUP PULLUP_DISABLE +#define GPIO_70_PULLUP PULLUP_DISABLE +#define GPIO_71_PULLUP PULLUP_DISABLE +#define GPIO_72_PULLUP PULLUP_DISABLE +#define GPIO_73_PULLUP PULLUP_DISABLE +#define GPIO_74_PULLUP PULLUP_DISABLE +#define GPIO_75_PULLUP PULLUP_DISABLE +#define GPIO_76_PULLUP PULLUP_DISABLE +#define GPIO_77_PULLUP PULLUP_DISABLE +#define GPIO_78_PULLUP PULLUP_DISABLE +#define GPIO_79_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_81_PULLUP PULLUP_DISABLE +#define GPIO_82_PULLUP PULLUP_DISABLE +#define GPIO_83_PULLUP PULLUP_DISABLE +#define GPIO_84_PULLUP PULLUP_DISABLE +#define GPIO_85_PULLUP PULLUP_DISABLE +#define GPIO_86_PULLUP PULLUP_DISABLE +#define GPIO_87_PULLUP PULLUP_DISABLE +#define GPIO_88_PULLUP PULLUP_DISABLE +#define GPIO_89_PULLUP PULLUP_DISABLE +#define GPIO_90_PULLUP PULLUP_DISABLE +#define GPIO_91_PULLUP PULLUP_DISABLE +#define GPIO_92_PULLUP PULLUP_DISABLE +#define GPIO_93_PULLUP PULLUP_DISABLE +#define GPIO_94_PULLUP PULLUP_DISABLE +#define GPIO_95_PULLUP PULLUP_DISABLE +#define GPIO_96_PULLUP PULLUP_DISABLE +#define GPIO_97_PULLUP PULLUP_DISABLE +#define GPIO_98_PULLUP PULLUP_DISABLE +#define GPIO_99_PULLUP PULLUP_DISABLE +#define GPIO_100_PULLUP PULLUP_DISABLE +#define GPIO_101_PULLUP PULLUP_DISABLE +#define GPIO_102_PULLUP PULLUP_DISABLE +#define GPIO_103_PULLUP PULLUP_DISABLE +#define GPIO_104_PULLUP PULLUP_DISABLE +#define GPIO_105_PULLUP PULLUP_DISABLE +#define GPIO_106_PULLUP PULLUP_DISABLE +#define GPIO_107_PULLUP PULLUP_DISABLE +#define GPIO_108_PULLUP PULLUP_DISABLE +#define GPIO_109_PULLUP PULLUP_DISABLE +#define GPIO_110_PULLUP PULLUP_DISABLE +#define GPIO_111_PULLUP PULLUP_DISABLE +#define GPIO_112_PULLUP PULLUP_DISABLE +#define GPIO_113_PULLUP PULLUP_DISABLE +#define GPIO_114_PULLUP PULLUP_DISABLE +#define GPIO_115_PULLUP PULLUP_DISABLE +#define GPIO_116_PULLUP PULLUP_DISABLE +#define GPIO_117_PULLUP PULLUP_DISABLE +#define GPIO_118_PULLUP PULLUP_ENABLE +#define GPIO_119_PULLUP PULLUP_DISABLE +#define GPIO_120_PULLUP PULLUP_DISABLE +#define GPIO_121_PULLUP PULLUP_DISABLE +#define GPIO_122_PULLUP PULLUP_DISABLE +#define GPIO_123_PULLUP PULLUP_DISABLE +#define GPIO_124_PULLUP PULLUP_DISABLE +#define GPIO_125_PULLUP PULLUP_DISABLE +#define GPIO_126_PULLUP PULLUP_DISABLE +#define GPIO_127_PULLUP PULLUP_DISABLE +#define GPIO_128_PULLUP PULLUP_DISABLE +#define GPIO_129_PULLUP PULLUP_DISABLE +#define GPIO_130_PULLUP PULLUP_DISABLE +#define GPIO_131_PULLUP PULLUP_DISABLE +#define GPIO_132_PULLUP PULLUP_DISABLE +#define GPIO_133_PULLUP PULLUP_DISABLE +#define GPIO_134_PULLUP PULLUP_DISABLE +#define GPIO_135_PULLUP PULLUP_DISABLE +#define GPIO_136_PULLUP PULLUP_DISABLE +#define GPIO_137_PULLUP PULLUP_DISABLE +#define GPIO_138_PULLUP PULLUP_DISABLE +#define GPIO_139_PULLUP PULLUP_DISABLE +#define GPIO_140_PULLUP PULLUP_DISABLE +#define GPIO_141_PULLUP PULLUP_DISABLE +#define GPIO_142_PULLUP PULLUP_DISABLE +#define GPIO_143_PULLUP PULLUP_DISABLE +#define GPIO_144_PULLUP PULLUP_DISABLE +#define GPIO_145_PULLUP PULLUP_DISABLE +#define GPIO_146_PULLUP PULLUP_DISABLE +#define GPIO_147_PULLUP PULLUP_DISABLE +#define GPIO_148_PULLUP PULLUP_DISABLE +#define GPIO_149_PULLUP PULLUP_DISABLE +#define GPIO_150_PULLUP PULLUP_DISABLE +#define GPIO_151_PULLUP PULLUP_DISABLE +#define GPIO_152_PULLUP PULLUP_DISABLE +#define GPIO_153_PULLUP PULLUP_DISABLE +#define GPIO_154_PULLUP PULLUP_DISABLE +#define GPIO_155_PULLUP PULLUP_DISABLE +#define GPIO_156_PULLUP PULLUP_DISABLE +#define GPIO_157_PULLUP PULLUP_DISABLE +#define GPIO_158_PULLUP PULLUP_DISABLE +#define GPIO_159_PULLUP PULLUP_DISABLE +#define GPIO_160_PULLUP PULLUP_DISABLE +#define GPIO_161_PULLUP PULLUP_DISABLE +#define GPIO_162_PULLUP PULLUP_DISABLE +#define GPIO_163_PULLUP PULLUP_DISABLE +#define GPIO_164_PULLUP PULLUP_DISABLE +#define GPIO_165_PULLUP PULLUP_DISABLE +#define GPIO_166_PULLUP PULLUP_DISABLE +#define GPIO_167_PULLUP PULLUP_DISABLE +#define GPIO_168_PULLUP PULLUP_DISABLE +#define GPIO_169_PULLUP PULLUP_DISABLE +#define GPIO_170_PULLUP PULLUP_DISABLE +#define GPIO_171_PULLUP PULLUP_DISABLE +#define GPIO_172_PULLUP PULLUP_DISABLE +#define GPIO_173_PULLUP PULLUP_DISABLE +#define GPIO_174_PULLUP PULLUP_DISABLE +#define GPIO_175_PULLUP PULLUP_DISABLE +#define GPIO_176_PULLUP PULLUP_DISABLE +#define GPIO_177_PULLUP PULLUP_DISABLE +#define GPIO_178_PULLUP PULLUP_DISABLE +#define GPIO_179_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_181_PULLUP PULLUP_DISABLE +#define GPIO_182_PULLUP PULLUP_DISABLE +#define GPIO_183_PULLUP PULLUP_DISABLE +#define GPIO_184_PULLUP PULLUP_DISABLE +#define GPIO_185_PULLUP PULLUP_DISABLE +#define GPIO_186_PULLUP PULLUP_DISABLE +#define GPIO_187_PULLUP PULLUP_DISABLE +#define GPIO_188_PULLUP PULLUP_DISABLE +#define GPIO_189_PULLUP PULLUP_DISABLE +#define GPIO_190_PULLUP PULLUP_DISABLE +#define GPIO_191_PULLUP PULLUP_DISABLE +#define GPIO_192_PULLUP PULLUP_DISABLE +#define GPIO_193_PULLUP PULLUP_DISABLE +#define GPIO_194_PULLUP PULLUP_DISABLE +#define GPIO_195_PULLUP PULLUP_DISABLE +#define GPIO_196_PULLUP PULLUP_DISABLE +#define GPIO_197_PULLUP PULLUP_DISABLE +#define GPIO_198_PULLUP PULLUP_DISABLE +#define GPIO_199_PULLUP PULLUP_DISABLE +#define GPIO_200_PULLUP PULLUP_DISABLE +#define GPIO_201_PULLUP PULLUP_DISABLE +#define GPIO_202_PULLUP PULLUP_DISABLE +#define GPIO_203_PULLUP PULLUP_DISABLE +#define GPIO_204_PULLUP PULLUP_DISABLE +#define GPIO_205_PULLUP PULLUP_DISABLE +#define GPIO_206_PULLUP PULLUP_DISABLE +#define GPIO_207_PULLUP PULLUP_DISABLE +#define GPIO_208_PULLUP PULLUP_DISABLE +#define GPIO_209_PULLUP PULLUP_DISABLE +#define GPIO_210_PULLUP PULLUP_DISABLE +#define GPIO_211_PULLUP PULLUP_DISABLE +#define GPIO_212_PULLUP PULLUP_DISABLE +#define GPIO_213_PULLUP PULLUP_DISABLE +#define GPIO_214_PULLUP PULLUP_DISABLE +#define GPIO_215_PULLUP PULLUP_DISABLE +#define GPIO_216_PULLUP PULLUP_DISABLE +#define GPIO_217_PULLUP PULLUP_DISABLE +#define GPIO_218_PULLUP PULLUP_DISABLE +#define GPIO_219_PULLUP PULLUP_DISABLE +#define GPIO_220_PULLUP PULLUP_DISABLE +#define GPIO_221_PULLUP PULLUP_DISABLE +#define GPIO_222_PULLUP PULLUP_DISABLE +#define GPIO_223_PULLUP PULLUP_DISABLE +#define GPIO_224_PULLUP PULLUP_DISABLE +#define GPIO_225_PULLUP PULLUP_DISABLE +#define GPIO_226_PULLUP PULLUP_DISABLE +#define GPIO_227_PULLUP PULLUP_DISABLE +#define GPIO_228_PULLUP PULLUP_DISABLE +#define GPIO_229_PULLUP PULLUP_DISABLE + +#define PULLDOWN_ENABLE (1<<4) +#define PULLDOWN_DISABLE (0<<4) + +#define GPIO_00_PULLDOWN PULLDOWN_DISABLE +#define GPIO_01_PULLDOWN PULLDOWN_DISABLE +#define GPIO_02_PULLDOWN PULLDOWN_DISABLE +#define GPIO_03_PULLDOWN PULLDOWN_DISABLE +#define GPIO_04_PULLDOWN PULLDOWN_DISABLE +#define GPIO_05_PULLDOWN PULLDOWN_DISABLE +#define GPIO_06_PULLDOWN PULLDOWN_DISABLE +#define GPIO_07_PULLDOWN PULLDOWN_DISABLE +#define GPIO_08_PULLDOWN PULLDOWN_DISABLE +#define GPIO_09_PULLDOWN PULLDOWN_DISABLE +#define GPIO_10_PULLDOWN PULLDOWN_DISABLE +#define GPIO_11_PULLDOWN PULLDOWN_DISABLE +#define GPIO_12_PULLDOWN PULLDOWN_DISABLE +#define GPIO_13_PULLDOWN PULLDOWN_DISABLE +#define GPIO_14_PULLDOWN PULLDOWN_DISABLE +#define GPIO_15_PULLDOWN PULLDOWN_DISABLE +#define GPIO_16_PULLDOWN PULLDOWN_DISABLE +#define GPIO_17_PULLDOWN PULLDOWN_DISABLE +#define GPIO_18_PULLDOWN PULLDOWN_DISABLE +#define GPIO_19_PULLDOWN PULLDOWN_DISABLE +#define GPIO_20_PULLDOWN PULLDOWN_DISABLE +#define GPIO_21_PULLDOWN PULLDOWN_DISABLE +#define GPIO_22_PULLDOWN PULLDOWN_DISABLE +#define GPIO_23_PULLDOWN PULLDOWN_DISABLE +#define GPIO_24_PULLDOWN PULLDOWN_DISABLE +#define GPIO_25_PULLDOWN PULLDOWN_DISABLE +#define GPIO_26_PULLDOWN PULLDOWN_DISABLE +#define GPIO_27_PULLDOWN PULLDOWN_DISABLE +#define GPIO_28_PULLDOWN PULLDOWN_DISABLE +#define GPIO_29_PULLDOWN PULLDOWN_DISABLE +#define GPIO_30_PULLDOWN PULLDOWN_DISABLE +#define GPIO_31_PULLDOWN PULLDOWN_DISABLE +#define GPIO_32_PULLDOWN PULLDOWN_DISABLE +#define GPIO_33_PULLDOWN PULLDOWN_DISABLE +#define GPIO_34_PULLDOWN PULLDOWN_DISABLE +#define GPIO_35_PULLDOWN PULLDOWN_DISABLE +#define GPIO_36_PULLDOWN PULLDOWN_DISABLE +#define GPIO_37_PULLDOWN PULLDOWN_DISABLE +#define GPIO_38_PULLDOWN PULLDOWN_DISABLE +#define GPIO_39_PULLDOWN PULLDOWN_DISABLE +#define GPIO_40_PULLDOWN PULLDOWN_DISABLE +#define GPIO_41_PULLDOWN PULLDOWN_DISABLE +#define GPIO_42_PULLDOWN PULLDOWN_DISABLE +#define GPIO_43_PULLDOWN PULLDOWN_DISABLE +#define GPIO_44_PULLDOWN PULLDOWN_DISABLE +#define GPIO_45_PULLDOWN PULLDOWN_DISABLE +#define GPIO_46_PULLDOWN PULLDOWN_DISABLE +#define GPIO_47_PULLDOWN PULLDOWN_DISABLE +#define GPIO_48_PULLDOWN PULLDOWN_DISABLE +#define GPIO_49_PULLDOWN PULLDOWN_DISABLE +#define GPIO_50_PULLDOWN PULLDOWN_DISABLE +#define GPIO_51_PULLDOWN PULLDOWN_DISABLE +#define GPIO_52_PULLDOWN PULLDOWN_DISABLE +#define GPIO_53_PULLDOWN PULLDOWN_DISABLE +#define GPIO_54_PULLDOWN PULLDOWN_DISABLE +#define GPIO_55_PULLDOWN PULLDOWN_DISABLE +#define GPIO_56_PULLDOWN PULLDOWN_DISABLE +#define GPIO_57_PULLDOWN PULLDOWN_DISABLE +#define GPIO_58_PULLDOWN PULLDOWN_DISABLE +#define GPIO_59_PULLDOWN PULLDOWN_DISABLE +#define GPIO_60_PULLDOWN PULLDOWN_DISABLE +#define GPIO_61_PULLDOWN PULLDOWN_DISABLE +#define GPIO_62_PULLDOWN PULLDOWN_DISABLE +#define GPIO_63_PULLDOWN PULLDOWN_DISABLE +#define GPIO_64_PULLDOWN PULLDOWN_DISABLE +#define GPIO_65_PULLDOWN PULLDOWN_DISABLE +#define GPIO_66_PULLDOWN PULLDOWN_DISABLE +#define GPIO_67_PULLDOWN PULLDOWN_DISABLE +#define GPIO_68_PULLDOWN PULLDOWN_DISABLE +#define GPIO_69_PULLDOWN PULLDOWN_DISABLE +#define GPIO_70_PULLDOWN PULLDOWN_DISABLE +#define GPIO_71_PULLDOWN PULLDOWN_DISABLE +#define GPIO_72_PULLDOWN PULLDOWN_DISABLE +#define GPIO_73_PULLDOWN PULLDOWN_DISABLE +#define GPIO_74_PULLDOWN PULLDOWN_DISABLE +#define GPIO_75_PULLDOWN PULLDOWN_DISABLE +#define GPIO_76_PULLDOWN PULLDOWN_DISABLE +#define GPIO_77_PULLDOWN PULLDOWN_DISABLE +#define GPIO_78_PULLDOWN PULLDOWN_DISABLE +#define GPIO_79_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_81_PULLDOWN PULLDOWN_DISABLE +#define GPIO_82_PULLDOWN PULLDOWN_DISABLE +#define GPIO_83_PULLDOWN PULLDOWN_DISABLE +#define GPIO_84_PULLDOWN PULLDOWN_DISABLE +#define GPIO_85_PULLDOWN PULLDOWN_DISABLE +#define GPIO_86_PULLDOWN PULLDOWN_DISABLE +#define GPIO_87_PULLDOWN PULLDOWN_DISABLE +#define GPIO_88_PULLDOWN PULLDOWN_DISABLE +#define GPIO_89_PULLDOWN PULLDOWN_DISABLE +#define GPIO_90_PULLDOWN PULLDOWN_DISABLE +#define GPIO_91_PULLDOWN PULLDOWN_DISABLE +#define GPIO_92_PULLDOWN PULLDOWN_DISABLE +#define GPIO_93_PULLDOWN PULLDOWN_DISABLE +#define GPIO_94_PULLDOWN PULLDOWN_DISABLE +#define GPIO_95_PULLDOWN PULLDOWN_DISABLE +#define GPIO_96_PULLDOWN PULLDOWN_DISABLE +#define GPIO_97_PULLDOWN PULLDOWN_DISABLE +#define GPIO_98_PULLDOWN PULLDOWN_DISABLE +#define GPIO_99_PULLDOWN PULLDOWN_DISABLE +#define GPIO_100_PULLDOWN PULLDOWN_DISABLE +#define GPIO_101_PULLDOWN PULLDOWN_DISABLE +#define GPIO_102_PULLDOWN PULLDOWN_DISABLE +#define GPIO_103_PULLDOWN PULLDOWN_DISABLE +#define GPIO_104_PULLDOWN PULLDOWN_DISABLE +#define GPIO_105_PULLDOWN PULLDOWN_DISABLE +#define GPIO_106_PULLDOWN PULLDOWN_DISABLE +#define GPIO_107_PULLDOWN PULLDOWN_DISABLE +#define GPIO_108_PULLDOWN PULLDOWN_DISABLE +#define GPIO_109_PULLDOWN PULLDOWN_DISABLE +#define GPIO_110_PULLDOWN PULLDOWN_DISABLE +#define GPIO_111_PULLDOWN PULLDOWN_DISABLE +#define GPIO_112_PULLDOWN PULLDOWN_DISABLE +#define GPIO_113_PULLDOWN PULLDOWN_DISABLE +#define GPIO_114_PULLDOWN PULLDOWN_DISABLE +#define GPIO_115_PULLDOWN PULLDOWN_DISABLE +#define GPIO_116_PULLDOWN PULLDOWN_DISABLE +#define GPIO_117_PULLDOWN PULLDOWN_DISABLE +#define GPIO_118_PULLDOWN PULLDOWN_DISABLE +#define GPIO_119_PULLDOWN PULLDOWN_DISABLE +#define GPIO_120_PULLDOWN PULLDOWN_DISABLE +#define GPIO_121_PULLDOWN PULLDOWN_DISABLE +#define GPIO_122_PULLDOWN PULLDOWN_DISABLE +#define GPIO_123_PULLDOWN PULLDOWN_DISABLE +#define GPIO_124_PULLDOWN PULLDOWN_DISABLE +#define GPIO_125_PULLDOWN PULLDOWN_DISABLE +#define GPIO_126_PULLDOWN PULLDOWN_DISABLE +#define GPIO_127_PULLDOWN PULLDOWN_DISABLE +#define GPIO_128_PULLDOWN PULLDOWN_DISABLE +#define GPIO_129_PULLDOWN PULLDOWN_DISABLE +#define GPIO_130_PULLDOWN PULLDOWN_DISABLE +#define GPIO_131_PULLDOWN PULLDOWN_DISABLE +#define GPIO_132_PULLDOWN PULLDOWN_DISABLE +#define GPIO_133_PULLDOWN PULLDOWN_DISABLE +#define GPIO_134_PULLDOWN PULLDOWN_DISABLE +#define GPIO_135_PULLDOWN PULLDOWN_DISABLE +#define GPIO_136_PULLDOWN PULLDOWN_DISABLE +#define GPIO_137_PULLDOWN PULLDOWN_DISABLE +#define GPIO_138_PULLDOWN PULLDOWN_DISABLE +#define GPIO_139_PULLDOWN PULLDOWN_DISABLE +#define GPIO_140_PULLDOWN PULLDOWN_DISABLE +#define GPIO_141_PULLDOWN PULLDOWN_DISABLE +#define GPIO_142_PULLDOWN PULLDOWN_DISABLE +#define GPIO_143_PULLDOWN PULLDOWN_DISABLE +#define GPIO_144_PULLDOWN PULLDOWN_DISABLE +#define GPIO_145_PULLDOWN PULLDOWN_DISABLE +#define GPIO_146_PULLDOWN PULLDOWN_DISABLE +#define GPIO_147_PULLDOWN PULLDOWN_DISABLE +#define GPIO_148_PULLDOWN PULLDOWN_DISABLE +#define GPIO_149_PULLDOWN PULLDOWN_DISABLE +#define GPIO_150_PULLDOWN PULLDOWN_DISABLE +#define GPIO_151_PULLDOWN PULLDOWN_DISABLE +#define GPIO_152_PULLDOWN PULLDOWN_DISABLE +#define GPIO_153_PULLDOWN PULLDOWN_DISABLE +#define GPIO_154_PULLDOWN PULLDOWN_DISABLE +#define GPIO_155_PULLDOWN PULLDOWN_DISABLE +#define GPIO_156_PULLDOWN PULLDOWN_DISABLE +#define GPIO_157_PULLDOWN PULLDOWN_DISABLE +#define GPIO_158_PULLDOWN PULLDOWN_DISABLE +#define GPIO_159_PULLDOWN PULLDOWN_DISABLE +#define GPIO_160_PULLDOWN PULLDOWN_DISABLE +#define GPIO_161_PULLDOWN PULLDOWN_DISABLE +#define GPIO_162_PULLDOWN PULLDOWN_ENABLE +#define GPIO_163_PULLDOWN PULLDOWN_ENABLE +#define GPIO_164_PULLDOWN PULLDOWN_ENABLE +#define GPIO_165_PULLDOWN PULLDOWN_DISABLE +#define GPIO_166_PULLDOWN PULLDOWN_DISABLE +#define GPIO_167_PULLDOWN PULLDOWN_ENABLE +#define GPIO_168_PULLDOWN PULLDOWN_DISABLE +#define GPIO_169_PULLDOWN PULLDOWN_DISABLE +#define GPIO_170_PULLDOWN PULLDOWN_DISABLE +#define GPIO_171_PULLDOWN PULLDOWN_DISABLE +#define GPIO_172_PULLDOWN PULLDOWN_DISABLE +#define GPIO_173_PULLDOWN PULLDOWN_DISABLE +#define GPIO_174_PULLDOWN PULLDOWN_DISABLE +#define GPIO_175_PULLDOWN PULLDOWN_DISABLE +#define GPIO_176_PULLDOWN PULLDOWN_DISABLE +#define GPIO_177_PULLDOWN PULLDOWN_DISABLE +#define GPIO_178_PULLDOWN PULLDOWN_DISABLE +#define GPIO_179_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_181_PULLDOWN PULLDOWN_DISABLE +#define GPIO_182_PULLDOWN PULLDOWN_DISABLE +#define GPIO_183_PULLDOWN PULLDOWN_DISABLE +#define GPIO_184_PULLDOWN PULLDOWN_DISABLE +#define GPIO_185_PULLDOWN PULLDOWN_ENABLE +#define GPIO_186_PULLDOWN PULLDOWN_ENABLE +#define GPIO_187_PULLDOWN PULLDOWN_DISABLE +#define GPIO_188_PULLDOWN PULLDOWN_DISABLE +#define GPIO_189_PULLDOWN PULLDOWN_DISABLE +#define GPIO_190_PULLDOWN PULLDOWN_DISABLE +#define GPIO_191_PULLDOWN PULLDOWN_DISABLE +#define GPIO_192_PULLDOWN PULLDOWN_DISABLE +#define GPIO_193_PULLDOWN PULLDOWN_DISABLE +#define GPIO_194_PULLDOWN PULLDOWN_DISABLE +#define GPIO_195_PULLDOWN PULLDOWN_DISABLE +#define GPIO_196_PULLDOWN PULLDOWN_DISABLE +#define GPIO_197_PULLDOWN PULLDOWN_DISABLE +#define GPIO_198_PULLDOWN PULLDOWN_DISABLE +#define GPIO_199_PULLDOWN PULLDOWN_DISABLE +#define GPIO_200_PULLDOWN PULLDOWN_DISABLE +#define GPIO_201_PULLDOWN PULLDOWN_DISABLE +#define GPIO_202_PULLDOWN PULLDOWN_DISABLE +#define GPIO_203_PULLDOWN PULLDOWN_DISABLE +#define GPIO_204_PULLDOWN PULLDOWN_DISABLE +#define GPIO_205_PULLDOWN PULLDOWN_DISABLE +#define GPIO_206_PULLDOWN PULLDOWN_DISABLE +#define GPIO_207_PULLDOWN PULLDOWN_DISABLE +#define GPIO_208_PULLDOWN PULLDOWN_DISABLE +#define GPIO_209_PULLDOWN PULLDOWN_DISABLE +#define GPIO_210_PULLDOWN PULLDOWN_DISABLE +#define GPIO_211_PULLDOWN PULLDOWN_DISABLE +#define GPIO_212_PULLDOWN PULLDOWN_DISABLE +#define GPIO_213_PULLDOWN PULLDOWN_DISABLE +#define GPIO_214_PULLDOWN PULLDOWN_DISABLE +#define GPIO_215_PULLDOWN PULLDOWN_DISABLE +#define GPIO_216_PULLDOWN PULLDOWN_DISABLE +#define GPIO_217_PULLDOWN PULLDOWN_DISABLE +#define GPIO_218_PULLDOWN PULLDOWN_DISABLE +#define GPIO_219_PULLDOWN PULLDOWN_DISABLE +#define GPIO_220_PULLDOWN PULLDOWN_DISABLE +#define GPIO_221_PULLDOWN PULLDOWN_DISABLE +#define GPIO_222_PULLDOWN PULLDOWN_DISABLE +#define GPIO_223_PULLDOWN PULLDOWN_DISABLE +#define GPIO_224_PULLDOWN PULLDOWN_DISABLE +#define GPIO_225_PULLDOWN PULLDOWN_DISABLE +#define GPIO_226_PULLDOWN PULLDOWN_DISABLE +#define GPIO_227_PULLDOWN PULLDOWN_DISABLE +#define GPIO_228_PULLDOWN PULLDOWN_DISABLE +#define GPIO_229_PULLDOWN PULLDOWN_DISABLE + +#define EVENT_DISABLE 0 +#define EVENT_ENABLE 1 + +#define GEVENT_00_EVENTENABLE EVENT_DISABLE +#define GEVENT_01_EVENTENABLE EVENT_DISABLE +#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# +#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# +#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# +#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_06_EVENTENABLE EVENT_DISABLE +#define GEVENT_07_EVENTENABLE EVENT_DISABLE +#define GEVENT_08_EVENTENABLE EVENT_DISABLE +#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_10_EVENTENABLE EVENT_DISABLE +#define GEVENT_11_EVENTENABLE EVENT_DISABLE +#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_13_EVENTENABLE EVENT_DISABLE +#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# +#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# +#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA +#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_18_EVENTENABLE EVENT_DISABLE +#define GEVENT_19_EVENTENABLE EVENT_DISABLE +#define GEVENT_20_EVENTENABLE EVENT_DISABLE +#define GEVENT_21_EVENTENABLE EVENT_DISABLE +#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# +#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# + +#define SCITRIG_LOW 0 +#define SCITRIG_HI 1 + +#define GEVENT_00_SCITRIG SCITRIG_LOW +#define GEVENT_01_SCITRIG SCITRIG_LOW +#define GEVENT_02_SCITRIG SCITRIG_LOW +#define GEVENT_03_SCITRIG SCITRIG_LOW +#define GEVENT_04_SCITRIG SCITRIG_LOW +#define GEVENT_05_SCITRIG SCITRIG_LOW +#define GEVENT_06_SCITRIG SCITRIG_LOW +#define GEVENT_07_SCITRIG SCITRIG_LOW +#define GEVENT_08_SCITRIG SCITRIG_LOW +#define GEVENT_09_SCITRIG SCITRIG_LOW +#define GEVENT_10_SCITRIG SCITRIG_LOW +#define GEVENT_11_SCITRIG SCITRIG_LOW +#define GEVENT_12_SCITRIG SCITRIG_LOW +#define GEVENT_13_SCITRIG SCITRIG_LOW +#define GEVENT_14_SCITRIG SCITRIG_LOW +#define GEVENT_15_SCITRIG SCITRIG_LOW +#define GEVENT_16_SCITRIG SCITRIG_LOW +#define GEVENT_17_SCITRIG SCITRIG_HI +#define GEVENT_18_SCITRIG SCITRIG_LOW +#define GEVENT_19_SCITRIG SCITRIG_LOW +#define GEVENT_20_SCITRIG SCITRIG_LOW +#define GEVENT_21_SCITRIG SCITRIG_LOW +#define GEVENT_22_SCITRIG SCITRIG_LOW +#define GEVENT_23_SCITRIG SCITRIG_LOW + +#define SCILEVEL_EDGE 0 +#define SCILEVEL_LEVEL 1 + +#define GEVENT_00_SCILEVEL SCILEVEL_EDGE +#define GEVENT_01_SCILEVEL SCILEVEL_EDGE +#define GEVENT_02_SCILEVEL SCILEVEL_EDGE +#define GEVENT_03_SCILEVEL SCILEVEL_EDGE +#define GEVENT_04_SCILEVEL SCILEVEL_EDGE +#define GEVENT_05_SCILEVEL SCILEVEL_EDGE +#define GEVENT_06_SCILEVEL SCILEVEL_EDGE +#define GEVENT_07_SCILEVEL SCILEVEL_EDGE +#define GEVENT_08_SCILEVEL SCILEVEL_EDGE +#define GEVENT_09_SCILEVEL SCILEVEL_EDGE +#define GEVENT_10_SCILEVEL SCILEVEL_EDGE +#define GEVENT_11_SCILEVEL SCILEVEL_EDGE +#define GEVENT_12_SCILEVEL SCILEVEL_EDGE +#define GEVENT_13_SCILEVEL SCILEVEL_EDGE +#define GEVENT_14_SCILEVEL SCILEVEL_EDGE +#define GEVENT_15_SCILEVEL SCILEVEL_EDGE +#define GEVENT_16_SCILEVEL SCILEVEL_EDGE +#define GEVENT_17_SCILEVEL SCILEVEL_EDGE +#define GEVENT_18_SCILEVEL SCILEVEL_EDGE +#define GEVENT_19_SCILEVEL SCILEVEL_EDGE +#define GEVENT_20_SCILEVEL SCILEVEL_EDGE +#define GEVENT_21_SCILEVEL SCILEVEL_EDGE +#define GEVENT_22_SCILEVEL SCILEVEL_EDGE +#define GEVENT_23_SCILEVEL SCILEVEL_EDGE + +#define SMISCI_DISABLE 0 +#define SMISCI_ENABLE 1 + +#define GEVENT_00_SMISCIEN SMISCI_DISABLE +#define GEVENT_01_SMISCIEN SMISCI_DISABLE +#define GEVENT_02_SMISCIEN SMISCI_DISABLE +#define GEVENT_03_SMISCIEN SMISCI_DISABLE +#define GEVENT_04_SMISCIEN SMISCI_DISABLE +#define GEVENT_05_SMISCIEN SMISCI_DISABLE +#define GEVENT_06_SMISCIEN SMISCI_DISABLE +#define GEVENT_07_SMISCIEN SMISCI_DISABLE +#define GEVENT_08_SMISCIEN SMISCI_DISABLE +#define GEVENT_09_SMISCIEN SMISCI_DISABLE +#define GEVENT_10_SMISCIEN SMISCI_DISABLE +#define GEVENT_11_SMISCIEN SMISCI_DISABLE +#define GEVENT_12_SMISCIEN SMISCI_DISABLE +#define GEVENT_13_SMISCIEN SMISCI_DISABLE +#define GEVENT_14_SMISCIEN SMISCI_DISABLE +#define GEVENT_15_SMISCIEN SMISCI_DISABLE +#define GEVENT_16_SMISCIEN SMISCI_DISABLE +#define GEVENT_17_SMISCIEN SMISCI_DISABLE +#define GEVENT_18_SMISCIEN SMISCI_DISABLE +#define GEVENT_19_SMISCIEN SMISCI_DISABLE +#define GEVENT_20_SMISCIEN SMISCI_DISABLE +#define GEVENT_21_SMISCIEN SMISCI_DISABLE +#define GEVENT_22_SMISCIEN SMISCI_DISABLE +#define GEVENT_23_SMISCIEN SMISCI_DISABLE + +#define SCIS0_DISABLE 0 +#define SCIS0_ENABLE 1 + +#define GEVENT_00_SCIS0EN SCIS0_DISABLE +#define GEVENT_01_SCIS0EN SCIS0_DISABLE +#define GEVENT_02_SCIS0EN SCIS0_DISABLE +#define GEVENT_03_SCIS0EN SCIS0_DISABLE +#define GEVENT_04_SCIS0EN SCIS0_DISABLE +#define GEVENT_05_SCIS0EN SCIS0_DISABLE +#define GEVENT_06_SCIS0EN SCIS0_DISABLE +#define GEVENT_07_SCIS0EN SCIS0_DISABLE +#define GEVENT_08_SCIS0EN SCIS0_DISABLE +#define GEVENT_09_SCIS0EN SCIS0_DISABLE +#define GEVENT_10_SCIS0EN SCIS0_DISABLE +#define GEVENT_11_SCIS0EN SCIS0_DISABLE +#define GEVENT_12_SCIS0EN SCIS0_DISABLE +#define GEVENT_13_SCIS0EN SCIS0_DISABLE +#define GEVENT_14_SCIS0EN SCIS0_DISABLE +#define GEVENT_15_SCIS0EN SCIS0_DISABLE +#define GEVENT_16_SCIS0EN SCIS0_DISABLE +#define GEVENT_17_SCIS0EN SCIS0_DISABLE +#define GEVENT_18_SCIS0EN SCIS0_DISABLE +#define GEVENT_19_SCIS0EN SCIS0_DISABLE +#define GEVENT_20_SCIS0EN SCIS0_DISABLE +#define GEVENT_21_SCIS0EN SCIS0_DISABLE +#define GEVENT_22_SCIS0EN SCIS0_DISABLE +#define GEVENT_23_SCIS0EN SCIS0_DISABLE + +#define GEVENT_SCIMASK 0x1F +#define GEVENT_00_SCIMAP 0 +#define GEVENT_01_SCIMAP 1 +#define GEVENT_02_SCIMAP 2 +#define GEVENT_03_SCIMAP 3 +#define GEVENT_04_SCIMAP 4 +#define GEVENT_05_SCIMAP 5 +#define GEVENT_06_SCIMAP 6 +#define GEVENT_07_SCIMAP 7 +#define GEVENT_08_SCIMAP 8 +#define GEVENT_09_SCIMAP 9 +#define GEVENT_10_SCIMAP 10 +#define GEVENT_11_SCIMAP 11 +#define GEVENT_12_SCIMAP 12 +#define GEVENT_13_SCIMAP 13 +#define GEVENT_14_SCIMAP 14 +#define GEVENT_15_SCIMAP 15 +#define GEVENT_16_SCIMAP 16 +#define GEVENT_17_SCIMAP 17 +#define GEVENT_18_SCIMAP 18 +#define GEVENT_19_SCIMAP 19 +#define GEVENT_20_SCIMAP 20 +#define GEVENT_21_SCIMAP 21 +#define GEVENT_22_SCIMAP 22 +#define GEVENT_23_SCIMAP 23 + +#define SMITRIG_LOW 0 +#define SMITRIG_HI 1 + +#define GEVENT_00_SMITRIG SMITRIG_HI +#define GEVENT_01_SMITRIG SMITRIG_HI +#define GEVENT_02_SMITRIG SMITRIG_HI +#define GEVENT_03_SMITRIG SMITRIG_HI +#define GEVENT_04_SMITRIG SMITRIG_HI +#define GEVENT_05_SMITRIG SMITRIG_HI +#define GEVENT_06_SMITRIG SMITRIG_HI +#define GEVENT_07_SMITRIG SMITRIG_HI +#define GEVENT_08_SMITRIG SMITRIG_HI +#define GEVENT_09_SMITRIG SMITRIG_HI +#define GEVENT_10_SMITRIG SMITRIG_HI +#define GEVENT_11_SMITRIG SMITRIG_HI +#define GEVENT_12_SMITRIG SMITRIG_HI +#define GEVENT_13_SMITRIG SMITRIG_HI +#define GEVENT_14_SMITRIG SMITRIG_HI +#define GEVENT_15_SMITRIG SMITRIG_HI +#define GEVENT_16_SMITRIG SMITRIG_HI +#define GEVENT_17_SMITRIG SMITRIG_HI +#define GEVENT_18_SMITRIG SMITRIG_HI +#define GEVENT_19_SMITRIG SMITRIG_HI +#define GEVENT_20_SMITRIG SMITRIG_HI +#define GEVENT_21_SMITRIG SMITRIG_HI +#define GEVENT_22_SMITRIG SMITRIG_HI +#define GEVENT_23_SMITRIG SMITRIG_HI + +#define SMICONTROL_MASK 3 +#define SMICONTROL_DISABLE 0 +#define SMICONTROL_SMI 1 +#define SMICONTROL_NMI 2 +#define SMICONTROL_IRQ13 3 + +#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE + +#define GPIO_RSVD_ZONE0_S GPIO_81 +#define GPIO_RSVD_ZONE0_E GPIO_95 +#define GPIO_RSVD_ZONE1_S GPIO_120 +#define GPIO_RSVD_ZONE1_E GPIO_127 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef enum _GPIO_COUNT +{ + GPIO_00=0, + GPIO_01, + GPIO_02, + GPIO_03, + GPIO_04, + GPIO_05, + GPIO_06, + GPIO_07, + GPIO_08, + GPIO_09, + GPIO_10, + GPIO_11, + GPIO_12, + GPIO_13, + GPIO_14, + GPIO_15, + GPIO_16, + GPIO_17, + GPIO_18, + GPIO_19, + GPIO_20, + GPIO_21, + GPIO_22, + GPIO_23, + GPIO_24, + GPIO_25, + GPIO_26, + GPIO_27, + GPIO_28, + GPIO_29, + GPIO_30, + GPIO_31, + GPIO_32, + GPIO_33, + GPIO_34, + GPIO_35, + GPIO_36, + GPIO_37, + GPIO_38, + GPIO_39, + GPIO_40, + GPIO_41, + GPIO_42, + GPIO_43, + GPIO_44, + GPIO_45, + GPIO_46, + GPIO_47, + GPIO_48, + GPIO_49, + GPIO_50, + GPIO_51, + GPIO_52, + GPIO_53, + GPIO_54, + GPIO_55, + GPIO_56, + GPIO_57, + GPIO_58, + GPIO_59, + GPIO_60, + GPIO_61, + GPIO_62, + GPIO_63, + GPIO_64, + GPIO_65, + GPIO_66, + GPIO_67, + GPIO_68, + GPIO_69, + GPIO_70, + GPIO_71, + GPIO_72, + GPIO_73, + GPIO_74, + GPIO_75, + GPIO_76, + GPIO_77, + GPIO_78, + GPIO_79, + GPIO_80, + GPIO_81, + GPIO_82, + GPIO_83, + GPIO_84, + GPIO_85, + GPIO_86, + GPIO_87, + GPIO_88, + GPIO_89, + GPIO_90, + GPIO_91, + GPIO_92, + GPIO_93, + GPIO_94, + GPIO_95, + GPIO_96, + GPIO_97, + GPIO_98, + GPIO_99, + GPIO_100, + GPIO_101, + GPIO_102, + GPIO_103, + GPIO_104, + GPIO_105, + GPIO_106, + GPIO_107, + GPIO_108, + GPIO_109, + GPIO_110, + GPIO_111, + GPIO_112, + GPIO_113, + GPIO_114, + GPIO_115, + GPIO_116, + GPIO_117, + GPIO_118, + GPIO_119, + GPIO_120, + GPIO_121, + GPIO_122, + GPIO_123, + GPIO_124, + GPIO_125, + GPIO_126, + GPIO_127, + GPIO_128, + GPIO_129, + GPIO_130, + GPIO_131, + GPIO_132, + GPIO_133, + GPIO_134, + GPIO_135, + GPIO_136, + GPIO_137, + GPIO_138, + GPIO_139, + GPIO_140, + GPIO_141, + GPIO_142, + GPIO_143, + GPIO_144, + GPIO_145, + GPIO_146, + GPIO_147, + GPIO_148, + GPIO_149, + GPIO_150, + GPIO_151, + GPIO_152, + GPIO_153, + GPIO_154, + GPIO_155, + GPIO_156, + GPIO_157, + GPIO_158, + GPIO_159, + GPIO_160, + GPIO_161, + GPIO_162, + GPIO_163, + GPIO_164, + GPIO_165, + GPIO_166, + GPIO_167, + GPIO_168, + GPIO_169, + GPIO_170, + GPIO_171, + GPIO_172, + GPIO_173, + GPIO_174, + GPIO_175, + GPIO_176, + GPIO_177, + GPIO_178, + GPIO_179, + GPIO_180, + GPIO_181, + GPIO_182, + GPIO_183, + GPIO_184, + GPIO_185, + GPIO_186, + GPIO_187, + GPIO_188, + GPIO_189, + GPIO_190, + GPIO_191, + GPIO_192, + GPIO_193, + GPIO_194, + GPIO_195, + GPIO_196, + GPIO_197, + GPIO_198, + GPIO_199, + GPIO_200, + GPIO_201, + GPIO_202, + GPIO_203, + GPIO_204, + GPIO_205, + GPIO_206, + GPIO_207, + GPIO_208, + GPIO_209, + GPIO_210, + GPIO_211, + GPIO_212, + GPIO_213, + GPIO_214, + GPIO_215, + GPIO_216, + GPIO_217, + GPIO_218, + GPIO_219, + GPIO_220, + GPIO_221, + GPIO_222, + GPIO_223, + GPIO_224, + GPIO_225, + GPIO_226, + GPIO_227, + GPIO_228, + GPIO_229, + MAX_GPIO_NO +} GPIO_COUNT; + +typedef struct _GPIO_SETTINGS +{ + u8 select; + u8 type; + u8 value; + u8 NonGpioGevent; +} GPIO_SETTINGS; + +GPIO_SETTINGS gpio_table[]= +{ + {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT}, + {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT}, + {GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT}, + {GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT}, + {GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT}, + {GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT}, + {GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT}, + {GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT}, + {GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT}, + {GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT}, + {GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT}, + {GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT}, + {GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT}, + {GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT}, + {GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT}, + {GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT}, + {GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT}, + {GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT}, + {GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT}, + {GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT}, + {GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT}, + {GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT}, + {GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT}, + {GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT}, + {GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT}, + {GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT}, + {GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT}, + {GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT}, + {GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT}, + {GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT}, + {GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT}, + {GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT}, + {GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT}, + {GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT}, + {GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT}, + {GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT}, + {GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT}, + {GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT}, + {GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT}, + {GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT}, + {GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT}, + {GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT}, + {GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT}, + {GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT}, + {GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT}, + {GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT}, + {GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT}, + {GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT}, + {GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT}, + {GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT}, + {GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT}, + {GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT}, + {GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT}, + {GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT}, + {GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT}, + {GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT}, + {GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT}, + {GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT}, + {GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT}, + {GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT}, + {GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT}, + {GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT}, + {GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT}, + {GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT}, + {GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT}, + {GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT}, + {GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT}, + {GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT}, + {GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT}, + {GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT}, + {GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT}, + {GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT}, + {GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT}, + {GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT}, + {GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT}, + {GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT}, + {GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT}, + {GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT}, + {GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT}, + {GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT}, + {GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT}, + {GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT}, + {GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT}, + {GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT}, + {GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT}, + {GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT}, + {GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT}, + {GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT}, + {GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT}, + {GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT}, + {GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT}, + {GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT}, + {GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT}, + {GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT}, + {GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT}, + {GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT}, + {GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT}, + {GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT}, + {GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT}, + {GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT}, + {GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT}, + {GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT}, + {GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT}, + {GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT}, + {GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT}, + {GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT}, + {GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT}, + {GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT}, + {GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT}, + {GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT}, + {GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT}, + {GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT}, + {GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT}, + {GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT}, + {GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT}, + {GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT}, + {GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT}, + {GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT}, + {GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT}, + {GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT}, + {GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT}, + {GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT}, + {GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT}, + {GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT}, + {GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT}, + {GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT}, + {GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT}, + {GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT}, + {GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT}, + {GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT}, + {GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT}, + {GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT}, + {GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT}, + {GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT}, + {GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT}, + {GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT}, + {GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT}, + {GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT}, + {GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT}, + {GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT}, + {GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT}, + {GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT}, + {GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT}, + {GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT}, + {GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT}, + {GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT}, + {GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT}, + {GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT}, + {GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT}, + {GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT}, + {GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT}, + {GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT}, + {GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT}, + {GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT}, + {GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT}, + {GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT}, + {GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT}, + {GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT}, + {GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT}, + {GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT}, + {GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT}, + {GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT}, + {GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT}, + {GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT}, + {GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT}, + {GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT}, + {GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT}, + {GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT}, + {GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT}, + {GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT}, + {GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT}, + {GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT}, + {GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT}, + {GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT}, + {GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT}, + {GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT}, + {GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT}, + {GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT}, + {GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT}, + {GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT}, + {GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT}, + {GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT}, + {GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT}, + {GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT}, + {GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT}, + {GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT}, + {GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT}, + {GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT}, + {GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT}, + {GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT}, + {GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT}, + {GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT}, + {GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT}, + {GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT}, + {GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT}, + {GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT}, + {GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT}, + {GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT}, + {GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT}, + {GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT}, + {GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT}, + {GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT}, + {GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT}, + {GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT}, + {GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT}, + {GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT}, + {GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT}, + {GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT}, + {GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT}, + {GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT}, + {GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT}, + {GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT}, + {GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT}, + {GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT}, + {GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT}, + {GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT}, + {GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT}, + {GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT}, + {GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT}, + {GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT}, + {GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT}, + {GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT}, + {GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT}, + {GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT}, + {GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT}, + {GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT}, + {GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT}, + {GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT}, + {GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT}, + {GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT}, +}; + +typedef enum _GEVENT_COUNT +{ + GEVENT_00=0x60, + GEVENT_01, + GEVENT_02, + GEVENT_03, + GEVENT_04, + GEVENT_05, + GEVENT_06, + GEVENT_07, + GEVENT_08, + GEVENT_09, + GEVENT_10, + GEVENT_11, + GEVENT_12, + GEVENT_13, + GEVENT_14, + GEVENT_15, + GEVENT_16, + GEVENT_17, + GEVENT_18, + GEVENT_19, + GEVENT_20, + GEVENT_21, + GEVENT_22, + GEVENT_23 +} GEVENT_COUNT; + +typedef struct _GEVENT_SETTINGS +{ + u8 EventEnable; // 0: Disable, 1: Enable + u8 SciTrig; // 0: Falling Edge, 1: Rising Edge + u8 SciLevl; // 0: Edge trigger, 1: Level Trigger + u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI + u8 SciS0En; // 0: Disable, 1: Enable + u8 SciMap; // 0000b->1111b + u8 SmiTrig; // 0: Active Low, 1: Active High + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 +} GEVENT_SETTINGS; + +GEVENT_SETTINGS gevent_table[] = +{ + {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL}, + {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL}, + {GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL}, + {GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL}, + {GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL}, + {GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL}, + {GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL}, + {GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL}, + {GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL}, + {GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL}, + {GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL}, + {GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL}, + {GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL}, + {GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL}, + {GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL}, + {GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL}, + {GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL}, + {GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL}, + {GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL}, + {GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL}, + {GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL}, + {GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL}, + {GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL}, + {GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL}, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c new file mode 100644 index 0000000..afd8c67 --- /dev/null +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include + + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb700[2]; +extern unsigned long sbdn_sb700; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb700[0]; + pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c new file mode 100644 index 0000000..9d10390 --- /dev/null +++ b/src/mainboard/amd/dinar/mainboard.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define ONE_MB 0x100000 +//#define SMBUS_IO_BASE 0x6000 + +void set_pcie_reset(void *nbconfig); +void set_pcie_dereset(void *nbconfig); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void *nbconfig) +{ +} + +/** + * Mainboard specific RD890 CIMx callback + * Release Resets to PCIe Links + * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie + */ +void set_pcie_dereset(void *nbconfig) +{ + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; + + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } +} + +uint64_t uma_memory_base, uma_memory_size; + +/************************************************* + * enable the dedicated function in dinar board. + *************************************************/ +static void dinar_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeOR () */ + /* + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + */ + sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + uma_memory_size = 512 * ONE_MB; + } else if (sys_mem >= 1024 * ONE_MB) { + uma_memory_size = 256 * ONE_MB; + } else { + uma_memory_size = 64 * ONE_MB; + } + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ + uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ +#endif + +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME("AMD DINAR Mainboard") + .enable_dev = dinar_enable, +}; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c new file mode 100644 index 0000000..b43080d --- /dev/null +++ b/src/mainboard/amd/dinar/mptable.c @@ -0,0 +1,180 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 bus_rd890[14]; +extern u8 bus_sb700[2]; +extern u32 bus_type[256]; +extern u32 sbdn_rd890; +extern u32 sbdn_sb700; + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicid_sb700; + u32 apicid_rd890; + device_t dev; + u32 dword; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + get_bus_conf(); + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. + dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + if (dev) { + /* Set sb700 IOAPIC ID */ + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb700, 0x20, dword); + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + + /* Set RS5650 IOAPIC ID */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_rd890, 0x20, dword); + } + + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) + + /* SMBUS */ + //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x2, 0x10); + + /* USB */ + /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ + /* EHCI hard-wired to 02h, corresponding to using INTB# */ + /* USB1 */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ + PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ + PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ + + /* USB2 */ + PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ + PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ + PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ + + /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ + PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + + /* on board NIC & Slot PCIE. */ + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13); + */ + + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h new file mode 100644 index 0000000..8265f87 --- /dev/null +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c new file mode 100644 index 0000000..9518691 --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include +#include + +#ifndef __PRE_RAM__ +#include +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h new file mode 100644 index 0000000..a4f4e1a --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +#define RD890_IOAPIC_ADDR 0xC8000000 +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c new file mode 100644 index 0000000..4cc1efd --- /dev/null +++ b/src/mainboard/amd/dinar/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /*inb, outb*/ +#include /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c new file mode 100644 index 0000000..6f3911a --- /dev/null +++ b/src/mainboard/amd/dinar/romstage.c @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpu/x86/bist.h" +#include "superio/smsc/sch4037/sch4037_early_init.c" +#include "superio/smsc/sio1036/sio1036_early_init.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "pc80/i8254.c" +#include "pc80/i8259.c" +#include "nb_cimx.h" +#include "sb_cimx.h" +#include "Platform.h" +#include + +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +u32 agesawrapper_amdinitmmio (void); +u32 agesawrapper_amdinitreset (void); +u32 agesawrapper_amdinitearly (void); +u32 agesawrapper_amdinitenv (void); +u32 agesawrapper_amdinitlate (void); +u32 agesawrapper_amdinitpost (void); +u32 agesawrapper_amdinitmid (void); + + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + if (!cpu_init_detectedx && boot_cpu()) { + + post_code(0x30); + + sch4037_early_init (CONFIG_SIO_PORT); + + /* Detect SMSC SIO1036 LPC Debug Card status */ + if (detect_sio1036_chip(0x4E)) { + /* Found SMSC SIO1036 LPC Debug Card */ + sio1036_early_init(0x4E); + } + + post_code(0x31); + uart_init(); + console_init(); + + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + } + + post_code(0x32); + val = agesawrapper_amdinitmmio(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); + } + + /* Halt if there was a built in self test failure */ + post_code(0x33); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + if(boot_cpu()) { + post_code(0x34); + sb_Poweron_Init(); + } + + post_code(0x35); + val = agesawrapper_amdinitreset(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); + } + + post_code(0x36); + val = agesawrapper_amdinitearly (); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); + } + + post_code(0x37); + nb_Poweron_Init(); + post_code(0x38); + nb_Ht_Init(); + + + post_code(0x39); + val = agesawrapper_amdinitpost (); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); + } + + post_code(0x40); + val = agesawrapper_amdinitenv (); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); + } + + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x43); + print_debug("Disabling cache as ram "); + disable_cache_as_ram(); + print_debug("done\n"); + + post_code(0x44); + copy_and_run(0); + + post_code(0x45); // Should never see this post code. +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c new file mode 100644 index 0000000..b2f3d17 --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - No sb_config.\n", __func__); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - Start.\n", __func__); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - %s - End.\n", __func__); +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h new file mode 100644 index 0000000..b405f0e --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_ From gerrit at coreboot.org Fri Feb 17 09:10:05 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 17 Feb 2012 09:10:05 +0100 Subject: [coreboot] Patch set updated for coreboot: 06edf50 SIO: Add smsc sio1036 superio References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/563 -gerrit commit 06edf5030bf5ad86db07a0922213d6d50d73553a Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc sio1036 superio Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1036/Makefile.inc | 21 ++++ src/superio/smsc/sio1036/chip.h | 34 +++++++ src/superio/smsc/sio1036/sio1036.h | 25 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 101 ++++++++++++++++++++ src/superio/smsc/sio1036/superio.c | 122 +++++++++++++++++++++++++ 7 files changed, 306 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index ddd5b96..d4f07ec 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,5 +40,7 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SIO1036 + bool config SUPERIO_SMSC_SCH4037 bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bfdc68e..d07afea 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,4 +29,5 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc new file mode 100644 index 0000000..4e48899 --- /dev/null +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c + diff --git a/src/superio/smsc/sio1036/chip.h b/src/superio/smsc/sio1036/chip.h new file mode 100644 index 0000000..abed430 --- /dev/null +++ b/src/superio/smsc/sio1036/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_SIO1036_CHIP_H +#define SUPERIO_SMSC_SIO1036_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_kbc1100_ops; + +struct superio_smsc_sio1036_config { + struct uart8250 com1; +}; + +#endif //SUPERIO_SMSC_SIO1036_CHIP_H + diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h new file mode 100644 index 0000000..cdd5a8b --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SIO1036_SP1 0 /* Com1 */ + +#define UART_POWER_DOWN (1 << 7) +#define LPT_POWER_DOWN (1 << 2) +#define IR_OUPUT_MUX (1 << 6) + diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c new file mode 100644 index 0000000..980e8c5 --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include "sio1036.h" + +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3F8 +#endif +static inline void sio1036_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static inline void sio1036_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static u8 detect_sio1036_chip(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + unsigned data; + sio1036_enter_conf_state (dev); + data = pnp_read_config (dev, 0x0D); + sio1036_exit_conf_state(dev); + /* detect smsc sio1036 chip */ + if (data == 0x82) { + /* Found SMSC SIO1036 chip */ + return 0; + } + else { + return -1; + }; +} + +static inline void sio1036_early_init(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + + if (detect_sio1036_chip(port) != 0) { + /* Not found SMSC SIO1036 */ + return; + } + sio1036_enter_conf_state (dev); + + /* Enable SMSC UART 0 */ + /* Valid configuration cycle */ + pnp_write_config (dev, 0x00, 0x28); + + /* PP power/mode/cr lock */ + pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN); + pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN); + + /*Auto power management*/ + pnp_write_config (dev, 0x07, 0x00 ); + + /*ECP FIFO threhod */ + pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX); + + /*GPIO direction register 2 */ + pnp_write_config (dev, 0x033, 0x00); + + /*UART Mode */ + pnp_write_config (dev, 0x0C, 0x02); + + /* GPIO polarity regisgter 2 */ + pnp_write_config (dev, 0x034, 0x00); + + /* Enable SMSC UART 0 */ + /*Set base io address */ + pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + + /* Set UART IRQ onto 0x04 */ + pnp_write_config (dev, 0x28, 0x04); + + sio1036_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c new file mode 100644 index 0000000..2522d92 --- /dev/null +++ b/src/superio/smsc/sio1036/superio.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC SIO1036 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sio1036.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sio1036_pnp_set_resources(device_t dev); +static void sio1036_pnp_enable_resources(device_t dev); +static void sio1036_pnp_enable(device_t dev); +static void sio1036_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sio1036_pnp_set_resources, + .enable_resources = sio1036_pnp_enable_resources, + .enable = sio1036_pnp_enable, + .init = sio1036_init, +}; + +static struct pnp_info pnp_dev_info[] = { + {}, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sio1036_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sio1036_init(device_t dev) +{ + struct superio_smsc_sio1036_config *conf = dev->chip_info; + struct resource *res0, *res1; + + + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + default: + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + From gerrit at coreboot.org Fri Feb 17 09:10:06 2012 From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com)) Date: Fri, 17 Feb 2012 09:10:06 +0100 Subject: [coreboot] Patch set updated for coreboot: 0295597 SIO: Add smsc/sch4037 superio support References: Message-ID: Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit 0295597c40c6069186d690651b91a85efefc7851 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 ++++ src/superio/smsc/sch4037/chip.h | 34 +++++++ src/superio/smsc/sch4037/sch4037.h | 34 +++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 69 ++++++++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++++++++++++++ 7 files changed, 285 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include +#include + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..8dff3b8 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..9c74062 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config(dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..eebcacd --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_SPEW, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} From gerrit at coreboot.org Fri Feb 17 10:49:26 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 10:49:26 +0100 Subject: [coreboot] New patch to review for coreboot: ce4abe3 lint: Add test for whitespace issues in the code References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/645 -gerrit commit ce4abe3fa98283a400b63760750e4df04e0ae204 Author: Patrick Georgi Date: Thu Feb 16 20:28:42 2012 +0100 lint: Add test for whitespace issues in the code So far it tests for trailing whitespace. "Upstream" files (bison/flex's .?_shipped, kconfig, vendorcode) are ignored. Change-Id: I7af1954d537fd05f06cd210ac130dac87892159b Signed-off-by: Patrick Georgi --- util/lint/lint-003-whitespace | 39 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/util/lint/lint-003-whitespace b/util/lint/lint-003-whitespace new file mode 100755 index 0000000..fe305bf --- /dev/null +++ b/util/lint/lint-003-whitespace @@ -0,0 +1,39 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Patrick Georgi +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# DESCR: Check for superfluous whitespace in the tree + +LC_ALL=C export LC_ALL +find src util -name .svn -type d -prune -o \ + -name .git -type d -prune -o \ + -name README -prune -o \ + -name LICENSE -prune -o \ + -name TODO -prune -o \ + -name COPYING -prune -o \ + -name \*.txt -prune -o \ + -name microcode-\*.h -prune -o \ + -name \*.?_shipped -prune -o \ + -name \*.[18] -prune -o \ + -name kconfig -type d -prune -o \ + -name romcc -type d -prune -o \ + -name crossgcc -type d -prune -o \ + -name vendorcode -type d -prune -o \ + -type f -exec \ + grep -l "[[:space:]][[:space:]]*$" {} + | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," + From gerrit at coreboot.org Fri Feb 17 10:49:26 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 10:49:26 +0100 Subject: [coreboot] New patch to review for coreboot: 924a34d Remove whitespace. References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/646 -gerrit commit 924a34d608c3420398947661f1412cb443274a4f Author: Patrick Georgi Date: Thu Feb 16 20:44:20 2012 +0100 Remove whitespace. Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi --- src/cpu/amd/agesa/family12/Kconfig | 6 +- src/cpu/amd/agesa/family12/Makefile.inc | 12 ++-- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/via/car/cache_as_ram.inc | 2 +- src/cpu/x86/32bit/entry32.inc | 4 +- src/lib/uart8250.c | 2 +- src/mainboard/amd/inagua/cmos.layout | 10 +- src/mainboard/amd/south_station/BiosCallOuts.c | 12 ++-- src/mainboard/amd/south_station/BiosCallOuts.h | 2 +- src/mainboard/amd/south_station/PlatformGnbPcie.c | 18 ++-- .../amd/south_station/PlatformGnbPcieComplex.h | 22 +++--- src/mainboard/amd/south_station/buildOpts.c | 16 ++-- src/mainboard/amd/south_station/cmos.layout | 10 +- src/mainboard/amd/south_station/dimmSpd.c | 16 ++-- src/mainboard/amd/south_station/get_bus_conf.c | 18 ++-- src/mainboard/amd/south_station/mptable.c | 6 +- src/mainboard/amd/torpedo/cmos.layout | 10 +- src/mainboard/amd/torpedo/dsdt.asl | 2 +- src/mainboard/amd/union_station/BiosCallOuts.c | 12 ++-- src/mainboard/amd/union_station/BiosCallOuts.h | 2 +- src/mainboard/amd/union_station/PlatformGnbPcie.c | 18 ++-- .../amd/union_station/PlatformGnbPcieComplex.h | 22 +++--- src/mainboard/amd/union_station/buildOpts.c | 16 ++-- src/mainboard/amd/union_station/cmos.layout | 10 +- src/mainboard/amd/union_station/dimmSpd.c | 16 ++-- src/mainboard/amd/union_station/get_bus_conf.c | 18 ++-- src/mainboard/amd/union_station/mptable.c | 6 +- src/mainboard/asrock/939a785gmh/acpi/routing.asl | 8 +- src/mainboard/asrock/Kconfig | 2 +- src/mainboard/asrock/e350m1/cmos.layout | 10 +- src/mainboard/getac/p470/acpi/ec.asl | 8 +- src/mainboard/getac/p470/acpi/i945_pci_irqs.asl | 2 +- src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl | 2 +- src/mainboard/getac/p470/acpi/mainboard.asl | 2 +- src/mainboard/getac/p470/acpi/platform.asl | 10 +- src/mainboard/getac/p470/acpi/superio.asl | 8 +- src/mainboard/getac/p470/acpi/thermal.asl | 2 +- src/mainboard/getac/p470/cmos.layout | 2 +- src/mainboard/getac/p470/devicetree.cb | 8 +- src/mainboard/getac/p470/dsdt.asl | 2 +- src/mainboard/msi/ms7135/dsdt.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/Kconfig | 14 ++-- src/mainboard/siemens/sitemp_g1p1/acpi/event.asl | 2 +- src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl | 10 +- src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl | 8 +- src/mainboard/siemens/sitemp_g1p1/devicetree.cb | 4 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 80 ++++++++++---------- src/mainboard/wyse/s50/devicetree.cb | 2 +- src/northbridge/amd/agesa/family12/Makefile.inc | 4 +- src/northbridge/amd/agesa/family14/Makefile.inc | 2 +- src/northbridge/amd/amdfam10/Kconfig | 2 +- src/northbridge/amd/gx2/northbridgeinit.c | 6 +- src/southbridge/intel/i82801gx/Kconfig | 2 +- util/acpi/acpidump-all | 6 +- util/ifdtool/Makefile | 4 +- util/lint/lint-001-no-global-config-in-romstage | 2 +- util/lint/remccoms3.sed | 4 +- util/mkelfImage/configure.ac | 2 +- 58 files changed, 256 insertions(+), 256 deletions(-) diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index c53ee57..87e09d6 100755 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -61,9 +61,9 @@ config XIP_ROM_SIZE hex default 0x80000 depends on CPU_AMD_AGESA_FAMILY12 - + config HAVE_INIT_TIMER bool default y - depends on CPU_AMD_AGESA_FAMILY12 - + depends on CPU_AMD_AGESA_FAMILY12 + diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 5aa4127..4c7b2fd 100755 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -2,7 +2,7 @@ # # Copyright (c) 2011, Advanced Micro Devices, Inc. # All rights reserved. -# +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright @@ -10,10 +10,10 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived # from this software without specific prior written permission. -# +# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED # WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -24,9 +24,9 @@ # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +# #***************************************************************************** - + ramstage-y += chip_name.c driver-y += model_12_init.c diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 955aec9..4625da1 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -146,7 +146,7 @@ CAR_FAM10_out: #elif (CONFIG_MMCONF_BUS_NUMBER == 2) orl $(1 << 2), %eax #elif (CONFIG_MMCONF_BUS_NUMBER == 4) - orl $(2 << 2), %eax + orl $(2 << 2), %eax #elif (CONFIG_MMCONF_BUS_NUMBER == 8) orl $(3 << 2), %eax #elif (CONFIG_MMCONF_BUS_NUMBER == 16) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index aad2369..90e6d2b 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -182,7 +182,7 @@ clear_fixed_var_mtrr_out: movl %eax, %esp #ifdef CARTEST -testok: +testok: post_code(0x40) xorl %edx, %edx xorl %eax, %eax diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 740ea47..f74e1b8 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -6,8 +6,8 @@ .code32 - /* This is the GDT for the ROM stage part of coreboot. It - * is different from the RAM stage GDT which is defined in + /* This is the GDT for the ROM stage part of coreboot. It + * is different from the RAM stage GDT which is defined in * c_start.S */ diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index fe8ed70..261b90f 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -75,7 +75,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_rx_byte(base_port)); - + if (i) return inb(base_port + UART_RBR); else diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index 8315401..3b98cbb 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -1,18 +1,18 @@ #***************************************************************************** -# +# # This file is part of the coreboot project. -# +# # Copyright (C) 2011 Advanced Micro Devices, Inc. -# +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 3fb0e87..3cfd741 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } } - + return CalloutStatus; } @@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the + Update NextNodeOffset and BufferSize to include the size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; @@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) TempData8 &= 0x03; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - + Data8 |= BIT2+BIT3; Data8 &= ~BIT4; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h index 750b59d..f9201ce 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.h +++ b/src/mainboard/amd/south_station/BiosCallOuts.h @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index 8749e3d..07aee7d 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + } }; PCIe_DDI_DESCRIPTOR DdiList [] = { @@ -116,8 +116,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; @@ -125,10 +125,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); + ASSERT(FALSE); return; } - + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); @@ -136,7 +136,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - + LibAmdMemFill (BrazosPcieComplexListPtr, 0, sizeof (PCIe_COMPLEX_DESCRIPTOR), @@ -146,7 +146,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { 0, sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - + LibAmdMemFill (BrazosPcieDdiPtr, 0, sizeof (PCIe_DDI_DESCRIPTOR) * 2, @@ -160,7 +160,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index f35d8db..b51089f 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 63f12f0..f87522c 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /** * @file * @@ -55,13 +55,13 @@ #define INSTALL_FT1_SOCKET_SUPPORT TRUE #define INSTALL_AM3_SOCKET_SUPPORT FALSE -/* - * Agesa optional capabilities selection. +/* + * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE @@ -102,7 +102,7 @@ #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE @@ -219,10 +219,10 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/* - * Agesa configuration values selection. +/* + * Agesa configuration values selection. * Uncomment and specify the value for the configuration options - * needed by the system. + * needed by the system. */ #include "AGESA.h" #include "CommonReturns.h" diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index 8315401..3b98cbb 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -1,18 +1,18 @@ #***************************************************************************** -# +# # This file is part of the coreboot project. -# +# # Copyright (C) 2011 Advanced Micro Devices, Inc. -# +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/src/mainboard/amd/south_station/dimmSpd.c b/src/mainboard/amd/south_station/dimmSpd.c index 9da0e0e..2bd27d6 100644 --- a/src/mainboard/amd/south_station/dimmSpd.c +++ b/src/mainboard/amd/south_station/dimmSpd.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "Porting.h" #include "AGESA.h" #include "amdlib.h" @@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) UINT64 limit; address |= 1; // set read bit - + __outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 1, 0x1F); // clear error status __outbyte (iobase + 3, offset); // offset in eeprom @@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer) * * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid + * Optimization relies on autoincrement to avoid * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ @@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); if (error) return error; } - + return 0; } @@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; ioBase = 0xB00; setupFch (ioBase); diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index 4bc5b48..2d28023 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -69,22 +69,22 @@ void get_bus_conf(void) * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); + status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } - + sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 5c8ae5a..5242f69 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - + u32 dword; u8 byte; - + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ - + /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/amd/torpedo/cmos.layout b/src/mainboard/amd/torpedo/cmos.layout index 8315401..3b98cbb 100755 --- a/src/mainboard/amd/torpedo/cmos.layout +++ b/src/mainboard/amd/torpedo/cmos.layout @@ -1,18 +1,18 @@ #***************************************************************************** -# +# # This file is part of the coreboot project. -# +# # Copyright (C) 2011 Advanced Micro Devices, Inc. -# +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 2355e46..bc812e4 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -1066,7 +1066,7 @@ DefinitionBlock ( } } } - + Device (PS2K) { Name (_HID, EisaId ("PNP0303")) Name (_CRS, ResourceTemplate () { diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 3fb0e87..3cfd741 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -91,7 +91,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } } - + return CalloutStatus; } @@ -289,7 +289,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the + Update NextNodeOffset and BufferSize to include the size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; @@ -470,7 +470,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) TempData8 &= 0x03; TempData8 |= Data8; Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - + Data8 |= BIT2+BIT3; Data8 &= ~BIT4; TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); @@ -563,13 +563,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; @@ -586,7 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h index 750b59d..f9201ce 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.h +++ b/src/mainboard/amd/union_station/BiosCallOuts.h @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #ifndef _BIOS_CALLOUT_H_ #define _BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 59d31ef..b0389b8 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -86,7 +86,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + } }; PCIe_DDI_DESCRIPTOR DdiList [] = { @@ -118,8 +118,8 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 5 + sizeof (PCIe_DDI_DESCRIPTOR)) * 2; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; @@ -127,10 +127,10 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); + ASSERT(FALSE); return; } - + BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); @@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - + LibAmdMemFill (BrazosPcieComplexListPtr, 0, sizeof (PCIe_COMPLEX_DESCRIPTOR), @@ -148,7 +148,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { 0, sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - + LibAmdMemFill (BrazosPcieDdiPtr, 0, sizeof (PCIe_DDI_DESCRIPTOR) * 2, @@ -162,7 +162,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index f35d8db..b51089f 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -25,42 +25,42 @@ #include "amdlib.h" //GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced @@ -68,5 +68,5 @@ VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ); - + #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 48e18a6..20d667d 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /** * @file * @@ -55,13 +55,13 @@ #define INSTALL_FT1_SOCKET_SUPPORT TRUE #define INSTALL_AM3_SOCKET_SUPPORT FALSE -/* - * Agesa optional capabilities selection. +/* + * Agesa optional capabilities selection. * Uncomment and mark FALSE those features you wish to include in the build. * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE @@ -102,7 +102,7 @@ #define BLDOPT_REMOVE_HT_ASSIST TRUE #define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE #define BLDOPT_REMOVE_GFX_RECOVERY TRUE @@ -219,10 +219,10 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -/* - * Agesa configuration values selection. +/* + * Agesa configuration values selection. * Uncomment and specify the value for the configuration options - * needed by the system. + * needed by the system. */ #include "AGESA.h" #include "CommonReturns.h" diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index 8315401..3b98cbb 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -1,18 +1,18 @@ #***************************************************************************** -# +# # This file is part of the coreboot project. -# +# # Copyright (C) 2011 Advanced Micro Devices, Inc. -# +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/src/mainboard/amd/union_station/dimmSpd.c b/src/mainboard/amd/union_station/dimmSpd.c index 9da0e0e..2bd27d6 100644 --- a/src/mainboard/amd/union_station/dimmSpd.c +++ b/src/mainboard/amd/union_station/dimmSpd.c @@ -16,7 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include "Porting.h" #include "AGESA.h" #include "amdlib.h" @@ -55,7 +55,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) UINT64 limit; address |= 1; // set read bit - + __outbyte (iobase + 0, 0xFF); // clear error status __outbyte (iobase + 1, 0x1F); // clear error status __outbyte (iobase + 3, offset); // offset in eeprom @@ -112,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer) * * readspd - Read one or more SPD bytes from a DIMM. * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid + * Optimization relies on autoincrement to avoid * sending offset for every byte. * Reads 128 bytes in 7-8 ms at 400 KHz. */ @@ -131,7 +131,7 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); if (error) return error; } - + return 0; } @@ -154,11 +154,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress, ioBase; - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; ioBase = 0xB00; setupFch (ioBase); diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index 4bc5b48..2d28023 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -69,22 +69,22 @@ void get_bus_conf(void) * This is the call to AmdInitLate. It is really in the wrong place, conceptually, * but functionally within the coreboot model, this is the best place to make the * call. The logically correct place to call AmdInitLate is after PCI scan is done, - * after the decision about S3 resume is made, and before the system tables are - * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform - * specific entry point between the S3 resume decision point and the call to - * "write_tables", and the next platform specific entry points are the calls to - * the ACPI table write functions. The first of ose would seem to be the right - * place, but other table write functions, e.g. the PIRQ table write function, are + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are * called before the ACPI tables are written. This routine is called at the beginning * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ - status = agesawrapper_amdinitlate(); + status = agesawrapper_amdinitlate(); if(status) { printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); } - + sbdn_sb800 = 0; for (i = 0; i < 3; i++) { diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 5c8ae5a..5242f69 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -61,10 +61,10 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ - + u32 dword; u8 byte; - + ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); /* on board NIC & Slot PCIE. */ - + /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/asrock/939a785gmh/acpi/routing.asl b/src/mainboard/asrock/939a785gmh/acpi/routing.asl index fa3760e..fd02eac 100644 --- a/src/mainboard/asrock/939a785gmh/acpi/routing.asl +++ b/src/mainboard/asrock/939a785gmh/acpi/routing.asl @@ -32,12 +32,12 @@ Scope(\_SB) { /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - + Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, - + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices */ @@ -83,7 +83,7 @@ Scope(\_SB) { Package(){0x0009FFFF, 1, 0, 18 }, Package(){0x0009FFFF, 2, 0, 19 }, Package(){0x0009FFFF, 3, 0, 10 }, - + /* Bus 0, Dev A - PCIe internal ethernet */ Package(){0x000AFFFF, 0, 0, 18 }, Package(){0x000AFFFF, 1, 0, 19 }, @@ -146,7 +146,7 @@ Scope(\_SB) { Package(){0x0000FFFF, 2, 0, 16 }, Package(){0x0000FFFF, 3, 0, 17 }, }) - + Name(PS9, Package(){ /* PCIe slot - Hooked to PCIe x1 */ Package(){0x0000FFFF, 0, INTD, 0 }, diff --git a/src/mainboard/asrock/Kconfig b/src/mainboard/asrock/Kconfig index 1e4fff9..e6acd42 100644 --- a/src/mainboard/asrock/Kconfig +++ b/src/mainboard/asrock/Kconfig @@ -28,7 +28,7 @@ config BOARD_ASROCK_E350M1 endchoice -source "src/mainboard/asrock/939a785gmh/Kconfig" +source "src/mainboard/asrock/939a785gmh/Kconfig" source "src/mainboard/asrock/e350m1/Kconfig" config MAINBOARD_VENDOR diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index 8315401..3b98cbb 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -1,18 +1,18 @@ #***************************************************************************** -# +# # This file is part of the coreboot project. -# +# # Copyright (C) 2011 Advanced Micro Devices, Inc. -# +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. -# +# # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -# +# # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 6538b83..70faab2 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -151,7 +151,7 @@ Device(EC0) TRAP(0xc1) } } - + Method (_Q09, 0) { Notify(BAT0, 0x80) @@ -162,7 +162,7 @@ Device(EC0) { Notify(\_TZ.THRM, 0x80) } - + Method (_Q20, 0) { Notify(\_SB.ECO, 0x81) @@ -668,8 +668,8 @@ Scope(\_SB) } Return (0) } - - + + } } diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl index c78d7d6..b84acd9 100644 --- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl +++ b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * i945 */ diff --git a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl index 28b06a1..d9fba6b 100644 --- a/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl +++ b/src/mainboard/getac/p470/acpi/ich7_pci_irqs.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -/* This is board specific information: IRQ routing for the +/* This is board specific information: IRQ routing for the * 0:1e.0 PCI bridge of the ICH7 */ diff --git a/src/mainboard/getac/p470/acpi/mainboard.asl b/src/mainboard/getac/p470/acpi/mainboard.asl index 88ff8b4..396d8d8 100644 --- a/src/mainboard/getac/p470/acpi/mainboard.asl +++ b/src/mainboard/getac/p470/acpi/mainboard.asl @@ -40,7 +40,7 @@ Device (SLPB) Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) - + // Wake Name(_PRW, Package(){0x1d, 0x04}) } diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index eeaded8..01de2e4 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -53,9 +53,9 @@ Field(SMI1, AnyAcc, NoLock, Preserve) INFO, 1024 } -/* The _PIC method is called by the OS to choose between interrupt +/* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. - * + * * _PIC is called with a parameter of 0 for i8259 configuration and * with a parameter of 1 for Local Apic/IOAPIC configuration. */ @@ -119,7 +119,7 @@ Method(_WAK,1) // Notify PCI Express slots in case a card // was inserted while a sleep state was active. - + If (LEqual(RP1D, 0)) { Notify(\_SB.PCI0.RP01, 0) } @@ -132,13 +132,13 @@ Method(_WAK,1) Notify(\_SB.PCI0.RP04, 0) } - // Are we coming from S3? + // Are we coming from S3? If (LEqual(Arg0, 3)) { TRAP(0xeb) TRAP(0x46) } - // Are we coming from S4? + // Are we coming from S4? If (LEqual(Arg0, 4)) { Notify(SLPB, 0x02) If (DTSE) { diff --git a/src/mainboard/getac/p470/acpi/superio.asl b/src/mainboard/getac/p470/acpi/superio.asl index e84c204..6614016 100644 --- a/src/mainboard/getac/p470/acpi/superio.asl +++ b/src/mainboard/getac/p470/acpi/superio.asl @@ -136,7 +136,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) // Why? CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQL) - + Store (READ(0, 0x24, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) @@ -291,7 +291,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQL) - + Store (READ(0, 0x25, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) @@ -445,7 +445,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) // Why? CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQL) - + Store (READ(0, 0x1b, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) @@ -597,7 +597,7 @@ Device (SIO1) CreateByteField(RSRC, 0x05, IORH) // Why? CreateByteField(RSRC, \_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQL) - + Store (READ(0, 0x1c, 0xff), Local0) And (Local0, 0xc0, Local1) ShiftRight(Local1, 0x06, Local1) diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 93bdbcf..e5ea75e 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -26,7 +26,7 @@ Scope (\_TZ) ThermalZone (THRM) { // TODO These could/should be read from the - // GNVS area, so they can be controlled by + // GNVS area, so they can be controlled by // coreboot Name(TC1V, 0x00) Name(TC2V, 0x0a) diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index 130f1ce..c879078 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -1,6 +1,6 @@ # # This file is part of the coreboot project. -# +# # Copyright (C) 2007-2008 coresystems GmbH # # This program is free software; you can redistribute it and/or diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 9b376c7..bdd959e 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -1,6 +1,6 @@ ## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007-2009 coresystems GmbH ## ## This program is free software; you can redistribute it and/or @@ -27,7 +27,7 @@ chip northbridge/intel/i945 end end - device pci_domain 0 on + device pci_domain 0 on device pci 00.0 on end # host bridge # autodetect: #device pci 01.0 off end # i945 PCIe root port @@ -74,10 +74,10 @@ chip northbridge/intel/i945 device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on chip southbridge/ti/pcixx12 - + end end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio + #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/smsc/fdc37n972 diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index f6c6cf7..9728ea2 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -42,7 +42,7 @@ DefinitionBlock( // mainboard specific devices #include "acpi/mainboard.asl" - + // Thermal Zone #include "acpi/thermal.asl" diff --git a/src/mainboard/msi/ms7135/dsdt.asl b/src/mainboard/msi/ms7135/dsdt.asl index 090a3b2..3e3fbfb 100644 --- a/src/mainboard/msi/ms7135/dsdt.asl +++ b/src/mainboard/msi/ms7135/dsdt.asl @@ -260,7 +260,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1) Store (ETBA, HPT) Return (CRS) } - + } #endif } diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index 983e94c..1bc7406 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -23,12 +23,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select QRANK_DIMM_SUPPORT select SET_FIDVID select GFXUMA - select EXT_CONF_SUPPORT - + select EXT_CONF_SUPPORT + config MAINBOARD_DIR string default siemens/sitemp_g1p1 - + config LINT01_CONVERSION bool default y @@ -48,7 +48,7 @@ config MAX_CPUS config MAX_PHYSICAL_CPUS int default 1 - + config SB_HT_CHAIN_ON_BUS0 int default 1 @@ -68,13 +68,13 @@ config IRQ_SLOT_COUNT config IOMMU bool default n - + config HW_SCRUBBER bool default n - + config ECC_MEMORY bool default n - + endif # BOARD_SIEMENS_SITEMP_G1P1 diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl index 546f31b..3f3fed2 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl @@ -18,7 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /* Supported sleep states: */ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl index 1115388..82df7fe 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl @@ -18,7 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + /* Routing is in System Bus scope */ Scope(\_SB) { @@ -55,7 +55,7 @@ Scope(\_SB) Package(){0x0013FFFF, 3, 0, 19 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, @@ -162,9 +162,9 @@ Scope(\_SB) Package(){0x004FFFF, 0, \_SB.PCI0.LPC0.INTE, 0 }, Package(){0x004FFFF, 1, \_SB.PCI0.LPC0.INTF, 0 }, Package(){0x004FFFF, 2, \_SB.PCI0.LPC0.INTG, 0 }, - Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 }, + Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 }, }) - + Name(AP2P, Package(){ /* PCI slots: slot 0 behind Dev14, Fun4. */ Package(){0x0005FFFF, 0, 0, 21 }, // Phoenix does it @@ -174,5 +174,5 @@ Scope(\_SB) Package(){0x0004FFFF, 2, 0, 22 }, Package(){0x0004FFFF, 3, 0, 23 }, }) - + } diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl index 1d36f27..035e7d4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * */ - + /* THERMAL */ Scope(\_TZ) { Name (KELV, 2732) @@ -51,7 +51,7 @@ Scope(\_TZ) { /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ } } - + // Processors used for active cooling Method (_PSL, 0, Serialized) { @@ -60,7 +60,7 @@ Scope(\_TZ) { } Return (Package() {\_PR.CPU0}) } - + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ Return (Add (THOT, KELV)) @@ -96,4 +96,4 @@ Scope(\_TZ) { } } /* end of _TMP */ } /* end of TZ00 */ -} \ No newline at end of file +} diff --git a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb index adbe757..6f068e4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb +++ b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb @@ -15,7 +15,7 @@ chip northbridge/amd/amdk8/root_complex end end device pci_domain 0 on - subsystemid 0x110a 0x4076 inherit + subsystemid 0x110a 0x4076 inherit chip northbridge/amd/amdk8 device pci 18.0 on # southbridge chip southbridge/amd/rs690 @@ -24,7 +24,7 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 5.0 on # Internal Graphics 0x791F end - device pci 5.2 on # + device pci 5.2 on # end end device pci 2.0 on # PCIE P2P bridge 0x7913 (external GFX-port0) diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index f4752af..8ad0f82 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -37,8 +37,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(UOM7, 2) Name(UOM8, 6) Name(UOM9, 6) - - Name(DSEN, 1) // Display Output Switching Enable + + Name(DSEN, 1) // Display Output Switching Enable // Power notification /* PIC IRQ mapping registers, C00h-C01h */ @@ -252,13 +252,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) PCBA, 32, MPEN, 8 } - + Name (IOLM,0xe0000000) - -#include "acpi/platform.asl" + +#include "acpi/platform.asl" Scope(\_SB) { - + /* PCIe Configuration Space for 16 busses */ OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */ Field(PCFG, ByteAcc, NoLock, Preserve) { @@ -286,7 +286,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) ,14, P92E, 1, /* Port92 decode enable */ } - + OperationRegion(BAR5, SystemMemory, STB5, 0x1000) Field(BAR5, AnyAcc, NoLock, Preserve) { @@ -359,7 +359,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) P3PR, 1, } } -#include "acpi/event.asl" +#include "acpi/event.asl" #include "acpi/routing.asl" #include "acpi/usb.asl" @@ -367,7 +367,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Scope(\_SB) { /* Start \_SB scope */ - + #include "acpi/globutil.asl" Device(PWRB) { /* Start Power button device */ @@ -386,16 +386,16 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) - } + } Method(_STA, 0) { /* DBGO("\\_SB\\PCI0\\_STA\n") */ Return(0x0B) /* Status is visible */ } - + Device (MEMR) { Name (_HID, EisaId ("PNP0C02")) @@ -432,18 +432,18 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) If(PCIF){ Return(APR0) } /* APIC mode */ Return (PR0) /* PIC Mode */ } /* end _PRT */ - + OperationRegion (BAR1, PCI_Config, 0x14, 0x04) Field (BAR1, ByteAcc, NoLock, Preserve) { Z009, 32 } - + /* Describe the Northbridge devices */ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ - + /* The internal GFX bridge */ Device(AGPB) { Name(_ADR, 0x00010000) @@ -494,7 +494,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PCIF){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -520,7 +520,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) /* PCI slot 1 */ Device(PIBR) { Name(_ADR, 0x00140004) - Name(_PRW, Package() {4, 5}) // Phoenix doeas it so + Name(_PRW, Package() {4, 5}) // Phoenix doeas it so Method(_PRT, 0) { If(PCIF){ Return(AP2P) } /* APIC Mode */ Return (PCIB) /* PIC Mode */ @@ -530,7 +530,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) /* Describe the Southbridge devices */ Device(SATA) { Name(_ADR, 0x00120000) -#include "acpi/sata.asl" +#include "acpi/sata.asl" } /* end SATA */ Device(UOH1) { @@ -608,18 +608,18 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) } } /* end AZHD */ - Device(LPC0) + Device(LPC0) { Name (_ADR, 0x00140003) Mutex (PSMX, 0x00) - + /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) Field(PRQM, ByteAcc, NoLock, Preserve) { PRQI, 0x00000008, PRQD, 0x00000008, /* Offset: 1h */ } - + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { PINA, 0x00000008, /* Index 0 */ PINB, 0x00000008, /* Index 1 */ @@ -632,7 +632,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) PING, 0x00000008, /* Index B */ PINH, 0x00000008, /* Index C */ } - + Method(CIRQ, 0x00, NotSerialized) { Store(0, PINA) @@ -653,11 +653,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(IRQP, ResourceTemplate(){ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7} }) - + Name(PITF, ResourceTemplate(){ IRQ(Level,ActiveLow,Exclusive){9} - }) - + }) + Device(INTA) { Name(_HID, EISAID("PNP0C0F")) Name(_UID, 1) @@ -679,7 +679,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) } /* Method(_SB.INTA._PRS) */ Method(_CRS ,0) { - Store (IRQB, Local0) // + Store (IRQB, Local0) // CreateWordField(Local0, 0x1, IRQ0) ShiftLeft(1, PINA, IRQ0) Return(Local0) @@ -725,7 +725,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) /* Use lowest available IRQ */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) - Store(Local0, PINB) + Store(Local0, PINB) } /* End Method(_SB.INTB._SRS) */ } /* End Device(INTB) */ @@ -761,7 +761,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) /* Use lowest available IRQ */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) - Store(Local0, PINC) + Store(Local0, PINC) } /* End Method(_SB.INTC._SRS) */ } /* End Device(INTC) */ @@ -804,7 +804,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Device(INTE) { Name(_HID, EISAID("PNP0C0F")) Name(_UID, 5) - + Method(_STA, 0) { if (PINE) { Return(0x0B) /* sata is invisible */ @@ -817,7 +817,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Store(0, PINE) } /* End Method(_SB.INTE._DIS) */ - Method(_PRS ,0) { + Method(_PRS ,0) { Return(IRQB) // Return(IRQP) } @@ -944,7 +944,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ } /* End Device(INTH) */ - + /* Real Time Clock Device */ Device(RTC0) { @@ -1000,7 +1000,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ Name(_CRS, ResourceTemplate() { IO(Decode16, 0x00F0, 0x00F0, 1, 0x10) - IRQ (Edge, ActiveHigh, Exclusive, ) {13} + IRQ (Edge, ActiveHigh, Exclusive, ) {13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ @@ -1018,7 +1018,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Return(CRS) } } - + Device (KBC0) { Name (_HID, EisaId ("PNP0303")) @@ -1039,7 +1039,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) IRQ (Edge, ActiveHigh, Exclusive, ) {1} }) } - + Device (MSE0) { Name (_HID, EisaId ("PNP0F13")) @@ -1054,7 +1054,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00140005) Name (_PRW, Package (0x02) { - 0x0C, + 0x0C, 0x04 }) } /* end Ac97audio */ @@ -1063,7 +1063,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00140006) Name (_PRW, Package (0x02) { - 0x0C, + 0x0C, 0x04 }) } /* end Ac97modem */ @@ -1183,7 +1183,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) CreateDWordField(CRES, ^EMM2._MIN, EM2B) CreateDWordField(CRES, ^EMM2._MAX, EM2E) CreateDWordField(CRES, ^EMM2._LEN, EM2L) - + Store(TOM1, EM2B) Subtract(IOLM, 1, EM2E) Subtract(IOLM, TOM1, EM2L) @@ -1223,9 +1223,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) SCMD, 8, /* SMBUS shaow cmd */ SEVT, 8, /* SMBUS slave event */ SDAT, 8, /* SMBUS slave data */ - SMK1, 8, - SLMC, 8, - RADD, 8, + SMK1, 8, + SLMC, 8, + RADD, 8, SADD, 8 } diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb index d43b81e..cb30e43 100644 --- a/src/mainboard/wyse/s50/devicetree.cb +++ b/src/mainboard/wyse/s50/devicetree.cb @@ -20,7 +20,7 @@ ## chip northbridge/amd/gx2 - device pci_domain 0 on + device pci_domain 0 on device pci 1.0 on end # Geode GX2 Host Bridge device pci 1.1 on end # Geode GX2 Graphics Processor chip southbridge/amd/cs5536 diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc index 3bda8d5..8f0fe0d 100755 --- a/src/northbridge/amd/agesa/family12/Makefile.inc +++ b/src/northbridge/amd/agesa/family12/Makefile.inc @@ -16,7 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # - + driver-y += northbridge.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl \ No newline at end of file +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index 899d517..d3a125c 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -16,5 +16,5 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # - + driver-y += northbridge.c diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 74e0ff4..a14339e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -119,5 +119,5 @@ config SVI_HIGH_FREQ help Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. - + source src/northbridge/amd/amdfam10/root_complex/Kconfig diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index e55efcb..37fcf7e 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -335,7 +335,7 @@ static void GLPCIInit(void) /* we are ignoring the 5530 case for now, and perhaps forever. */ /* 553X NB Init */ - + /* Arbiter setup */ msrnum = GLPCI_ARB; msr = rdmsr(msrnum); @@ -404,7 +404,7 @@ static void ClockGatingInit(void) static void GeodeLinkPriority(void) { msr_t msr = { 0, 0 }; - + struct msrinit *prio = GeodeLinkPriorityTable; int i; @@ -426,7 +426,7 @@ static void GeodeLinkPriority(void) static uint64_t getShadow(void) { msr_t msr = { 0, 0 }; - + msr = rdmsr(GLIU0_P2D_SC_0); return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a6bd202..3550954 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -36,7 +36,7 @@ config EHCI_DEBUG_OFFSET config USBDEBUG_DEFAULT_PORT int - default 1 + default 1 config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/util/acpi/acpidump-all b/util/acpi/acpidump-all index fe10e9d..8550e5b 100755 --- a/util/acpi/acpidump-all +++ b/util/acpi/acpidump-all @@ -18,11 +18,11 @@ rm -rf out mkdir out - + # walk through all ACPI tables with their addresses -# example: +# example: # RSDT @ 0xcf6794ba -# we can not just dump the tables by their names because some +# we can not just dump the tables by their names because some # machines have double ACPI tables acpidump | grep "@ 0x" | while read line diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index fc8581f..144028e 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -23,7 +23,7 @@ CC = gcc INSTALL = /usr/bin/install PREFIX = /usr/local CFLAGS = -O2 -g -Wall -W -LDFLAGS = +LDFLAGS = OBJS = ifdtool.o @@ -47,7 +47,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 -.PHONY: all clean distclean dep +.PHONY: all clean distclean dep -include .dependencies diff --git a/util/lint/lint-001-no-global-config-in-romstage b/util/lint/lint-001-no-global-config-in-romstage index ae4d6a4..0c6f403 100755 --- a/util/lint/lint-001-no-global-config-in-romstage +++ b/util/lint/lint-001-no-global-config-in-romstage @@ -22,7 +22,7 @@ DEFINES=`grep "#define" src/mainboard/*/*/romstage.c |sed 's,.*#define[\t ]\([^\ SCANBUCKET=`mktemp` LC_ALL=C export LC_ALL find src -name .svn -type d -prune -o -name mainboard -type d -prune -o -name examples -type d -prune -o -type f -exec sed -nf `dirname $0`/remccoms3.sed {} + > $SCANBUCKET - + for define in $DEFINES; do if [ `egrep -c "([^_A-Za-z0-9]$define[^_A-Za-z0-9]|^$define[^_A-Za-z0-9]|[^_A-Za-z0-9]$define\$)" $SCANBUCKET` -gt 0 ]; then echo "$define is defined in mainboard(s) and used elsewhere" diff --git a/util/lint/remccoms3.sed b/util/lint/remccoms3.sed index 477a5ea..429d3bd 100644 --- a/util/lint/remccoms3.sed +++ b/util/lint/remccoms3.sed @@ -43,7 +43,7 @@ s,"[^"]*",,g s,\n\(.[^\"]*\).*,\1, x s,.[^\"]*,, - + /^"/b break /^\\/{ H @@ -69,7 +69,7 @@ s,"[^"]*",,g s,\n\(.[^\']*\).*,\1, x s,.[^\']*,, - + /^'/b break /^\\/{ H diff --git a/util/mkelfImage/configure.ac b/util/mkelfImage/configure.ac index a7fc37e..af0fe19 100644 --- a/util/mkelfImage/configure.ac +++ b/util/mkelfImage/configure.ac @@ -203,7 +203,7 @@ rm -f conftest*]) if test $libc_cv_fno_stack_protector = yes; then I386_CFLAGS="$I386_CFLAGS -fno-stack-protector" IA64_CFLAGS="$IA64_CFLAGS -fno-stack-protector" - + fi AC_SUBST(libc_cv_fno_stack_protector) From gerrit at coreboot.org Fri Feb 17 11:24:06 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 11:24:06 +0100 Subject: [coreboot] New patch to review for coreboot: 23defd9 Rename i945 ACPI files to not carry an i945_ prefix References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/647 -gerrit commit 23defd9637fb9791dc5c7cdadc847f2bc7698c1f Author: Patrick Georgi Date: Thu Feb 16 18:58:46 2012 +0100 Rename i945 ACPI files to not carry an i945_ prefix In the spirit of the earlier renames. Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff Signed-off-by: Patrick Georgi --- src/northbridge/intel/i945/acpi/hostbridge.asl | 240 +++++++++++++++ src/northbridge/intel/i945/acpi/i945.asl | 6 +- .../intel/i945/acpi/i945_hostbridge.asl | 240 --------------- src/northbridge/intel/i945/acpi/i945_igd.asl | 324 -------------------- src/northbridge/intel/i945/acpi/i945_peg.asl | 47 --- src/northbridge/intel/i945/acpi/igd.asl | 324 ++++++++++++++++++++ src/northbridge/intel/i945/acpi/peg.asl | 47 +++ 7 files changed, 614 insertions(+), 614 deletions(-) diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl new file mode 100644 index 0000000..a76d8e2 --- /dev/null +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) // 0:0.0 + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x40), // EPBAR + EPEN, 1, // Enable + , 11, // + EPBR, 20, // EPBAR + + Offset (0x44), // MCHBAR + MHEN, 1, // Enable + , 13, // + MHBR, 18, // MCHBAR + + Offset (0x48), // PCIe BAR + PXEN, 1, // Enable + PXSZ, 2, // BAR size + , 23, // + PXBR, 6, // PCIe BAR + + Offset (0x4c), // DMIBAR + DMEN, 1, // Enable + , 11, // + DMBR, 20, // DMIBAR + + // ... + + Offset (0x90), // PAM0 + , 4, + PM0H, 2, + , 2, + Offset (0x91), // PAM1 + PM1L, 2, + , 2, + PM1H, 2, + , 2, + Offset (0x92), // PAM2 + PM2L, 2, + , 2, + PM2H, 2, + , 2, + Offset (0x93), // PAM3 + PM3L, 2, + , 2, + PM3H, 2, + , 2, + Offset (0x94), // PAM4 + PM4L, 2, + , 2, + PM4H, 2, + , 2, + Offset (0x95), // PAM5 + PM5L, 2, + , 2, + PM5H, 2, + , 2, + Offset (0x96), // PAM6 + PM6L, 2, + , 2, + PM6H, 2, + , 2, + + Offset (0x9c), // Top of Low Used Memory + , 3, + TLUD, 5, + + Offset (0xa0), // Top of Used Memory + TOM, 16, + } + +} + + +// Current Resource Settings + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) + }) + + // Find PCI resource area in MCRS + CreateDwordField(MCRS, PM01._MIN, PMIN) + CreateDwordField(MCRS, PM01._MAX, PMAX) + CreateDwordField(MCRS, PM01._LEN, PLEN) + + // Fix up PCI memory region: + // Enter actual TOLUD. The TOLUD register contains bits 27-31 of + // the top of memory address. + ShiftLeft (^MCHC.TLUD, 27, PMIN) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/i945_pci_irqs.asl" + + diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 9511925..f5f4aae 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -#include "../../../northbridge/intel/i945/acpi/i945_hostbridge.asl" +#include "../../../northbridge/intel/i945/acpi/hostbridge.asl" #include "../../../northbridge/intel/i945/i945.h" /* PCI Device Resource Consumption */ @@ -77,10 +77,10 @@ Device (PDRC) } // PCIe graphics port 0:1.0 -#include "../../../northbridge/intel/i945/acpi/i945_peg.asl" +#include "../../../northbridge/intel/i945/acpi/peg.asl" // Integrated graphics 0:2.0 -#include "../../../northbridge/intel/i945/acpi/i945_igd.asl" +#include "../../../northbridge/intel/i945/acpi/igd.asl" Scope (\) { diff --git a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl deleted file mode 100644 index a76d8e2..0000000 --- a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl +++ /dev/null @@ -1,240 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_ADR, 0) -Name(_BBN, 0) - -Device (MCHC) -{ - Name(_ADR, 0x00000000) // 0:0.0 - - OperationRegion(MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 20, // EPBAR - - Offset (0x44), // MCHBAR - MHEN, 1, // Enable - , 13, // - MHBR, 18, // MCHBAR - - Offset (0x48), // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 6, // PCIe BAR - - Offset (0x4c), // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 20, // DMIBAR - - // ... - - Offset (0x90), // PAM0 - , 4, - PM0H, 2, - , 2, - Offset (0x91), // PAM1 - PM1L, 2, - , 2, - PM1H, 2, - , 2, - Offset (0x92), // PAM2 - PM2L, 2, - , 2, - PM2H, 2, - , 2, - Offset (0x93), // PAM3 - PM3L, 2, - , 2, - PM3H, 2, - , 2, - Offset (0x94), // PAM4 - PM4L, 2, - , 2, - PM4H, 2, - , 2, - Offset (0x95), // PAM5 - PM5L, 2, - , 2, - PM5H, 2, - , 2, - Offset (0x96), // PAM6 - PM6L, 2, - , 2, - PM6H, 2, - , 2, - - Offset (0x9c), // Top of Low Used Memory - , 3, - TLUD, 5, - - Offset (0xa0), // Top of Used Memory - TOM, 16, - } - -} - - -// Current Resource Settings - -Method (_CRS, 0, Serialized) -{ - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) - - // Fix up PCI memory region: - // Enter actual TOLUD. The TOLUD register contains bits 27-31 of - // the top of memory address. - ShiftLeft (^MCHC.TLUD, 27, PMIN) - Add(Subtract(PMAX, PMIN), 1, PLEN) - - Return (MCRS) -} - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/i945_pci_irqs.asl" - - diff --git a/src/northbridge/intel/i945/acpi/i945_igd.asl b/src/northbridge/intel/i945/acpi/i945_igd.asl deleted file mode 100644 index a6804ad..0000000 --- a/src/northbridge/intel/i945/acpi/i945_igd.asl +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Device (GFX0) -{ - Name (_ADR, 0x00020000) - - /* Display Output Switching */ - Method (_DOS, 1) - { - /* Windows 2000 and Windows XP call _DOS to enable/disable - * Display Output Switching during init and while a switch - * is already active - */ - Store (And(Arg0, 7), DSEN) - } - - /* We try to support as many i945 systems as possible, - * so keep the number of DIDs flexible. - */ - Method (_DOD, 0) - { - If (LEqual(NDID, 1)) { - Name(DOD1, Package() { - 0xffffffff - }) - Store (Or(0x00010000, DID1), Index(DOD1, 0)) - Return(DOD1) - } - - If (LEqual(NDID, 2)) { - Name(DOD2, Package() { - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID2), Index(DOD2, 0)) - Store (Or(0x00010000, DID2), Index(DOD2, 1)) - Return(DOD2) - } - - If (LEqual(NDID, 3)) { - Name(DOD3, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID3), Index(DOD3, 0)) - Store (Or(0x00010000, DID3), Index(DOD3, 1)) - Store (Or(0x00010000, DID3), Index(DOD3, 2)) - Return(DOD3) - } - - If (LEqual(NDID, 4)) { - Name(DOD4, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID4), Index(DOD4, 0)) - Store (Or(0x00010000, DID4), Index(DOD4, 1)) - Store (Or(0x00010000, DID4), Index(DOD4, 2)) - Store (Or(0x00010000, DID4), Index(DOD4, 3)) - Return(DOD4) - } - - If (LGreater(NDID, 4)) { - Name(DOD5, Package() { - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff - }) - Store (Or(0x00010000, DID5), Index(DOD5, 0)) - Store (Or(0x00010000, DID5), Index(DOD5, 1)) - Store (Or(0x00010000, DID5), Index(DOD5, 2)) - Store (Or(0x00010000, DID5), Index(DOD5, 3)) - Store (Or(0x00010000, DID5), Index(DOD5, 4)) - Return(DOD5) - } - - /* Some error happened, but we have to return something */ - Return (Package() {0x00000400}) - } - - Device(DD01) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID1, 0)) { - Return (1) - } Else { - Return (And(0xffff, DID1)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 1)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 1)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - Device(DD02) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID2, 0)) { - Return (2) - } Else { - Return (And(0xffff, DID2)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 2)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 2)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD03) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID3, 0)) { - Return (3) - } Else { - Return (And(0xffff, DID3)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 4)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD04) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID4, 0)) { - Return (4) - } Else { - Return (And(0xffff, DID4)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 8)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - - - Device(DD05) - { - /* Device Unique ID */ - Method(_ADR, 0, Serialized) - { - If(LEqual(DID5, 0)) { - Return (5) - } Else { - Return (And(0xffff, DID5)) - } - } - - /* Device Current Status */ - Method(_DCS, 0) - { - TRAP(1) - If (And(CSTE, 16)) { - Return (0x1f) - } - Return(0x1d) - } - - /* Query Device Graphics State */ - Method(_DGS, 0) - { - If (And(NSTE, 4)) { - Return(1) - } - Return(0) - } - - /* Device Set State */ - Method(_DSS, 1) - { - /* If Parameter Arg0 is (1 << 31) | (1 << 30), the - * display switch was completed - */ - If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { - Store (NSTE, CSTE) - } - } - } - -} - diff --git a/src/northbridge/intel/i945/acpi/i945_peg.asl b/src/northbridge/intel/i945/acpi/i945_peg.asl deleted file mode 100644 index bc7f8f7..0000000 --- a/src/northbridge/intel/i945/acpi/i945_peg.asl +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Device (PEGP) -{ - Name (_ADR, 0x00010000) - - // PCI Interrupt Routing. - Method (_PRT) - { - If (PICM) { - Return (Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } - }) - } Else { - Return (Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } - }) - } - - } -} - diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl new file mode 100644 index 0000000..a6804ad --- /dev/null +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -0,0 +1,324 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + /* Display Output Switching */ + Method (_DOS, 1) + { + /* Windows 2000 and Windows XP call _DOS to enable/disable + * Display Output Switching during init and while a switch + * is already active + */ + Store (And(Arg0, 7), DSEN) + } + + /* We try to support as many i945 systems as possible, + * so keep the number of DIDs flexible. + */ + Method (_DOD, 0) + { + If (LEqual(NDID, 1)) { + Name(DOD1, Package() { + 0xffffffff + }) + Store (Or(0x00010000, DID1), Index(DOD1, 0)) + Return(DOD1) + } + + If (LEqual(NDID, 2)) { + Name(DOD2, Package() { + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID2), Index(DOD2, 0)) + Store (Or(0x00010000, DID2), Index(DOD2, 1)) + Return(DOD2) + } + + If (LEqual(NDID, 3)) { + Name(DOD3, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID3), Index(DOD3, 0)) + Store (Or(0x00010000, DID3), Index(DOD3, 1)) + Store (Or(0x00010000, DID3), Index(DOD3, 2)) + Return(DOD3) + } + + If (LEqual(NDID, 4)) { + Name(DOD4, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID4), Index(DOD4, 0)) + Store (Or(0x00010000, DID4), Index(DOD4, 1)) + Store (Or(0x00010000, DID4), Index(DOD4, 2)) + Store (Or(0x00010000, DID4), Index(DOD4, 3)) + Return(DOD4) + } + + If (LGreater(NDID, 4)) { + Name(DOD5, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID5), Index(DOD5, 0)) + Store (Or(0x00010000, DID5), Index(DOD5, 1)) + Store (Or(0x00010000, DID5), Index(DOD5, 2)) + Store (Or(0x00010000, DID5), Index(DOD5, 3)) + Store (Or(0x00010000, DID5), Index(DOD5, 4)) + Return(DOD5) + } + + /* Some error happened, but we have to return something */ + Return (Package() {0x00000400}) + } + + Device(DD01) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID1, 0)) { + Return (1) + } Else { + Return (And(0xffff, DID1)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 1)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 1)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + Device(DD02) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID2, 0)) { + Return (2) + } Else { + Return (And(0xffff, DID2)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 2)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 2)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD03) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID3, 0)) { + Return (3) + } Else { + Return (And(0xffff, DID3)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 4)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD04) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID4, 0)) { + Return (4) + } Else { + Return (And(0xffff, DID4)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 8)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD05) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID5, 0)) { + Return (5) + } Else { + Return (And(0xffff, DID5)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 16)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + +} + diff --git a/src/northbridge/intel/i945/acpi/peg.asl b/src/northbridge/intel/i945/acpi/peg.asl new file mode 100644 index 0000000..bc7f8f7 --- /dev/null +++ b/src/northbridge/intel/i945/acpi/peg.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + // PCI Interrupt Routing. + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + } + + } +} + From gerrit at coreboot.org Fri Feb 17 11:24:07 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 11:24:07 +0100 Subject: [coreboot] New patch to review for coreboot: 87af06a Avoid ../../.. paths in ASL files References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/648 -gerrit commit 87af06a897dd92ae94e45f4b1d1f6d9719cf3edd Author: Patrick Georgi Date: Thu Feb 16 19:01:22 2012 +0100 Avoid ../../.. paths in ASL files The current directory is always part of the search path of cpp when using #include "..." Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52 Signed-off-by: Patrick Georgi --- src/northbridge/intel/i945/acpi/i945.asl | 8 ++++---- src/northbridge/intel/sch/acpi/sch.asl | 6 +++--- src/southbridge/intel/i82801gx/acpi/ich7.asl | 18 +++++++++--------- src/southbridge/intel/i82801gx/acpi/lpc.asl | 2 +- src/southbridge/intel/sch/acpi/lpc.asl | 2 +- src/southbridge/intel/sch/acpi/sch.asl | 16 ++++++++-------- 6 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index f5f4aae..47a6931 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -19,8 +19,8 @@ * MA 02110-1301 USA */ -#include "../../../northbridge/intel/i945/acpi/hostbridge.asl" -#include "../../../northbridge/intel/i945/i945.h" +#include "hostbridge.asl" +#include "../i945.h" /* PCI Device Resource Consumption */ Device (PDRC) @@ -77,10 +77,10 @@ Device (PDRC) } // PCIe graphics port 0:1.0 -#include "../../../northbridge/intel/i945/acpi/peg.asl" +#include "peg.asl" // Integrated graphics 0:2.0 -#include "../../../northbridge/intel/i945/acpi/igd.asl" +#include "igd.asl" Scope (\) { diff --git a/src/northbridge/intel/sch/acpi/sch.asl b/src/northbridge/intel/sch/acpi/sch.asl index 0a11851..5e0b3f8 100644 --- a/src/northbridge/intel/sch/acpi/sch.asl +++ b/src/northbridge/intel/sch/acpi/sch.asl @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -#include "../../../northbridge/intel/sch/acpi/hostbridge.asl" +#include "hostbridge.asl" /* PCI Device Resource Consumption */ Device (PDRC) @@ -76,10 +76,10 @@ Device (PDRC) } // PCIe graphics port 0:1.0 -#include "../../../northbridge/intel/sch/acpi/peg.asl" +#include "peg.asl" // Integrated graphics 0:2.0 -#include "../../../northbridge/intel/sch/acpi/igd.asl" +#include "igd.asl" Scope (\) { diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index ad5bdd0..43950c4 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -165,30 +165,30 @@ Scope(\) } // 0:1b.0 High Definition Audio (Azalia) -#include "../../../southbridge/intel/i82801gx/acpi/audio.asl" +#include "audio.asl" // PCI Express Ports -#include "../../../southbridge/intel/i82801gx/acpi/pcie.asl" +#include "pcie.asl" // USB -#include "../../../southbridge/intel/i82801gx/acpi/usb.asl" +#include "usb.asl" // PCI Bridge -#include "../../../southbridge/intel/i82801gx/acpi/pci.asl" +#include "pci.asl" // AC97 Audio and Modem -#include "../../../southbridge/intel/i82801gx/acpi/ac97.asl" +#include "ac97.asl" // LPC Bridge -#include "../../../southbridge/intel/i82801gx/acpi/lpc.asl" +#include "lpc.asl" // PATA -#include "../../../southbridge/intel/i82801gx/acpi/pata.asl" +#include "pata.asl" // SATA -#include "../../../southbridge/intel/i82801gx/acpi/sata.asl" +#include "sata.asl" // SMBus -#include "../../../southbridge/intel/i82801gx/acpi/smbus.asl" +#include "smbus.asl" diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index 3166a89..9138498 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -51,7 +51,7 @@ Device (LPCB) RCBA, 18, } - #include "../../../southbridge/intel/i82801gx/acpi/irqlinks.asl" + #include "irqlinks.asl" #include "acpi/ec.asl" diff --git a/src/southbridge/intel/sch/acpi/lpc.asl b/src/southbridge/intel/sch/acpi/lpc.asl index e847af4..788ac85 100644 --- a/src/southbridge/intel/sch/acpi/lpc.asl +++ b/src/southbridge/intel/sch/acpi/lpc.asl @@ -51,7 +51,7 @@ Device (LPCB) RCBA, 18, } -// #include "../../../southbridge/intel/sch/acpi/irqlinks.asl" +// #include "irqlinks.asl" #include "irqlinks.asl" #include "acpi/ec.asl" diff --git a/src/southbridge/intel/sch/acpi/sch.asl b/src/southbridge/intel/sch/acpi/sch.asl index c1e6e44..26f938e 100644 --- a/src/southbridge/intel/sch/acpi/sch.asl +++ b/src/southbridge/intel/sch/acpi/sch.asl @@ -139,27 +139,27 @@ Scope(\) } // 0:1b.0 High Definition Audio (Azalia) -#include "../../../southbridge/intel/sch/acpi/audio.asl" +#include "audio.asl" // PCI Express Ports -#include "../../../southbridge/intel/sch/acpi/pcie.asl" +#include "pcie.asl" // USB -#include "../../../southbridge/intel/sch/acpi/usb.asl" +#include "usb.asl" // PCI Bridge -#include "../../../southbridge/intel/sch/acpi/pci.asl" +#include "pci.asl" // AC97 Audio and Modem -#include "../../../southbridge/intel/sch/acpi/ac97.asl" +#include "ac97.asl" // LPC Bridge -#include "../../../southbridge/intel/sch/acpi/lpc.asl" +#include "lpc.asl" // PATA -#include "../../../southbridge/intel/sch/acpi/pata.asl" +#include "pata.asl" // SMBus -#include "../../../southbridge/intel/sch/acpi/smbus.asl" +#include "smbus.asl" From gerrit at coreboot.org Fri Feb 17 11:24:07 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 11:24:07 +0100 Subject: [coreboot] New patch to review for coreboot: 638c3f5 ACPI: More ../../.. removal References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/649 -gerrit commit 638c3f5471bc6c2c6424d0677db56291ce9b0b36 Author: Patrick Georgi Date: Thu Feb 16 19:16:14 2012 +0100 ACPI: More ../../.. removal CPP is ran with src/ as part of its search path, so using and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi --- src/mainboard/advansus/a785e-i/dsdt.asl | 4 ++-- src/mainboard/amd/bimini_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/dbm690t/dsdt.asl | 4 ++-- src/mainboard/amd/inagua/dsdt.asl | 4 ++-- src/mainboard/amd/mahogany/dsdt.asl | 4 ++-- src/mainboard/amd/mahogany_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/persimmon/dsdt.asl | 4 ++-- src/mainboard/amd/pistachio/dsdt.asl | 4 ++-- src/mainboard/amd/south_station/dsdt.asl | 4 ++-- src/mainboard/amd/tilapia_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/torpedo/dsdt.asl | 4 ++-- src/mainboard/amd/union_station/dsdt.asl | 4 ++-- src/mainboard/asrock/939a785gmh/dsdt.asl | 4 ++-- src/mainboard/asrock/e350m1/dsdt.asl | 4 ++-- src/mainboard/asus/m4a78-em/dsdt.asl | 4 ++-- src/mainboard/asus/m4a785-m/dsdt.asl | 4 ++-- src/mainboard/asus/m4a785t-m/dsdt.asl | 4 ++-- src/mainboard/asus/m5a88-v/dsdt.asl | 4 ++-- src/mainboard/avalue/eax-785e/dsdt.asl | 4 ++-- src/mainboard/getac/p470/dsdt.asl | 8 ++++---- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 4 ++-- src/mainboard/gigabyte/ma78gm/dsdt.asl | 4 ++-- src/mainboard/ibase/mb899/dsdt.asl | 8 ++++---- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 4 ++-- src/mainboard/intel/d945gclf/dsdt.asl | 8 ++++---- src/mainboard/iwave/iWRainbowG6/dsdt.asl | 8 ++++---- src/mainboard/jetway/pa78vm5/dsdt.asl | 4 ++-- src/mainboard/kontron/986lcd-m/dsdt.asl | 8 ++++---- src/mainboard/kontron/kt690/dsdt.asl | 4 ++-- src/mainboard/lenovo/t60/dsdt.asl | 8 ++++---- src/mainboard/lenovo/x60/dsdt.asl | 8 ++++---- src/mainboard/msi/ms9652_fam10/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/dsdt.asl | 8 ++++---- src/mainboard/supermicro/h8qgi/dsdt.asl | 4 ++-- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 4 ++-- src/mainboard/technexion/tim5690/dsdt.asl | 4 ++-- src/mainboard/technexion/tim8690/dsdt.asl | 4 ++-- 37 files changed, 89 insertions(+), 89 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 78d3220..52ca3b9 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 3ff6dab..e54723c 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 1b24e18..2b1aab8 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 4a61328..361adbb 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 33c4620..4920e2f 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1120,7 +1120,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 8bba547..b7e2a4a 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index c7ceb02..b480c33 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index bd5f73e..045db08 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1122,7 +1122,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index c4b69bd..7f03a43 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 93724e3..666cebe 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 2355e46..f1aef8b 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -798,7 +798,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 04952d3..5c8b661 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl index 70fca4d..da4d06a 100644 --- a/src/mainboard/asrock/939a785gmh/dsdt.asl +++ b/src/mainboard/asrock/939a785gmh/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ #include "northbridge/amd/amdk8/util.asl" Name(HPBA, 0xFED00000) /* Base address of HPET table */ @@ -460,7 +460,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 8dc40d0..97533c1 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index 7c28398..0d08d29 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index 34ddd3a..7ea5672 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index fe2bfa5..9e6ce88 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index b9a699b..a248766 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 1287f95..b835128 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index f6c6cf7..52397d3 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -35,7 +35,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -49,11 +49,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index fdd3a3e..a29bb2a 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 03d8fcd..c850b9e 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index f06b225..601c329 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 8dd0e21..8965f71 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 49b6033..62fa0af 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -44,11 +44,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl index f19ffb9..5bf59a7 100644 --- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl +++ b/src/mainboard/iwave/iWRainbowG6/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/sch/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/sch/acpi/sch.asl" - #include "../../../southbridge/intel/sch/acpi/sch.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/sch/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 38de9b9..8f75019 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 2235f62..a32015f 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 20ecb5b..a740a8b 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 905c94a..52a5edb 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -43,13 +43,13 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 905c94a..52a5edb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -43,13 +43,13 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index fe34112..c889841 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - #include "../../../../src/northbridge/amd/amdk8/util.asl" + #include /* For now only define 2 power states: * - S0 which is fully on diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index e3a62a3..58e78ec 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -46,11 +46,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 3f10012..137a90d 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1132,7 +1132,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index e8139c4..dd3c897 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1180,7 +1180,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 409d941..9279b5f 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index 5fd3e3e..b13d2ec 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ From gerrit at coreboot.org Fri Feb 17 13:21:07 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 17 Feb 2012 13:21:07 +0100 Subject: [coreboot] New patch to review for coreboot: 121bf31 Exit building if romstage.bin is larger than size of XIP References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/650 -gerrit commit 121bf312e7d51f9dd340b5e8da3a16d1fcb63866 Author: zbao Date: Fri Feb 17 21:21:23 2012 +0800 Exit building if romstage.bin is larger than size of XIP When the romstage.bin becomes bigger than the size of XIP, the cbfstool can not allocate the romstage in the CBFS. But it doesn't report an error. It will take quite a while to find out the root cause. Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/arch/x86/Makefile.inc | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..271b94d 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -346,6 +346,7 @@ $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld + test `stat -c%s $(obj)/romstage.bin` -le `printf %d $(CONFIG_XIP_ROM_SIZE)` || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" && exit 1; } $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt cat $(obj)/location.txt >> $(obj)/location.ld printf ';\n' >> $(obj)/location.ld From gerrit at coreboot.org Fri Feb 17 13:27:41 2012 From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com)) Date: Fri, 17 Feb 2012 13:27:41 +0100 Subject: [coreboot] New patch to review for coreboot: 70357f2 libpayload: enforce const correctness for CMOS getter/setter References: Message-ID: Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/652 -gerrit commit 70357f264a5f8a0472ea1fef7f6bc967fd674eb1 Author: Mathias Krause Date: Fri Feb 17 12:02:47 2012 +0100 libpayload: enforce const correctness for CMOS getter/setter Input only arguments to {get,set}_option*() should be const to catch programming errors early. Change-Id: I560001a8e9226dfd156a4e529fcad20549236ebd Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/options.c | 28 ++++++++++++++-------------- payloads/libpayload/include/libpayload.h | 14 +++++++------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 73316c1..03b6d36 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -97,7 +97,7 @@ void fix_options_checksum(void) static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) { - u8 *value = (u8 *)valptr; + u8 *value = valptr; int offs = 0; u32 addr, bit; u8 reg8; @@ -123,9 +123,9 @@ static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 le return 0; } -static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) +static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, const void *valptr) { - u8 *value = (u8 *)valptr; + const u8 *value = valptr; int offs = 0; u32 addr, bit; u8 reg8; @@ -152,7 +152,7 @@ static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 le return 0; } -static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, char *name) +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, const char *name) { struct cb_cmos_entries *cmos_entry; int len = name ? strnlen(name, CMOS_MAX_NAME_LENGTH) : 0; @@ -186,7 +186,7 @@ struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cmos_entry) } /* Either value or text must be NULL. Returns the field that matches "the other" for a given config_id */ -static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *option_table, int config_id, u8 *value, char *text) +static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *option_table, int config_id, const u8 *value, const char *text) { struct cb_cmos_entries *cmos_entry; int len = strnlen(text, CMOS_MAX_TEXT_LENGTH); @@ -211,17 +211,17 @@ static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table * return NULL; } -static struct cb_cmos_enums *lookup_cmos_enum_by_value(struct cb_cmos_option_table *option_table, int config_id, u8 *value) +static struct cb_cmos_enums *lookup_cmos_enum_by_value(struct cb_cmos_option_table *option_table, int config_id, const u8 *value) { return lookup_cmos_enum_core(option_table, config_id, value, NULL); } -static struct cb_cmos_enums *lookup_cmos_enum_by_label(struct cb_cmos_option_table *option_table, int config_id, char *label) +static struct cb_cmos_enums *lookup_cmos_enum_by_label(struct cb_cmos_option_table *option_table, int config_id, const char *label) { return lookup_cmos_enum_core(option_table, config_id, NULL, label); } -int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name) +int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, const char *name) { struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); if (cmos_entry) { @@ -236,17 +236,17 @@ int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_ta return 1; } -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, const char *name) { return get_option_with(use_nvram, option_table, dest, name); } -int get_option(void *dest, char *name) +int get_option(void *dest, const char *name) { return get_option_from(get_system_option_table(), dest, name); } -int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name) +int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const void *value, const char *name) { struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); if (cmos_entry) { @@ -257,12 +257,12 @@ int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_ta return 1; } -int set_option(void *value, char *name) +int set_option(const void *value, const char *name) { return set_option_with(use_nvram, get_system_option_table(), value, name); } -int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, char *name) +int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name) { void *raw; struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); @@ -298,7 +298,7 @@ int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_opti return ret; } -int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char *value, char *name) +int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const char *value, const char *name) { void *raw; struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 53d6672..c67c659 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -208,13 +208,13 @@ void fix_options_checksum_with(const struct nvram_accessor *nvram); void fix_options_checksum(void); struct cb_cmos_entries *first_cmos_entry(struct cb_cmos_option_table *option_table); struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cur); -int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name); -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); -int get_option(void *dest, char *name); -int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name); -int set_option(void *value, char *name); -int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, char *name); -int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char *value, char *name); +int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, const char *name); +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, const char *name); +int get_option(void *dest, const char *name); +int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const void *value, const char *name); +int set_option(const void *value, const char *name); +int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name); +int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const char *value, const char *name); /** * @defgroup console Console functions From gerrit at coreboot.org Fri Feb 17 13:27:28 2012 From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com)) Date: Fri, 17 Feb 2012 13:27:28 +0100 Subject: [coreboot] New patch to review for coreboot: 5ca7fab libpayload: fix compiler warning for first_cmos_entry() References: Message-ID: Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/651 -gerrit commit 5ca7fab6a2e741cddd4d86e2cf321378e807db1f Author: Mathias Krause Date: Fri Feb 17 11:53:28 2012 +0100 libpayload: fix compiler warning for first_cmos_entry() The 'name' argument to lookup_cmos_entry() is declared to be 'char *' but we pass an empty string ("") which is 'const char[]' so the compiler legitimatly warns about discarded qualifiers here. Fix this by passing NULL as 'name'. Minor nitpick: The NULL test in lookup_cmos_entry() is superfluous as our implementation of strnlen() can handle NULL pointers gracefully. But for an average C hacker it just doesn't feel right not to do so. Change-Id: I592917d12d8fa840804c0d19e38b844427064fef Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/options.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 7c76251..73316c1 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -155,7 +155,7 @@ static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 le static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, char *name) { struct cb_cmos_entries *cmos_entry; - int len = strnlen(name, CMOS_MAX_NAME_LENGTH); + int len = name ? strnlen(name, CMOS_MAX_NAME_LENGTH) : 0; /* cmos entries are located right after the option table */ @@ -173,7 +173,7 @@ static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *op struct cb_cmos_entries *first_cmos_entry(struct cb_cmos_option_table *option_table) { - return lookup_cmos_entry(option_table, ""); + return lookup_cmos_entry(option_table, NULL); } struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cmos_entry) From gerrit at coreboot.org Fri Feb 17 13:30:43 2012 From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com)) Date: Fri, 17 Feb 2012 13:30:43 +0100 Subject: [coreboot] New patch to review for coreboot: 979a6a3 libpayload: fix compile error with enabled USB_DEBUG References: Message-ID: Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/653 -gerrit commit 979a6a3099ff7b4498e098c1ab9df6508b0e8087 Author: Mathias Krause Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/usb/ohci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 4095d69..92cbf1c 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -190,7 +190,7 @@ dump_td(td_t *cur, int level) const char *spc=spaces+(10-level); debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[(cur->config & TD_DIRECTION_MASK) >> TD_DIRECTION_SHIFT], completion_codes[(cur->config & TD_CC_MASK) >> TD_CC_SHIFT]); - debug("%s toggle: %x\n", spc, cur->toggle); + debug("%s toggle: %x\n", spc, cur->config & TD_TOGGLE_DATA1 ? 1 : 0); #endif } From gerrit at coreboot.org Fri Feb 17 13:43:52 2012 From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com)) Date: Fri, 17 Feb 2012 13:43:52 +0100 Subject: [coreboot] Patch set updated for coreboot: 10daacf Exit building if romstage.bin is larger than size of XIP References: Message-ID: Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/650 -gerrit commit 10daacf118096519aeac961c1814f790cbf66d0e Author: zbao Date: Fri Feb 17 21:44:09 2012 +0800 Exit building if romstage.bin is larger than size of XIP When the romstage.bin becomes bigger than the size of XIP, the cbfstool can not allocate the romstage in the CBFS. But it doesn't report an error. It will take quite a while to find out the root cause. Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa Signed-off-by: Zheng Bao Signed-off-by: zbao --- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfstool.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..624b510 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -346,7 +346,7 @@ $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } cat $(obj)/location.txt >> $(obj)/location.ld printf ';\n' >> $(obj)/location.ld $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index b8abb51..939221e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -232,9 +232,10 @@ static int cbfs_locate(int argc, char **argv) uint32_t filesize = getfilesize(file); const char *filename = argv[4]; int align = strtoul(argv[5], NULL, 0); + uint32_t location = cbfs_find_location(romname, filesize, filename, align); - printf("%x\n", cbfs_find_location(romname, filesize, filename, align)); - return 0; + printf("%x\n", location); + return location == 0 ? 1 : 0; } static int cbfs_print(int argc, char **argv) From gerrit at coreboot.org Fri Feb 17 13:35:17 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 17 Feb 2012 13:35:17 +0100 Subject: [coreboot] Patch set updated for coreboot: 773f2c2 Add support for RAM-less multi-processor init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 773f2c2ae32a59f786aaecfbf1756f3d79c435e4 Author: Ky?sti M?lkki Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..0bdef34 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -31,6 +31,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help From gerrit at coreboot.org Fri Feb 17 13:37:31 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 17 Feb 2012 13:37:31 +0100 Subject: [coreboot] Patch set updated for coreboot: 97120f0 Intel cpus: copy model_6ex CAR code References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 97120f0397a34543b5300e68d0899efe4b63f3f0 Author: Ky?sti M?lkki Date: Fri Feb 17 01:38:13 2012 +0200 Intel cpus: copy model_6ex CAR code Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 269 +++++++++++++++++++++++++++++++++ 1 files changed, 269 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..4505e0e --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) + +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + +#if !CONFIG_INTEL_NETBURST + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). + * This MSR does not exist on NetBurst architecture. + * + * Description says this bit enables use of WBINVD and FLUSH#. + * Should this be set only after the system bus and/or memory + * controller can successfully handle write cycles? + */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr +#endif + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion. */ + cld + xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + rep stosl + + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp +#endif + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function. */ + call main + addl $4, %esp + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for low RAM. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable caching and Speculative Reads for Flash ROM device. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + From gerrit at coreboot.org Fri Feb 17 14:49:05 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 17 Feb 2012 14:49:05 +0100 Subject: [coreboot] Patch set updated for coreboot: 42a0258 Add support for RAM-less multi-processor init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 42a025844124f7dcb4d6de8eb1f99cd2fd8f71f4 Author: Ky?sti M?lkki Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index d576873..601f443 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -38,6 +38,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help From gerrit at coreboot.org Fri Feb 17 14:49:36 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 17 Feb 2012 14:49:36 +0100 Subject: [coreboot] Patch set updated for coreboot: d678491 Add cache_as_ram_ht.inc with hyper-threading CPU support References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit d678491fdb594b6a872c78465851a8656dfcd4da Author: Ky?sti M?lkki Date: Thu Feb 16 21:23:33 2012 +0200 Add cache_as_ram_ht.inc with hyper-threading CPU support This variant of cache_as_ram.inc starts the sibling CPU processors and clears the cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. The code was developed for model_f25 from model_6ex. Some of the cache enable-disable logic seems spurious to me. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 147 ++++++++++++++++++++++++++++++--- 1 files changed, 134 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 4505e0e..139f63a 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Ky?sti M?lkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +27,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) @@ -40,12 +43,9 @@ cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself. */ - movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax - movl %eax, (%edi) - - /* Zero out all fixed range and variable range MTRRs. */ + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -58,12 +58,127 @@ clear_mtrrs: dec %edi jnz clear_mtrrs + post_code(0x21) + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr + post_code(0x22) + + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~CPU_PHYSMASK_HI), %edx + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_init + +bsp_init: + + post_code(0x23) + + /* Send INIT IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + post_code(0x24) + + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc sipi_complete + bswapl %ebx + cmpb $01, %bh + jbe sipi_complete + +hyper_threading_cpu: + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x25) + + /* Send Start IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x26) + + /* Wait for sibling CPU to start. */ +1: movl $(MTRRphysBase_MSR(0)), %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + + +ap_init: + post_code(0x27) + + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + post_code(0x28) + + /* MTRR registers are shared between HT siblings. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(1<<12), %eax + xorl %edx, %edx + wrmsr + + post_code(0x29) + +ap_halt: + cli +1: hlt + jnz 1b + + + +sipi_complete: + + post_code(0x2a) + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax @@ -82,6 +197,8 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr + post_code(0x2b) + #if !CONFIG_INTEL_NETBURST /* Enable L2 cache Write-Back (WBINVD and FLUSH#). * This MSR does not exist on NetBurst architecture. @@ -96,6 +213,8 @@ clear_mtrrs: wrmsr #endif + post_code(0x2c) + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax @@ -114,6 +233,8 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 + post_code(0x2d) + #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx @@ -138,6 +259,8 @@ clear_mtrrs: andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 + post_code(0x2e) + /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ @@ -151,14 +274,12 @@ clear_mtrrs: movl %esp, %ebp pushl %eax - post_code(0x23) + post_code(0x2f) /* Call romstage.c main function. */ call main addl $4, %esp - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -166,7 +287,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 - post_code(0x31) + post_code(0x34) /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx @@ -174,18 +295,18 @@ clear_mtrrs: andl $(~MTRRdefTypeEn), %eax wrmsr - post_code(0x31) + post_code(0x35) invd - post_code(0x33) + post_code(0x36) /* Enable cache. */ movl %cr0, %eax andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 - post_code(0x36) + post_code(0x37) /* Disable cache. */ movl %cr0, %eax From gerrit at coreboot.org Fri Feb 17 14:49:49 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Fri, 17 Feb 2012 14:49:49 +0100 Subject: [coreboot] Patch set updated for coreboot: 5141b7c Apply cache-as-ram conditionally on socket mPGA604 References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607 -gerrit commit 5141b7cd455d57027469cdc4f4ad8ea63dbd5b60 Author: Ky?sti M?lkki Date: Wed Feb 1 19:15:13 2012 +0200 Apply cache-as-ram conditionally on socket mPGA604 The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Makefile.inc | 8 +------- src/cpu/intel/socket_mPGA604/Kconfig | 18 +++++++++++++++++- src/cpu/intel/socket_mPGA604/Makefile.inc | 2 ++ 3 files changed, 20 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..eeb162d 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..fb48968 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,11 +1,17 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X select MMX select SSE select UDELAY_TSC + select INTEL_NETBURST # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -13,4 +19,14 @@ config CPU_INTEL_SOCKET_MPGA604 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..fb1cacd 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc + From gerrit at coreboot.org Fri Feb 17 17:18:18 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 17:18:18 +0100 Subject: [coreboot] Patch merged into coreboot/master: 0295597 SIO: Add smsc/sch4037 superio support References: Message-ID: the following patch was just integrated into master: commit 0295597c40c6069186d690651b91a85efefc7851 Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Fri Feb 17 10:02:42 2012, giving +1 Reviewed-By: Marc Jones at Fri Feb 17 17:18:16 2012, giving +2 See http://review.coreboot.org/562 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 17:19:37 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 17:19:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: 06edf50 SIO: Add smsc sio1036 superio References: Message-ID: the following patch was just integrated into master: commit 06edf5030bf5ad86db07a0922213d6d50d73553a Author: Kerry Sheh Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc sio1036 superio Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Fri Feb 17 09:45:47 2012, giving +1 Reviewed-By: Marc Jones at Fri Feb 17 17:19:20 2012, giving +2 See http://review.coreboot.org/563 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 17:39:52 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 17:39:52 +0100 Subject: [coreboot] Patch merged into coreboot/master: d1946d5 Mainboard: Add AMD dinar mainboard. References: Message-ID: the following patch was just integrated into master: commit d1946d5dca690404bdde13f317f2fac862f7d88f Author: Kerry Sheh Date: Tue Feb 7 20:32:34 2012 +0800 Mainboard: Add AMD dinar mainboard. Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh Signed-off-by: Kerry Sheh Build-Tested: build bot (Jenkins) at Fri Feb 17 09:29:10 2012, giving +1 Reviewed-By: Marc Jones at Fri Feb 17 17:39:50 2012, giving +2 See http://review.coreboot.org/564 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 17:58:42 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:42 +0100 Subject: [coreboot] New patch to review for coreboot: 961e5ba amd/amd8111: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/654 -gerrit commit 961e5ba7c45630f20e66ef82105a2f9d51c48e3e Author: Patrick Georgi Date: Thu Feb 16 19:24:03 2012 +0100 amd/amd8111: Move HAVE_HARD_RESET to southbridge No in-tree amd8111-using board has it not selected, so move selection from boards to southbridge. Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52 Signed-off-by: Patrick Georgi --- src/mainboard/amd/serengeti_cheetah/Kconfig | 1 - src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 1 - src/mainboard/arima/hdama/Kconfig | 1 - src/mainboard/hp/dl145_g1/Kconfig | 1 - src/mainboard/ibm/e325/Kconfig | 1 - src/mainboard/ibm/e326/Kconfig | 1 - src/mainboard/iwill/dk8_htx/Kconfig | 1 - src/mainboard/iwill/dk8s2/Kconfig | 1 - src/mainboard/iwill/dk8x/Kconfig | 1 - src/mainboard/newisys/khepri/Kconfig | 1 - src/mainboard/tyan/s2850/Kconfig | 1 - src/mainboard/tyan/s2875/Kconfig | 1 - src/mainboard/tyan/s2880/Kconfig | 1 - src/mainboard/tyan/s2881/Kconfig | 1 - src/mainboard/tyan/s2882/Kconfig | 1 - src/mainboard/tyan/s2885/Kconfig | 1 - src/mainboard/tyan/s4880/Kconfig | 1 - src/mainboard/tyan/s4882/Kconfig | 1 - src/southbridge/amd/amd8111/Kconfig | 1 + 19 files changed, 1 insertions(+), 18 deletions(-) diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index 5cd07c6..f2f4b54 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID #select AP_CODE_IN_CAR select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index df71444..e633758 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select SERIAL_CPU_INIT select AMDMCT diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 7f0e40d..408e953 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_512 select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index d2de8a2..3628646 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index b935eb4..48b93d1 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 40c64bc..81c10ba 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index e58fe4e..3785b11 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index 78d0637..f9f1b57 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select ATI_RAGE_XL diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index 16eab8d..9216078 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index fc4c223..6ee4bf0 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index c555951..2d07423 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 56c3723..d9e7bac 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8151 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 87ec6ca..93dadac 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 0073ebb..c8888bb 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index c6711b3..145fdfc 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index f4a6f49..bfc22a0 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8151 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index 0b425b9..5040a6a 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 3aa1690..ee67bae 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 83fb8fc..fd244c8 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC + select HAVE_HARD_RESET config BOOTBLOCK_SOUTHBRIDGE_INIT string From gerrit at coreboot.org Fri Feb 17 17:58:43 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:43 +0100 Subject: [coreboot] New patch to review for coreboot: 1f333d1 intel/82801dx: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/655 -gerrit commit 1f333d1259fe02d1b69578f92fbf1306c2003150 Author: Patrick Georgi Date: Thu Feb 16 19:28:51 2012 +0100 intel/82801dx: Move HAVE_HARD_RESET to southbridge No in-tree 82801dx-using board has it not selected, so move selection from boards to southbridge. Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c Signed-off-by: Patrick Georgi --- src/mainboard/digitallogic/adl855pc/Kconfig | 1 - src/mainboard/lanner/em8510/Kconfig | 1 - src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/thomson/ip1000/Kconfig | 1 - src/southbridge/intel/i82801dx/Kconfig | 1 + 5 files changed, 1 insertions(+), 4 deletions(-) diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index 4b2bcd2..a20a5c8 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig index 52f5a72..1a306cf 100644 --- a/src/mainboard/lanner/em8510/Kconfig +++ b/src/mainboard/lanner/em8510/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index 5a9901e..1e4498a 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 - select HAVE_HARD_RESET select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index d9ea787..3bdfb8e 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select HAVE_HARD_RESET select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 0f749b5..5d4e15a 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,3 +22,4 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select IOAPIC + select HAVE_HARD_RESET From gerrit at coreboot.org Fri Feb 17 17:58:43 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:43 +0100 Subject: [coreboot] New patch to review for coreboot: cd38b83 via/cx700: Move HAVE_HARD_RESET to northbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/656 -gerrit commit cd38b83244c00a719a31ee3d23aea1ba8f30822d Author: Patrick Georgi Date: Thu Feb 16 19:37:58 2012 +0100 via/cx700: Move HAVE_HARD_RESET to northbridge No in-tree cx700-using board has it not selected, so move selection from boards to northbridge. Change-Id: Ifa79954a48cf99b5f7e49960eafce805401e571c Signed-off-by: Patrick Georgi --- src/mainboard/via/vt8454c/Kconfig | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index c9a0105..5739d2a 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE # select MMCONF_SUPPORT - select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 From gerrit at coreboot.org Fri Feb 17 17:58:44 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:44 +0100 Subject: [coreboot] New patch to review for coreboot: 99d2e99 nvidia/ck804: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/657 -gerrit commit 99d2e9999b9975e16b2aaadb4d1bba72ae74ef9e Author: Patrick Georgi Date: Thu Feb 16 19:39:39 2012 +0100 nvidia/ck804: Move HAVE_HARD_RESET to southbridge No in-tree ck804-using board has it not selected, so move selection from boards to southbridge. Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87 Signed-off-by: Patrick Georgi --- src/mainboard/asus/a8n_e/Kconfig | 1 - src/mainboard/msi/ms7135/Kconfig | 1 - src/mainboard/sunw/ultra40/Kconfig | 1 - src/mainboard/tyan/s2891/Kconfig | 1 - src/mainboard/tyan/s2892/Kconfig | 1 - src/mainboard/tyan/s2895/Kconfig | 1 - 6 files changed, 0 insertions(+), 6 deletions(-) diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index aca9e33..6c134f6 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select CK804_USE_NIC select CK804_USE_ACI diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index c08a169..40e4fb7 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_WINBOND_W83627THG select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 81a6608..6a02a82 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 select CK804_USE_NIC select CK804_USE_ACI diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index 2848380..395f734 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index d58f5ab..9c6e7ec 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index f35ea82..05b6806 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_LPC47B397 select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE - select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SERIAL_CPU_INIT From gerrit at coreboot.org Fri Feb 17 17:58:45 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:45 +0100 Subject: [coreboot] New patch to review for coreboot: c8753cb broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/658 -gerrit commit c8753cbfe7448a3ccb76742a77e7d5fe8fb749da Author: Patrick Georgi Date: Thu Feb 16 19:42:48 2012 +0100 broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3 Signed-off-by: Patrick Georgi --- src/mainboard/broadcom/blast/Kconfig | 1 - src/mainboard/hp/dl145_g3/Kconfig | 1 - src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - src/mainboard/msi/ms9185/Kconfig | 1 - 4 files changed, 0 insertions(+), 4 deletions(-) diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b2f923d..365ce09 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 8be6752..e27f803 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index e3dbf6b..cdff24f 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 1464acd..340b682 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO From gerrit at coreboot.org Fri Feb 17 17:58:45 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:45 +0100 Subject: [coreboot] New patch to review for coreboot: c5be342 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/659 -gerrit commit c5be3428454dc29fb28b0d7a507fa4ef7e707fa3 Author: Patrick Georgi Date: Thu Feb 16 19:44:28 2012 +0100 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi --- src/mainboard/asus/m2n-e/Kconfig | 1 - src/mainboard/gigabyte/m57sli/Kconfig | 1 - src/mainboard/msi/ms7260/Kconfig | 1 - src/mainboard/msi/ms9282/Kconfig | 1 - src/mainboard/msi/ms9652_fam10/Kconfig | 1 - src/mainboard/nvidia/l1_2pvv/Kconfig | 1 - src/mainboard/supermicro/h8dme/Kconfig | 1 - src/mainboard/supermicro/h8dmr/Kconfig | 1 - src/mainboard/supermicro/h8dmr_fam10/Kconfig | 1 - src/mainboard/supermicro/h8qme_fam10/Kconfig | 1 - src/mainboard/tyan/s2912/Kconfig | 1 - src/mainboard/tyan/s2912_fam10/Kconfig | 1 - src/southbridge/nvidia/mcp55/Kconfig | 1 + 13 files changed, 1 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index c23a2df..1f92097 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 7250a9c..0c8fc1b 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index be425ec..18f6e6f 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index 9e8cf4e..f4bc059 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 17f0502..7439646 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index bfec323..6ca0816 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 376b81a..e4fd9a6 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET #select AP_CODE_IN_CAR select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 5527319..106992a 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 3583300..7c7b89e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select AMDMCT select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 85d0fb0..8476599 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select AMDMCT select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 811e9a7..192b4ff 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index ffe665d..910181d 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index fc355cb..cd6009d 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool select HAVE_USBDEBUG select IOAPIC + select HAVE_HARD_RESET if SOUTHBRIDGE_NVIDIA_MCP55 From gerrit at coreboot.org Fri Feb 17 17:58:46 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:46 +0100 Subject: [coreboot] New patch to review for coreboot: daedba4 amd/sb600: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/660 -gerrit commit daedba4699667a81dce85d1d36df3d8f82f1ada4 Author: Patrick Georgi Date: Thu Feb 16 19:45:56 2012 +0100 amd/sb600: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0 Signed-off-by: Patrick Georgi --- src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim8690/Kconfig | 1 - src/southbridge/amd/sb600/Kconfig | 1 + 7 files changed, 1 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 3d3a04c..d1bf72f 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 487a599..d140878 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 91d6b67..6a1909f 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES select GFXUMA - select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index 983e94c..c7e3298 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 21cfa7b..404ddfe 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 5af6ace..293590c 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 07028a0..8ec3967 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB600 config BOOTBLOCK_SOUTHBRIDGE_INIT From gerrit at coreboot.org Fri Feb 17 17:58:48 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:48 +0100 Subject: [coreboot] New patch to review for coreboot: 44b094e amd/sb700: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/661 -gerrit commit 44b094ea4156f4f368c4ee40b34b1afa7efc2f17 Author: Patrick Georgi Date: Thu Feb 16 19:52:16 2012 +0100 amd/sb700: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1 Signed-off-by: Patrick Georgi --- src/mainboard/amd/mahogany/Kconfig | 1 - src/mainboard/amd/mahogany_fam10/Kconfig | 1 - src/mainboard/amd/tilapia_fam10/Kconfig | 1 - src/mainboard/asrock/939a785gmh/Kconfig | 1 - src/mainboard/asus/m4a78-em/Kconfig | 1 - src/mainboard/asus/m4a785-m/Kconfig | 1 - src/mainboard/asus/m4a785t-m/Kconfig | 1 - src/mainboard/gigabyte/ma785gmt/Kconfig | 1 - src/mainboard/gigabyte/ma78gm/Kconfig | 1 - src/mainboard/iei/kino-780am2-fam10/Kconfig | 1 - src/mainboard/jetway/pa78vm5/Kconfig | 1 - src/southbridge/amd/sb700/Kconfig | 1 + 12 files changed, 1 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index b0a46a4..7c91b7d 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index b8d46eb..8343fca 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index e9d6081..2c29f45 100755 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index 7021655..245b845 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select LIFT_BSP_APIC_ID - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select GFXUMA diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index d036b21..516308f 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index 84cc06c..ec3a488 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index e3893b2..633b994 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 77bda90..0605a39 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 56b819e..1b6966e 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index 8fb1950..01a2429 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index 62adb53..fa39039 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 98b8e2a..05f7d09 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_SB700 bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET config SOUTHBRIDGE_AMD_SP5100 bool From gerrit at coreboot.org Fri Feb 17 17:58:49 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:49 +0100 Subject: [coreboot] New patch to review for coreboot: 4163c03 intel/i82801cx: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/662 -gerrit commit 4163c03b2d713131a863fbf2ec636feb3a983d3e Author: Patrick Georgi Date: Thu Feb 16 19:53:21 2012 +0100 intel/i82801cx: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336 Signed-off-by: Patrick Georgi --- src/mainboard/intel/xe7501devkit/Kconfig | 1 - src/southbridge/intel/i82801cx/Kconfig | 2 ++ 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig index 9163423..a743469 100644 --- a/src/mainboard/intel/xe7501devkit/Kconfig +++ b/src/mainboard/intel/xe7501devkit/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801CX select SUPERIO_SMSC_LPC47B272 select ROMCC - select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig index a0c775d..17e90e8 100644 --- a/src/southbridge/intel/i82801cx/Kconfig +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -1,2 +1,4 @@ config SOUTHBRIDGE_INTEL_I82801CX bool + select HAVE_HARD_RESET + From gerrit at coreboot.org Fri Feb 17 17:58:49 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:49 +0100 Subject: [coreboot] New patch to review for coreboot: ce3ab07 sis/sis966: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/663 -gerrit commit ce3ab07e387c24eddbd08ca5ac67ae7259bae8b8 Author: Patrick Georgi Date: Thu Feb 16 19:56:50 2012 +0100 sis/sis966: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3 Signed-off-by: Patrick Georgi --- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 1 - src/southbridge/sis/sis966/Kconfig | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index d25db85..d47344b 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 3cee5b3..03dd6b1 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -2,6 +2,7 @@ config SOUTHBRIDGE_SIS_SIS966 bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET config BOOTBLOCK_SOUTHBRIDGE_INIT string From gerrit at coreboot.org Fri Feb 17 17:58:51 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:51 +0100 Subject: [coreboot] New patch to review for coreboot: 89e5ccc intel/i82801ex: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/664 -gerrit commit 89e5ccc70f88e9391b12e3658c9bdfe28d590741 Author: Patrick Georgi Date: Thu Feb 16 19:58:00 2012 +0100 intel/i82801ex: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56 Signed-off-by: Patrick Georgi --- src/mainboard/dell/s1850/Kconfig | 1 - src/mainboard/intel/jarrell/Kconfig | 1 - src/mainboard/supermicro/x6dhe_g2/Kconfig | 1 - src/mainboard/supermicro/x6dhr_ig/Kconfig | 1 - src/mainboard/supermicro/x6dhr_ig2/Kconfig | 1 - src/mainboard/tyan/s2735/Kconfig | 1 - src/southbridge/intel/i82801ex/Kconfig | 2 ++ 7 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig index 381c9f6..cd4a6a9 100644 --- a/src/mainboard/dell/s1850/Kconfig +++ b/src/mainboard/dell/s1850/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC8374 select ROMCC - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 494086e..282ec4b 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_NSC_PC87427 select ROMCC - select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig index e9d4041..0f03336 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC87427 select ROMCC - select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig index a146e77..db9fd95 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC - select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig index 6196e2a..395c184 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF select ROMCC - select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index 4aafa3c..9e1b57f 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_WINBOND_W83627HF - select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select UDELAY_TSC diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig index 905af26..23a68b8 100644 --- a/src/southbridge/intel/i82801ex/Kconfig +++ b/src/southbridge/intel/i82801ex/Kconfig @@ -1,3 +1,5 @@ config SOUTHBRIDGE_INTEL_I82801EX bool select IOAPIC + select HAVE_HARD_RESET + From gerrit at coreboot.org Fri Feb 17 17:58:51 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:51 +0100 Subject: [coreboot] New patch to review for coreboot: 7a2d314 intel/sch: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/665 -gerrit commit 7a2d3142f8f4d7c606c1f7e46a7d1e478e77b5fb Author: Patrick Georgi Date: Thu Feb 16 19:58:51 2012 +0100 intel/sch: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18 Signed-off-by: Patrick Georgi --- src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/southbridge/intel/sch/Kconfig | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index a1c03c8..6802d5c 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select USE_DCACHE_RAM select GFXUMA - select HAVE_HARD_RESET config MAINBOARD_DIR string diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index ed2c6c4..83ff447 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_SCH bool select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_INTEL_SCH From gerrit at coreboot.org Fri Feb 17 17:58:53 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Fri, 17 Feb 2012 17:58:53 +0100 Subject: [coreboot] New patch to review for coreboot: cd19125 amd/sb800: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/666 -gerrit commit cd191255004e3701096e0f7fc810e3e29456f80d Author: Patrick Georgi Date: Thu Feb 16 20:03:28 2012 +0100 amd/sb800: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. (cimx/sb800 is a "different" chipset) Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480 Signed-off-by: Patrick Georgi --- src/mainboard/amd/bimini_fam10/Kconfig | 1 - src/southbridge/amd/sb800/Kconfig | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 2118078..06ed977 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select GENERATE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 67cb8ef..592f9a7 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_SB800 bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET config BOOTBLOCK_SOUTHBRIDGE_INIT string From gerrit at coreboot.org Fri Feb 17 17:45:27 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 17:45:27 +0100 Subject: [coreboot] Patch merged into coreboot/master: 10daacf Exit building if romstage.bin is larger than size of XIP References: Message-ID: the following patch was just integrated into master: commit 10daacf118096519aeac961c1814f790cbf66d0e Author: zbao Date: Fri Feb 17 21:44:09 2012 +0800 Exit building if romstage.bin is larger than size of XIP When the romstage.bin becomes bigger than the size of XIP, the cbfstool can not allocate the romstage in the CBFS. But it doesn't report an error. It will take quite a while to find out the root cause. Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa Signed-off-by: Zheng Bao Signed-off-by: zbao Reviewed-By: Patrick Georgi at Fri Feb 17 14:32:33 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Feb 17 14:49:48 2012, giving +1 Reviewed-By: Marc Jones at Fri Feb 17 17:45:08 2012, giving +2 See http://review.coreboot.org/650 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 18:58:19 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 18:58:19 +0100 Subject: [coreboot] Patch merged into coreboot/master: 1f333d1 intel/82801dx: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 1f333d1259fe02d1b69578f92fbf1306c2003150 Author: Patrick Georgi Date: Thu Feb 16 19:28:51 2012 +0100 intel/82801dx: Move HAVE_HARD_RESET to southbridge No in-tree 82801dx-using board has it not selected, so move selection from boards to southbridge. Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 18:46:33 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 18:58:17 2012, giving +2 See http://review.coreboot.org/655 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:25:00 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:25:00 +0100 Subject: [coreboot] Patch merged into coreboot/master: 23defd9 Rename i945 ACPI files to not carry an i945_ prefix References: Message-ID: the following patch was just integrated into master: commit 23defd9637fb9791dc5c7cdadc847f2bc7698c1f Author: Patrick Georgi Date: Thu Feb 16 18:58:46 2012 +0100 Rename i945 ACPI files to not carry an i945_ prefix In the spirit of the earlier renames. Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 11:37:42 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:04:56 2012, giving +2 See http://review.coreboot.org/647 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:26:22 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:26:22 +0100 Subject: [coreboot] Patch merged into coreboot/master: 87af06a Avoid ../../.. paths in ASL files References: Message-ID: the following patch was just integrated into master: commit 87af06a897dd92ae94e45f4b1d1f6d9719cf3edd Author: Patrick Georgi Date: Thu Feb 16 19:01:22 2012 +0100 Avoid ../../.. paths in ASL files The current directory is always part of the search path of cpp when using #include "..." Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 11:48:54 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:05:18 2012, giving +2 See http://review.coreboot.org/648 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:27:19 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:27:19 +0100 Subject: [coreboot] Patch merged into coreboot/master: 70357f2 libpayload: enforce const correctness for CMOS getter/setter References: Message-ID: the following patch was just integrated into master: commit 70357f264a5f8a0472ea1fef7f6bc967fd674eb1 Author: Mathias Krause Date: Fri Feb 17 12:02:47 2012 +0100 libpayload: enforce const correctness for CMOS getter/setter Input only arguments to {get,set}_option*() should be const to catch programming errors early. Change-Id: I560001a8e9226dfd156a4e529fcad20549236ebd Signed-off-by: Mathias Krause Build-Tested: build bot (Jenkins) at Fri Feb 17 13:56:19 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:26:48 2012, giving +2 See http://review.coreboot.org/652 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:24:36 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:24:36 +0100 Subject: [coreboot] Patch merged into coreboot/master: 5ca7fab libpayload: fix compiler warning for first_cmos_entry() References: Message-ID: the following patch was just integrated into master: commit 5ca7fab6a2e741cddd4d86e2cf321378e807db1f Author: Mathias Krause Date: Fri Feb 17 11:53:28 2012 +0100 libpayload: fix compiler warning for first_cmos_entry() The 'name' argument to lookup_cmos_entry() is declared to be 'char *' but we pass an empty string ("") which is 'const char[]' so the compiler legitimatly warns about discarded qualifiers here. Fix this by passing NULL as 'name'. Minor nitpick: The NULL test in lookup_cmos_entry() is superfluous as our implementation of strnlen() can handle NULL pointers gracefully. But for an average C hacker it just doesn't feel right not to do so. Change-Id: I592917d12d8fa840804c0d19e38b844427064fef Signed-off-by: Mathias Krause Build-Tested: build bot (Jenkins) at Fri Feb 17 13:44:56 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:07:05 2012, giving +2 See http://review.coreboot.org/651 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 18:59:47 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 18:59:47 +0100 Subject: [coreboot] Patch merged into coreboot/master: cd38b83 via/cx700: Move HAVE_HARD_RESET to northbridge References: Message-ID: the following patch was just integrated into master: commit cd38b83244c00a719a31ee3d23aea1ba8f30822d Author: Patrick Georgi Date: Thu Feb 16 19:37:58 2012 +0100 via/cx700: Move HAVE_HARD_RESET to northbridge No in-tree cx700-using board has it not selected, so move selection from boards to northbridge. Change-Id: Ifa79954a48cf99b5f7e49960eafce805401e571c Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 18:58:03 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 18:59:19 2012, giving +2 See http://review.coreboot.org/656 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:24:23 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:24:23 +0100 Subject: [coreboot] Patch merged into coreboot/master: 99d2e99 nvidia/ck804: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 99d2e9999b9975e16b2aaadb4d1bba72ae74ef9e Author: Patrick Georgi Date: Thu Feb 16 19:39:39 2012 +0100 nvidia/ck804: Move HAVE_HARD_RESET to southbridge No in-tree ck804-using board has it not selected, so move selection from boards to southbridge. Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 19:15:47 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:19:37 2012, giving +2 See http://review.coreboot.org/657 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:01:37 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:01:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: 961e5ba amd/amd8111: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 961e5ba7c45630f20e66ef82105a2f9d51c48e3e Author: Patrick Georgi Date: Thu Feb 16 19:24:03 2012 +0100 amd/amd8111: Move HAVE_HARD_RESET to southbridge No in-tree amd8111-using board has it not selected, so move selection from boards to southbridge. Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 18:33:10 2012, giving +1 See http://review.coreboot.org/654 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:04:33 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:04:33 +0100 Subject: [coreboot] Patch merged into coreboot/master: 924a34d Remove whitespace. References: Message-ID: the following patch was just integrated into master: commit 924a34d608c3420398947661f1412cb443274a4f Author: Patrick Georgi Date: Thu Feb 16 20:44:20 2012 +0100 Remove whitespace. Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 11:14:39 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:04:25 2012, giving +2 See http://review.coreboot.org/646 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 19:04:26 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 19:04:26 +0100 Subject: [coreboot] Patch merged into coreboot/master: ce4abe3 lint: Add test for whitespace issues in the code References: Message-ID: the following patch was just integrated into master: commit ce4abe3fa98283a400b63760750e4df04e0ae204 Author: Patrick Georgi Date: Thu Feb 16 20:28:42 2012 +0100 lint: Add test for whitespace issues in the code So far it tests for trailing whitespace. "Upstream" files (bison/flex's .?_shipped, kconfig, vendorcode) are ignored. Change-Id: I7af1954d537fd05f06cd210ac130dac87892159b Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 11:03:11 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:01:58 2012, giving +2 See http://review.coreboot.org/645 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 20:09:37 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 20:09:37 +0100 Subject: [coreboot] Patch merged into coreboot/master: c8753cb broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit c8753cbfe7448a3ccb76742a77e7d5fe8fb749da Author: Patrick Georgi Date: Thu Feb 16 19:42:48 2012 +0100 broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 20:01:33 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:19:33 2012, giving +2 See http://review.coreboot.org/658 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 21:17:47 2012 From: gerrit at coreboot.org (Martin Roth (martin@se-eng.com)) Date: Fri, 17 Feb 2012 21:17:47 +0100 Subject: [coreboot] New patch to review for coreboot: a47f09d AGESA family 12 changes to fix torpedo warnings References: Message-ID: Martin Roth (martin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/667 -gerrit commit a47f09d8e723896eb63ae8437250c0ee7ce68da9 Author: Martin Roth Date: Fri Feb 17 13:16:04 2012 -0700 AGESA family 12 changes to fix torpedo warnings Fixes the warnings generated in the torpedo mainboard build by AGESA. Removing broken tests. Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b Signed-off-by: Martin L Roth --- .../amd/agesa/f12/Include/OptionMemoryInstall.h | 9 +++++ .../amd/agesa/f12/Include/PlatformInstall.h | 32 +++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h index 35825d8..cfb55cc 100755 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h @@ -44,6 +44,10 @@ #ifndef _OPTION_MEMORY_INSTALL_H_ #define _OPTION_MEMORY_INSTALL_H_ +#ifndef RUN_BROKEN_AGESA_TESTS + #define RUN_BROKEN_AGESA_TESTS 0 +#endif + /*------------------------------------------------------------------------------- * This option file is designed to be included into the platform solution install * file. The platform solution install file will define the options status. @@ -3395,9 +3399,14 @@ BOOLEAN MemFS3DefConstructorRet ( NULL }; CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); +/* SIZE_OF_PLATFORM is not defined when the preprocessor runs + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES #endif +#endif /*--------------------------------------------------------------------------------------------------- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h index 50275eb..ba8bc1f 100755 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h @@ -42,6 +42,10 @@ * ***************************************************************************/ +#ifndef RUN_BROKEN_AGESA_TESTS + #define RUN_BROKEN_AGESA_TESTS 0 +#endif + /***************************************************************************** * * Start processing the user options: First, set default settings @@ -76,7 +80,7 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , - '0000', + Int32FromChar ('0', '0', '0', '0'), //ModuleIdentifier[8] AGESA_ID, //ModuleVersion[12] @@ -2150,6 +2154,10 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #error No Dram init option has been selected #endif #endif +/* As an ENUM, DDRXXX_FREQUENCY is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS // Ensure the frequency limit is valid #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) @@ -2168,6 +2176,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif + +#endif +/* As an ENUM, TIMING_MODE_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + // Ensure timing mode is valid #if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED @@ -2176,6 +2191,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif + +#endif // Ensure the scrub rate is valid #if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) #error BLDCFG: Unsupported dram scrub rate set @@ -2192,12 +2209,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #if CFG_SCRUB_DC_RATE > 0x16 #error BLDCFG: Unsupported Dcache scrub rate set #endif +/* As an ENUM, QUADRANK_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + // Ensure Quad rank dimm type is valid #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED #error BLDCFG: Invalid quad rank dimm type set #endif #endif + +#endif // Ensure ECC symbol size is valid #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 @@ -2206,6 +2230,11 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif +/* As an ENUM, POWER_DOWN_BY_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + // Ensure power down mode is valid #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL @@ -2213,6 +2242,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif +#endif /***************************************************************************** * * Process the option logic, setting local control variables From gerrit at coreboot.org Fri Feb 17 22:41:40 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:41:40 +0100 Subject: [coreboot] Patch merged into coreboot/master: cd19125 amd/sb800: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit cd191255004e3701096e0f7fc810e3e29456f80d Author: Patrick Georgi Date: Thu Feb 16 20:03:28 2012 +0100 amd/sb800: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. (cimx/sb800 is a "different" chipset) Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 22:28:45 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:00:44 2012, giving +2 See http://review.coreboot.org/666 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 22:41:42 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:41:42 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7a2d314 intel/sch: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 7a2d3142f8f4d7c606c1f7e46a7d1e478e77b5fb Author: Patrick Georgi Date: Thu Feb 16 19:58:51 2012 +0100 intel/sch: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 22:15:35 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:07:28 2012, giving +2 See http://review.coreboot.org/665 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 22:41:45 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:41:45 +0100 Subject: [coreboot] Patch merged into coreboot/master: 89e5ccc intel/i82801ex: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 89e5ccc70f88e9391b12e3658c9bdfe28d590741 Author: Patrick Georgi Date: Thu Feb 16 19:58:00 2012 +0100 intel/i82801ex: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 22:02:41 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:07:36 2012, giving +2 See http://review.coreboot.org/664 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 22:41:56 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:41:56 +0100 Subject: [coreboot] Patch merged into coreboot/master: ce3ab07 sis/sis966: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit ce3ab07e387c24eddbd08ca5ac67ae7259bae8b8 Author: Patrick Georgi Date: Thu Feb 16 19:56:50 2012 +0100 sis/sis966: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 21:49:48 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:07:43 2012, giving +2 See http://review.coreboot.org/663 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 22:42:04 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:42:04 +0100 Subject: [coreboot] Patch merged into coreboot/master: 4163c03 intel/i82801cx: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 4163c03b2d713131a863fbf2ec636feb3a983d3e Author: Patrick Georgi Date: Thu Feb 16 19:53:21 2012 +0100 intel/i82801cx: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 21:36:16 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:07:51 2012, giving +2 See http://review.coreboot.org/662 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 22:42:07 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:42:07 +0100 Subject: [coreboot] Patch merged into coreboot/master: 44b094e amd/sb700: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 44b094ea4156f4f368c4ee40b34b1afa7efc2f17 Author: Patrick Georgi Date: Thu Feb 16 19:52:16 2012 +0100 amd/sb700: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1 Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 21:21:59 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:19:19 2012, giving +2 See http://review.coreboot.org/661 for details. -gerrit From gerrit at coreboot.org Fri Feb 17 22:42:10 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 17 Feb 2012 22:42:10 +0100 Subject: [coreboot] Patch merged into coreboot/master: c5be342 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit c5be3428454dc29fb28b0d7a507fa4ef7e707fa3 Author: Patrick Georgi Date: Thu Feb 16 19:44:28 2012 +0100 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi Build-Tested: build bot (Jenkins) at Fri Feb 17 20:34:20 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 19:19:29 2012, giving +2 See http://review.coreboot.org/659 for details. -gerrit From c-d.hailfinger.devel.2006 at gmx.net Sat Feb 18 03:10:25 2012 From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger) Date: Sat, 18 Feb 2012 03:10:25 +0100 Subject: [coreboot] Patchwork/Django anti-spam cleanup script Message-ID: <4F3F0891.4090807@gmx.net> In case you ever want to clean a Patchwork instance of spam registrations and assuming that nothing on your site besides Patchwork uses Django, try the following script which should kill a majority of spam accounts. Disclaimer: This script is an absolutely gross 5-minute hack, and it should remove all inactive accounts with all associated data. If you deactivated real users, they will vanish as well. I wrote this killer script after I noticed that 99% of the spam accounts in coreboot patchwork were inactive. License of this script is WTFPL 2.0 # use w3m to log in to patchwork for ((i=0; i<1980; i++)); do w3m -cookie http://patchwork.yoursite.org/admin/auth/user/$i -dump|grep "Active\|Date\|Time" >$i.txt; echo -n .; done fgrep -l "[ ]Active" *txt|cut -f 1 -d.|while read a; do grep "Date:\|Time:" $a.txt|sort -u|wc -l|grep -q "^2$" && echo $a; done|while read b; do w3m -cookie http://patchwork.yoursite.org/admin/auth/user/$b/delete/ -dump -cols 200 >$b.del; done # inspect *.del and check if any .del file mentions data you want to keep # extract the cookie value from your w3m cookie cache ls *.del|cut -f 1 -d.|while read a; do curl --data post=yes --cookie sessionid=123456789abcdef http://patchwork.yoursite.org/admin/auth/user/$a/delete/ ; done Regards, Carl-Daniel -- http://www.hailfinger.org/ From gerrit at coreboot.org Sat Feb 18 13:58:22 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sat, 18 Feb 2012 13:58:22 +0100 Subject: [coreboot] Patch set updated for coreboot: 09e71a9 Intel model_6ex: apply some good programming practices in CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643 -gerrit commit 09e71a9782e7687ac0c769f141fd1ac1b05c3844 Author: Ky?sti M?lkki Date: Sat Feb 18 14:35:03 2012 +0200 Intel model_6ex: apply some good programming practices in CAR Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/model_6ex/cache_as_ram.inc | 23 +++++++++++++---------- 1 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index cbfa4f8..5a29744 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -21,6 +21,10 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) @@ -37,9 +41,9 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -91,11 +95,10 @@ clear_mtrrs: movl %eax, %cr0 /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ @@ -130,11 +133,10 @@ clear_mtrrs: /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -145,6 +147,7 @@ clear_mtrrs: /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f) From gerrit at coreboot.org Mon Feb 20 05:35:01 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 05:35:01 +0100 Subject: [coreboot] Patch merged into coreboot/master: 41897bc IEI Kino Fam10 ACPI table fixes. References: Message-ID: the following patch was just integrated into master: commit 41897bc521632641b9b9053a73caa9d828019bba Author: Dave Frodin Date: Thu Feb 2 14:07:43 2012 -0700 IEI Kino Fam10 ACPI table fixes. Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup. Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 01:19:20 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 23:26:47 2012, giving +2 See http://review.coreboot.org/628 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 05:35:14 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 05:35:14 +0100 Subject: [coreboot] Patch merged into coreboot/master: 25ccaa5 IEI-Kino Fam10 MPtable fix. References: Message-ID: the following patch was just integrated into master: commit 25ccaa54982ced9c697f58dc978a0d252763e766 Author: Dave Frodin Date: Thu Feb 2 13:38:50 2012 -0700 IEI-Kino Fam10 MPtable fix. Make changes to MPtable to match the ACPI tables. Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1 Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 01:30:33 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 23:26:55 2012, giving +2 See http://review.coreboot.org/629 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 05:36:18 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 05:36:18 +0100 Subject: [coreboot] Patch merged into coreboot/master: 95aad86 Fixes Fam10/SR5650 cpu not recognized message. References: Message-ID: the following patch was just integrated into master: commit 95aad867212c87fde722934a536e14ca78f0c9f9 Author: Dave Frodin Date: Thu Feb 2 15:08:22 2012 -0700 Fixes Fam10/SR5650 cpu not recognized message. Extend the Family10 revisions checked byt the printk message. Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44 Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 02:14:04 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 23:29:37 2012, giving +2 See http://review.coreboot.org/633 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 05:36:42 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 05:36:42 +0100 Subject: [coreboot] Patch merged into coreboot/master: b1443cb Torpedo mainboard changes to fix warnings. References: Message-ID: the following patch was just integrated into master: commit b1443cb4c25f6efa6d0ffc388dbfb8f36c8f15f4 Author: Martin Roth Date: Tue Feb 14 10:50:11 2012 -0700 Torpedo mainboard changes to fix warnings. Fixes the warnings generated in the torpedo mainboard build. Most of these changes are similar to fixes already implemented in the persimmon mainboard. Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5 Signed-off-by: Martin L Roth Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 22:35:26 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 23:31:20 2012, giving +2 See http://review.coreboot.org/634 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 05:37:29 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 05:37:29 +0100 Subject: [coreboot] Patch merged into coreboot/master: ee068e8 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. References: Message-ID: the following patch was just integrated into master: commit ee068e84d951b1d198007371d767b920e82ba149 Author: Marc Jones Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 22:16:41 2012, giving +1 Reviewed-By: Stefan Reinauer at Fri Feb 17 22:44:19 2012, giving +2 See http://review.coreboot.org/627 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 10:38:00 2012 From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com)) Date: Mon, 20 Feb 2012 10:38:00 +0100 Subject: [coreboot] Patch set updated for coreboot: 2703285 libpayload: fix compile error with enabled USB_DEBUG References: Message-ID: Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/653 -gerrit commit 270328581ec7881676f9d808483953026e473ff1 Author: Mathias Krause Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause --- payloads/libpayload/drivers/usb/ohci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 4095d69..3a1b51d 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -190,7 +190,7 @@ dump_td(td_t *cur, int level) const char *spc=spaces+(10-level); debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[(cur->config & TD_DIRECTION_MASK) >> TD_DIRECTION_SHIFT], completion_codes[(cur->config & TD_CC_MASK) >> TD_CC_SHIFT]); - debug("%s toggle: %x\n", spc, cur->toggle); + debug("%s toggle: %x\n", spc, !!(cur->config & TD_TOGGLE_DATA1)); #endif } From svn at coreboot.org Mon Feb 20 16:00:01 2012 From: svn at coreboot.org (coreboot tracker) Date: Mon, 20 Feb 2012 16:00:01 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From darmawan.salihun at gmail.com Mon Feb 20 17:16:46 2012 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Mon, 20 Feb 2012 23:16:46 +0700 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: References: <20120214205258.GA26278@coreboot.org> Message-ID: Hi Ron, I've been looking for DDR-SDRAM start-up tutorial. Is there any on the web outside of the JEDEC specs? Anyway, where are the codes located in the Coreboot source ? is it on the motherboard-specific codes? TIA, Darmawan On 2/15/12, ron minnich wrote: > reading your note leads me to believe you are not familiar with how > sdram startup works. It's a lot more than just setting one register. > > ron > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From darmawan.salihun at gmail.com Mon Feb 20 17:22:50 2012 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Mon, 20 Feb 2012 23:22:50 +0700 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: References: <20120214205258.GA26278@coreboot.org> Message-ID: Well, sorry about the noise. I forgot to mention that most of the RAM init I found was in the raminit.c of each of the northbridge. Is there any other important file(s) that I missed? Thanks, Darmawan On 2/20/12, Darmawan Salihun wrote: > Hi Ron, > > I've been looking for DDR-SDRAM start-up tutorial. Is there any on the > web outside of the JEDEC specs? Anyway, where are the codes located in > the Coreboot source ? is it on the motherboard-specific codes? > > TIA, > > Darmawan > > On 2/15/12, ron minnich wrote: >> reading your note leads me to believe you are not familiar with how >> sdram startup works. It's a lot more than just setting one register. >> >> ron >> >> -- >> coreboot mailing list: coreboot at coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > -------------------------------------------------------------------- > -= Human knowledge belongs to the world =- > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From rminnich at gmail.com Mon Feb 20 17:51:17 2012 From: rminnich at gmail.com (ron minnich) Date: Mon, 20 Feb 2012 08:51:17 -0800 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: References: <20120214205258.GA26278@coreboot.org> Message-ID: you commented out a number of calls to critical functions. You can't just simply set a register and assume it all works. Maybe I misunderstood. I think stepan's i945 code is a great example of how to turn on dram. Or you can look at sdram_enable in the lx440 code for the basic sdram startup cycle. Don't look at the reset of that code, I am not sure it was ever tested on real hardware, there's a comment in there about qemu I don't understand. The lx440 was the second (or first) linuxbios mainboard, but that's not my code, so I'm just not sure about it. ron From gerrit at coreboot.org Mon Feb 20 18:58:08 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 18:58:08 +0100 Subject: [coreboot] Patch merged into coreboot/master: 213eb80 Force SB800 bootblock to use I/O for PCI config References: Message-ID: the following patch was just integrated into master: commit 213eb80a8a071403ca9448dc08b8e00b95f31e67 Author: Dave Frodin Date: Thu Feb 2 14:56:23 2012 -0700 Force SB800 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O. Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0 Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 01:41:13 2012, giving +1 Reviewed-By: Stefan Reinauer at Mon Feb 20 18:51:38 2012, giving +2 See http://review.coreboot.org/630 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 18:58:22 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 18:58:22 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3a72344 Force SB700 bootblock code to use I/O for PCI config cycles. References: Message-ID: the following patch was just integrated into master: commit 3a7234421e81fa4a5b86be12de07c220ac0ccf5b Author: Dave Frodin Date: Wed Feb 1 16:15:08 2012 -0700 Force SB700 bootblock code to use I/O for PCI config cycles. If PCI config cycles use MMIO instead of I/O in the SB700 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is specified by the mainboards Kconfig. Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672 Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 01:52:19 2012, giving +1 Reviewed-By: Stefan Reinauer at Mon Feb 20 18:51:59 2012, giving +2 See http://review.coreboot.org/631 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 18:58:32 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 18:58:32 +0100 Subject: [coreboot] Patch merged into coreboot/master: 0d7d667 Force SB600 bootblock to use I/O for PCI config References: Message-ID: the following patch was just integrated into master: commit 0d7d6676e9c1def4d26432aa481752dbbabd3bec Author: Dave Frodin Date: Thu Feb 2 14:50:02 2012 -0700 Force SB600 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the SB600 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is defined by the mainboards Kconfig. Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Tue Feb 14 02:03:05 2012, giving +1 Reviewed-By: Stefan Reinauer at Mon Feb 20 18:52:11 2012, giving +2 See http://review.coreboot.org/632 for details. -gerrit From gerrit at coreboot.org Mon Feb 20 21:46:34 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 20 Feb 2012 21:46:34 +0100 Subject: [coreboot] Patch merged into coreboot/master: 2703285 libpayload: fix compile error with enabled USB_DEBUG References: Message-ID: the following patch was just integrated into master: commit 270328581ec7881676f9d808483953026e473ff1 Author: Mathias Krause Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause Build-Tested: build bot (Jenkins) at Mon Feb 20 10:57:47 2012, giving +1 Reviewed-By: Peter Stuge at Mon Feb 20 21:46:32 2012, giving +2 See http://review.coreboot.org/653 for details. -gerrit From darmawan.salihun at gmail.com Tue Feb 21 06:47:13 2012 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Tue, 21 Feb 2012 12:47:13 +0700 Subject: [coreboot] porting Coreboot to a new motherboard.... In-Reply-To: References: <20120214205258.GA26278@coreboot.org> Message-ID: Thanks Ron. I'm looking into it. On 2/20/12, ron minnich wrote: > you commented out a number of calls to critical functions. You can't > just simply set a register and assume it all works. Maybe I > misunderstood. > > I think stepan's i945 code is a great example of how to turn on dram. > Or you can look at sdram_enable in the lx440 code for the basic sdram > startup cycle. Don't look at the reset of that code, I am not sure it > was ever tested on real hardware, there's a comment in there about > qemu I don't understand. The lx440 was the second (or first) linuxbios > mainboard, but that's not my code, so I'm just not sure about it. > > ron > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From kyosti.malkki at gmail.com Tue Feb 21 09:39:33 2012 From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=) Date: Tue, 21 Feb 2012 10:39:33 +0200 Subject: [coreboot] Real-mode trouble with hyper-threaded CPU Message-ID: <1329813573.5785.580.camel@obelix> So I have been working with hyper-threaded P4 NetBurst CPUs. Currently I have a dual-socket 604 with model f25 P4 Xeon CPUs that boots with the CAR code I have made available in git [1]. I have received a report of a non-HT f27 booting with my code [1] on a different mainboard and socket 478. On that mainboard, hyper-threaded non-Xeon P4 CPU models f29 and f49 fail before console. Using POST codes, we have traced the issue this far: 1. BSP CPU has successfully sent Start-Up IPI to AP CPU. 2. AP CPU has successfully received Start-Up IPI and has entered ap_sipi_vector and executes code from src/cpu/x86/16bit/entry16.inc At the time AP CPU executes "lidt", it seems both BSP and AP CPUs halt. a) Any reference to this null-limit method in Intel literature? b) Both limit of 0 and base of 0x00 for IDT seem incorrect to me. That would mean IDT is one byte at non-existing RAM adress 0x00. c) There is a longish explanation of LGDT parameter calculation. Why is this not applied to LIDT? Thanks, KM [1] http://review.coreboot.org/607 From gerrit at coreboot.org Tue Feb 21 17:44:35 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Tue, 21 Feb 2012 17:44:35 +0100 Subject: [coreboot] New patch to review for coreboot: ee18b94 Revert "Fix multipleVGA cards resource conflict on Windows" References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/668 -gerrit commit ee18b943ef7de736dfa103d66ec1fb1820a49a98 Author: Marc Jones Date: Tue Feb 21 17:44:35 2012 +0100 Revert "Fix multipleVGA cards resource conflict on Windows" This reverts commit b7929add7bf1b40795e0a16ab08fc47858971ccc This commit has been found to cause problems with vbios and option rom init in seabios. It has been found by several people and requires more analysis before being recommitted. --- src/devices/device.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 8ad9787..a2619bf 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -932,6 +932,10 @@ void dev_configure(void) struct device *root; struct device *child; +#if CONFIG_VGA_BRIDGE_SETUP == 1 + set_vga_bridge_bits(); +#endif + printk(BIOS_INFO, "Allocating resources...\n"); root = &dev_root; @@ -1024,10 +1028,6 @@ void dev_configure(void) printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); -#if CONFIG_VGA_BRIDGE_SETUP == 1 - set_vga_bridge_bits(); -#endif - printk(BIOS_INFO, "Done allocating resources.\n"); } From gerrit at coreboot.org Tue Feb 21 22:44:30 2012 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Tue, 21 Feb 2012 22:44:30 +0100 Subject: [coreboot] New patch to review for coreboot: d8759cd asus/m4a785t-m: correct the CPU microcode patch selection References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/669 -gerrit commit d8759cd8725469489ac9cc0b83bb53c0d51e54ed Author: Denis 'GNUtoo' Carikli Date: Tue Feb 21 22:29:30 2012 +0100 asus/m4a785t-m: correct the CPU microcode patch selection Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 ruik at ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explaned(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 633b994..727ae0c 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -68,7 +68,7 @@ config IRQ_SLOT_COUNT config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000c4.h" + default "mc_patch_0100009f.h" config RAMTOP hex From gerrit at coreboot.org Tue Feb 21 22:58:54 2012 From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org)) Date: Tue, 21 Feb 2012 22:58:54 +0100 Subject: [coreboot] Patch set updated for coreboot: 6bfce95 asus/m4a785t-m: correct the CPU microcode patch selection References: Message-ID: Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/669 -gerrit commit 6bfce95ce462ea42f08b20a846e07b4c37681b2c Author: Denis 'GNUtoo' Carikli Date: Tue Feb 21 22:29:30 2012 +0100 asus/m4a785t-m: correct the CPU microcode patch selection Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 ruik at ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explained(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli --- src/mainboard/asus/m4a785t-m/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 633b994..727ae0c 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -68,7 +68,7 @@ config IRQ_SLOT_COUNT config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000c4.h" + default "mc_patch_0100009f.h" config RAMTOP hex From gerrit at coreboot.org Wed Feb 22 01:09:35 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 22 Feb 2012 01:09:35 +0100 Subject: [coreboot] New patch to review for coreboot: 90fc6a1 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670 -gerrit commit 90fc6a1bb7ca57a24e6d0456cb6323fb384b55e2 Author: Marc Jones Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<GStatus &= ~(1<Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..582a1f2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6f6767a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + print_tx(" ECC enabled on node: ", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } From gerrit at coreboot.org Wed Feb 22 01:35:05 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 22 Feb 2012 01:35:05 +0100 Subject: [coreboot] Patch set updated for coreboot: 2724d28 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670 -gerrit commit 2724d286cbad4ae8a3a6f63719bc1098cc94360f Author: Marc Jones Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<GStatus &= ~(1<Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..d126a95 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6f6767a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + print_tx(" ECC enabled on node: ", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } From gerrit at coreboot.org Wed Feb 22 01:46:33 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 22 Feb 2012 01:46:33 +0100 Subject: [coreboot] New patch to review for coreboot: 617edf7 Revert "Fix multipleVGA cards resource conflict on Windows" References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/671 -gerrit commit 617edf7e746df87616e4ada8a40decabe1231341 Author: Marc Jones Date: Tue Feb 21 17:44:35 2012 +0100 Revert "Fix multipleVGA cards resource conflict on Windows" This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e This commit has been found to cause problems with vbios and option rom init in seabios. It has been found by several people and requires more analysis before being recommitted. Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230 Signed-off-by: Marc Jones --- src/devices/device.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 8ad9787..a2619bf 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -932,6 +932,10 @@ void dev_configure(void) struct device *root; struct device *child; +#if CONFIG_VGA_BRIDGE_SETUP == 1 + set_vga_bridge_bits(); +#endif + printk(BIOS_INFO, "Allocating resources...\n"); root = &dev_root; @@ -1024,10 +1028,6 @@ void dev_configure(void) printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); -#if CONFIG_VGA_BRIDGE_SETUP == 1 - set_vga_bridge_bits(); -#endif - printk(BIOS_INFO, "Done allocating resources.\n"); } From gerrit at coreboot.org Wed Feb 22 01:55:49 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 22 Feb 2012 01:55:49 +0100 Subject: [coreboot] New patch to review for coreboot: 3d3abb2 Remove old AMD fam10 fixme comment References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/672 -gerrit commit 3d3abb2e9ce3a175c9182b6bc3ad17bc3487735b Author: Marc Jones Date: Tue Feb 21 17:53:13 2012 -0700 Remove old AMD fam10 fixme comment The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones --- src/mainboard/amd/mahogany_fam10/romstage.c | 1 - .../amd/serengeti_cheetah_fam10/romstage.c | 1 - src/mainboard/amd/tilapia_fam10/romstage.c | 1 - src/mainboard/asus/m4a78-em/romstage.c | 1 - src/mainboard/asus/m4a785-m/romstage.c | 1 - src/mainboard/gigabyte/ma785gmt/romstage.c | 1 - src/mainboard/gigabyte/ma78gm/romstage.c | 1 - src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 - src/mainboard/jetway/pa78vm5/romstage.c | 1 - src/mainboard/msi/ms9652_fam10/romstage.c | 1 - src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 - src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 - src/mainboard/tyan/s2912_fam10/romstage.c | 1 - 13 files changed, 0 insertions(+), 13 deletions(-) diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 04a9e45..dce9baa 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index b41230d..29b00b2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -331,7 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 52cab42..f316395 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 76449cb..a96592d 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 76449cb..a96592d 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 4572169..68f3dcc 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bd81e67..6c25a9e 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 54b364a..f51b3ec 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -222,7 +222,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index b2d4ecb..ba3b208 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -227,7 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index fc8120b..0bf6d11 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -241,7 +241,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c9fb928..4e243c2 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -240,7 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 870125d..d9d5218 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -290,7 +290,6 @@ post_code(0x40); raminit_amdmct(sysinfo); post_code(0x41); -// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 97c03b5..df571a0 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -238,7 +238,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } From gerrit at coreboot.org Wed Feb 22 02:03:25 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 22 Feb 2012 02:03:25 +0100 Subject: [coreboot] Patch set updated for coreboot: 15e268e Fix ECC disable option for AMD Fam10 DDR2 and DDR3. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670 -gerrit commit 15e268ee435d7d6f8d76997336efb38c4732042e Author: Marc Jones Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<GStatus &= ~(1<Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..d126a95 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6107e80 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + printk(BIOS_DEBUG, " ECC enabled on node: %02x\n", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node); + printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status); + printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus); + printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode); + printk(BIOS_DEBUG, "ECCInit: Done\n"); + } + } return MemClrECC; } From hillmands at gmail.com Wed Feb 22 03:53:09 2012 From: hillmands at gmail.com (David Hillman) Date: Tue, 21 Feb 2012 21:53:09 -0500 Subject: [coreboot] Asus M2V-MX memory init Message-ID: Northbridge: K8M890 Southbridge: VT8237A Superio: ITE IT8716F I finally got past booting this board. The system boots fine with a 2GB stick of memory, but it freezes with 4GB. It looks like I am missing something to properly initialize memory to get correct SPD info. Maybe SMBUS isn't working properly? What should I check? Here is the log for 4GB (2 sticks): coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change Current fid_cur: 0x2, fid_max: 0x12 Requested fid_new: 0x12 FidVid table step fidvid: 0xe FidVid table step fidvid: 0x10 200MHZ step fidvid: 0x12 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000ceee8 Device error Device error Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved RAM end at 0x00400000 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce950 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 Writing 18171819 of size 4 to nvram pos: 17 Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 Writing 113222 of size 4 to nvram pos: 30 Writing 15141615 of size 4 to nvram pos: 34 Writing 15141515 of size 4 to nvram pos: 38 Writing 15 of size 1 to nvram pos: 42 Writing 202520 of size 4 to nvram pos: 43 Writing 17191818 of size 4 to nvram pos: 47 Writing 18191716 of size 4 to nvram pos: 51 Writing 16 of size 1 to nvram pos: 55 Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 Writing 7410809b of size 4 to nvram pos: 60 DQS Training:tsc[00]=000000008cbdd63c DQS Training:tsc[01]=000000008f476e2e DQS Training:tsc[02]=000000008f476e37 DQS Training:tsc[03]=000000015b152149 DQS Training:tsc[04]=000000016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a IN TEST WAKEUP 800Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (622592 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [1106/0336] ops VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled Capability: type 0x02 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x08 @ 0x60 flags: 0x0060 PCI: 00:00.0 count: 0003 static_count: 0014 PCI: 00:00.0 [1106/0336] enabled next_unitid: 0014 PCI: pci_scan_bus for bus 00 VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled PCI: 00:00.1 [1106/1336] ops K8x8xx: Enabling NB error reporting: Done VIA_X_1 device dump: 00: 06 11 36 13 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.1 [1106/1336] enabled PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops K8M890: UMA base is fa000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff 30 00 fc 19 00 fc 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.3 [1106/3336] enabled PCI: 00:00.4 [1106/4336] enabled PCI: 00:00.5 [1106/5336] ops PCI: 00:00.5 [1106/5336] enabled PCI: 00:00.6 [1106/6290] enabled PCI: 00:00.7 [1106/7336] ops PCI: 00:00.7 [1106/7336] enabled PCI: 00:01.0 [1106/b188] bus ops B188 device dump 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 40: 91 40 08 44 31 3a 88 b1 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 0e 70 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 80 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.0 [1106/b188] enabled PCI: 00:02.0 [1106/a238] bus ops Configuring PCIe PEG 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c 12 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 07 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 PCIe link timeout 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 7c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c f0 40 81 00 00 03 00 01 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 0b 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 [1106/a238] enabled PCI: 00:03.0 [1106/c238] bus ops Configuring PCIe PEXs 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 PCIe link up after 15100 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 [1106/c238] enabled PCI: 00:0f.0 [1106/0591] ops PCI: 00:0f.0 [1106/0591] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled PCI: 00:11.0 [1106/3337] bus ops PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled PCI: Static device PCI: 00:12.0 not found, disabling it. Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.0 [1106/337b] enabled Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.1 [1106/337a] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3230] ops PCI: 01:00.0 [1106/3230] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [197b/2363] enabled PCI: pci_scan_bus returning with max=003 Capability: type 0x01 @ 0x68 Capability: type 0x10 @ 0x50 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:11.0 smbus: PCI: 00:11.0[0]->I2C: 01:50 enabled smbus: PCI: 00:11.0[0]->I2C: 01:51 enabled smbus: PCI: 00:11.0[0]->I2C: 01:52 enabled smbus: PCI: 00:11.0[0]->I2C: 01:53 enabled PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 disabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:11.0 done do_pci_scan_bridge for PCI: 00:13.0 PCI: pci_scan_bus for bus 04 PCI: 04:01.0 [1106/3288] enabled PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:13.1 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:02.0 read_resources bus 2 link: 0 PCI: 00:02.0 read_resources bus 2 link: 0 done PCI: 00:03.0 read_resources bus 3 link: 0 PCI: 00:03.0 read_resources bus 3 link: 0 done PCI: 00:11.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:11.0 read_resources bus 1 link: 0 done PCI: 00:13.0 read_resources bus 4 link: 0 PCI: 00:13.0 read_resources bus 4 link: 0 done PCI: 00:13.1 read_resources bus 5 link: 0 PCI: 00:13.1 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8 PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 10000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 03:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 03:00.0 20 * [0x0 - 0xf] io PCI: 03:00.0 10 * [0x10 - 0x17] io PCI: 03:00.0 18 * [0x18 - 0x1f] io PCI: 03:00.0 14 * [0x20 - 0x23] io PCI: 03:00.0 1c * [0x24 - 0x27] io PCI: 00:03.0 compute_resources_io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 1c * [0x0 - 0xfff] io PCI: 00:0f.0 24 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI: 00:18.0 compute_resources_io: base: 14b8 size: 2000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 24 * [0x10000000 - 0x1fffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 14 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:01.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 30 * [0x0 - 0xffff] mem PCI: 03:00.0 24 * [0x10000 - 0x11fff] mem PCI: 00:03.0 compute_resources_mem: base: 12000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:01.0 10 * [0x0 - 0x3fff] mem PCI: 00:13.0 compute_resources_mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.5 61 * [0x0 - 0xfffffff] mem PCI: 00:01.0 20 * [0x10000000 - 0x110fffff] mem PCI: 00:03.0 20 * [0x11100000 - 0x111fffff] mem PCI: 00:13.0 20 * [0x11200000 - 0x112fffff] mem PCI: 00:10.4 10 * [0x11300000 - 0x113000ff] mem PCI: 00:18.0 compute_resources_mem: base: 11300100 size: 11400000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 02 * [0x0 - 0x1fffffff] prefmem PCI: 00:18.0 01 * [0x20000000 - 0x313fffff] mem PCI: 00:18.3 94 * [0x34000000 - 0x37ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.5 constrain_resources: PCI: 00:00.6 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:11.0 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.4 constrain_resources: PCI: 00:11.7 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 04:01.0 constrain_resources: PCI: 00:13.1 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:ffff Assigned: PCI: 00:03.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:0f.0 24 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI: 00:18.0 allocate_resources_io: next_base: 24b8 size: 2000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:00.0 20 * [0x1000 - 0x100f] io Assigned: PCI: 03:00.0 10 * [0x1010 - 0x1017] io Assigned: PCI: 03:00.0 18 * [0x1018 - 0x101f] io Assigned: PCI: 03:00.0 14 * [0x1020 - 0x1023] io Assigned: PCI: 03:00.0 1c * [0x1024 - 0x1027] io PCI: 00:03.0 allocate_resources_io: next_base: 1028 size: 1000 align: 12 gran: 12 done PCI: 00:13.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:13.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:febfffff Assigned: PCI: 00:18.0 02 * [0xc0000000 - 0xdfffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xe0000000 - 0xf13fffff] mem Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.0 10 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:01.0 24 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:d0000000 size:10000000 align:28 gran:20 limit:febfffff Assigned: PCI: 01:00.0 10 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: e0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:e0000000 size:11400000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.5 61 * [0xe0000000 - 0xefffffff] mem Assigned: PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem Assigned: PCI: 00:03.0 20 * [0xf1100000 - 0xf11fffff] mem Assigned: PCI: 00:13.0 20 * [0xf1200000 - 0xf12fffff] mem Assigned: PCI: 00:10.4 10 * [0xf1300000 - 0xf13000ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: f1300100 size: 11400000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:f0000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 01:00.0 14 * [0xf0000000 - 0xf0ffffff] mem Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf100ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: f1010000 size: 1100000 align: 24 gran: 20 done PCI: 00:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:f1100000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 03:00.0 30 * [0xf1100000 - 0xf110ffff] mem Assigned: PCI: 03:00.0 24 * [0xf1110000 - 0xf1111fff] mem PCI: 00:03.0 allocate_resources_mem: next_base: f1112000 size: 100000 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_mem: base:f1200000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 04:01.0 10 * [0xf1200000 - 0xf1203fff] mem PCI: 00:13.0 allocate_resources_mem: next_base: f1204000 size: 100000 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 node 0 : uma_memory_base/1024=0x003e8000, mmio_basek=0x00300000, basek=0x00000300, limitk=0x00400000 split: 1088K table at =f9ef0000 0: mmio_basek=00300000, basek=00300000, limitk=00400000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 prefmem PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f13fffff] size 0x11400000 gran 0x14 mem PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:00.0 14 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f100ffff] size 0x00010000 gran 0x10 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:03.0 20 <- [0x00f1100000 - 0x00f11fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 03:00.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io PCI: 03:00.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io PCI: 03:00.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io PCI: 03:00.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 03:00.0 24 <- [0x00f1110000 - 0x00f1111fff] size 0x00002000 gran 0x0d mem PCI: 03:00.0 30 <- [0x00f1100000 - 0x00f110ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00f1300000 - 0x00f13000ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 1 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000230 - 0x0000000237] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PCI: 00:11.0 assign_resources, bus 1 link: 0 PCI: 00:13.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:13.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:13.0 20 <- [0x00f1200000 - 0x00f12fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 04:01.0 10 <- [0x00f1200000 - 0x00f1203fff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 00:13.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:13.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:13.1 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base c0000000 size 3fffe000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI_DOMAIN: 0000 resource base fa000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff flags 60080100 index 1c0 PCI: 00:18.0 resource base c0000000 size 20000000 align 28 gran 20 limit febfffff flags 60081200 index 1b8 PCI: 00:18.0 resource base e0000000 size 11400000 align 28 gran 20 limit febfffff flags 60080200 index 1b0 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 70000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base d0000000 size 10000000 align 28 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base d0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 14 PCI: 01:00.0 resource base f1000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:03.0 resource base f1100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 03:00.0 resource base f1110000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 24 PCI: 03:00.0 resource base f1100000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base f1300000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.0 resource base f1200000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base f1200000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/0000 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/0000 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/0000 PCI: 00:00.0 cmd <- 02 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 cmd <- 06 PCI: 00:00.3 cmd <- 06 PCI: 00:00.4 cmd <- 06 PCI: 00:00.5 cmd <- 06 PCI: 00:00.6 cmd <- 06 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 001f PCI: 00:01.0 cmd <- 07 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 07 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 01 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:11.0 subsystem <- 1043/0000 PCI: 00:11.0 cmd <- 01 PCI: 00:11.7 cmd <- 00 PCI: 00:13.0 bridge ctrl <- 0003 PCI: 00:13.0 cmd <- 07 PCI: 00:13.1 bridge ctrl <- 0003 PCI: 00:13.1 cmd <- 01 PCI: 01:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 03 PCI: 04:01.0 cmd <- 02 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 50ff3 CPU: family 0f, model 5f, stepping 03 Enabling cache CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 4000MB, range: 32MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 Processor 4000+ Setting up local apic... apic_id: 0x00 done. Scrubbing Disabled ECC Disabled CPU #0 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:18.1 init Searching for pci1022,1101.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1101.rom'. PCI: 00:18.2 init Searching for pci1022,1102.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1102.rom'. PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:00.0 init PCI: 00:00.3 init K8M890: Using a 32MB framebuffer. PCI: 00:00.4 init Searching for pci1106,4336.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,4336.rom'. PCI: 00:00.6 init Searching for pci1106,6290.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,6290.rom'. PCI: 00:00.7 init K8x8xx: Initializing V-Link to VT8237R sb: VT8237R LPC not found ! PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0xb Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:11.0 init SLP_TYP type was 800 0 RTC Init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 00: 06 11 37 33 01 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 7f f8 0b 00 00 00 00 0c 20 00 00 44 00 00 08 50: c0 0d 09 00 00 00 00 00 43 80 00 0b 00 00 00 00 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 90: 00 04 99 88 a0 cc 00 02 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 08 00 24 69 10 80 00 00 00 00 04 00 00 00 f0: 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00 PCI: 00:11.7 init 00: 06 11 7e 28 00 00 10 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 50: 00 03 33 03 00 04 01 fc 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: fd 3f df 00 00 00 00 e0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 50 ee 88 8a 88 00 03 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 19 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 b0 00 00 00 PCI: 01:00.0 init Chrome: Using 32MB Framebuffer at 0xD0000000. Chrome VGA Textmode initialized. PCI: 03:00.0 init Searching for pci197b,2363.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci197b,2363.rom'. On card, ROM address for PCI: 03:00.0 = f1100000 PCI expansion ROM, signature 0x7f7f, INIT size 0xfe00, data ptr 0x7f7f Incorrect expansion ROM header signature 7f7f PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.3 init PNP: 002e.4 init FAN_CTL: reg = 0x02a9, read value = 0x50 FAN_CTL: reg = 0x02a9, writing value = 0xd7 PCI: 04:01.0 init Searching for pci1106,3288.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,3288.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.5: enabled 1 PCI: 00:00.6: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.7: enabled 1 PCI: 01:00.0: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 Initializing CBMEM area to 0xf9ef0000 (1114112 bytes) ERROR: CBMEM was not initialized yet. Error: Could not relocate GDT. High Tables Base is f9ef0000. ERROR: CBMEM was not initialized yet. ACPI: Writing ACPI tables at f0000... ACPI: * FACS ACPI: * DSDT @ 000f0140 Length ba5 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET ACPI: added table 2/32, length now 44 ACPI: * MADT ACPI: added table 3/32, length now 48 ACPI: * MCFG ACPI: added table 4/32, length now 52 ACPI: * SRAT SRAT: lapic cpu_index=00, node_id=00, apic_id=00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00300000, sizek=ffff8000 ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 ACPI: * SSDT processor_brand=AMD Athlon(tm) 64 Processor 4000+ Pstates Algorithm ... Pstate_freq[0] = 2600MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw Pstate_freq[1] = 2400MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 566975mw Pstate_freq[2] = 2200MHz Pstate_vid[2] = 12 Pstate_volt[2] = 1250mv Pstate_power[2] = 480516mw Pstate_freq[3] = 2000MHz Pstate_vid[3] = 14 Pstate_volt[3] = 1200mv Pstate_power[3] = 402585mw Pstate_freq[4] = 1000MHz Pstate_vid[4] = 18 Pstate_volt[4] = 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. ERROR: CBMEM was not initialized yet. smbios_write_tables: 000f1400 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) PCI_DOMAIN: 0000 (AMD K8 Root Complex) PCI: 00:18.0 (AMD K8 Northbridge) PCI: 00:00.0 (VIA VT8237R Southbridge) PCI: 00:0f.1 (VIA VT8237R Southbridge) PCI: 00:11.0 (VIA VT8237R Southbridge) I2C: 01:50 () I2C: 01:51 () I2C: 01:52 () I2C: 01:53 () PNP: 002e.0 (ITE IT8716F Super I/O) PNP: 002e.1 (ITE IT8716F Super I/O) PNP: 002e.2 (ITE IT8716F Super I/O) PNP: 002e.3 (ITE IT8716F Super I/O) PNP: 002e.4 (ITE IT8716F Super I/O) PNP: 002e.5 (ITE IT8716F Super I/O) PNP: 002e.6 (ITE IT8716F Super I/O) PNP: 002e.7 (ITE IT8716F Super I/O) PNP: 002e.8 (ITE IT8716F Super I/O) PNP: 002e.9 (ITE IT8716F Super I/O) PNP: 002e.a (ITE IT8716F Super I/O) PCI: 00:12.0 (VIA VT8237R Southbridge) PCI: 00:13.0 (VIA VT8237R Southbridge) PCI: 00:13.1 (VIA VT8237R Southbridge) PCI: 00:18.1 (AMD K8 Northbridge) PCI: 00:18.2 (AMD K8 Northbridge) PCI: 00:18.3 (AMD K8 Northbridge) PCI: 00:00.1 () PCI: 00:00.2 () PCI: 00:00.3 () PCI: 00:00.4 () PCI: 00:00.5 () PCI: 00:00.6 () PCI: 00:00.7 () PCI: 00:01.0 () PCI: 00:02.0 () PCI: 00:03.0 () PCI: 00:0f.0 () PCI: 00:10.0 () PCI: 00:10.1 () PCI: 00:10.2 () PCI: 00:10.3 () PCI: 00:10.4 () PCI: 00:11.7 () PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () SMBIOS size 277 bytes ERROR: CBMEM was not initialized yet. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum eaaf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x000f1520 rom_table_end = 0x000f1520 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x000f1520 to 0x00100000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000000effff: RAM 3. 00000000000f0000-00000000000fffff: CONFIGURATION TABLES 4. 0000000000100000-00000000bfffffff: RAM 5. 00000000c0000000-00000000dfffffff: RAM 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000f0000000-00000000f9eeffff: RAM 8. 00000000f9ef0000-00000000f9ffffff: CONFIGURATION TABLES 9. 00000000fa000000-00000000fbffffff: RESERVED 10. 00000000fc000000-00000000febfffff: RAM 11. 00000000fec00000-00000000fec000ff: RESERVED 12. 00000000fec00100-00000000fecbffff: RAM 13. 00000000fecc0000-00000000fecc00ff: RESERVED 14. 00000000fecc0100-00000000feffffff: RAM 15. 00000000ff000000-00000000ffffffff: RESERVED 16. 0000000100000000-00000400bdffffff: RAM Wrote coreboot table at: 000f1520 - 000f17d4 checksum f32e ERROR: CBMEM was not initialized yet. Multiboot Information structure has been written. Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfffad538 data (compression=1) New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8ba (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8ba Loading segment from rom address 0xfffad554 Entry Point 0x00000000 No matching ram area found for range: [0x00000000000e6b54, 0x0000000000100000) Ram areas [0x0000000000000000, 0x0000000000001000) Reserved [0x0000000000001000, 0x00000000000a0000) RAM [0x00000000000c0000, 0x00000000000f0000) RAM [0x00000000000f0000, 0x0000000000100000) Reserved [0x0000000000100000, 0x00000000c0000000) RAM [0x00000000c0000000, 0x00000000e0000000) RAM [0x00000000e0000000, 0x00000000f0000000) Reserved [0x00000000f0000000, 0x00000000f9ef0000) RAM [0x00000000f9ef0000, 0x00000000fa000000) Reserved [0x00000000fa000000, 0x00000000fc000000) Reserved [0x00000000fc000000, 0x00000000fec00000) RAM [0x00000000fec00000, 0x00000000fec00100) Reserved [0x00000000fec00100, 0x00000000fecc0000) RAM [0x00000000fecc0000, 0x00000000fecc0100) Reserved [0x00000000fecc0100, 0x00000000ff000000) RAM [0x00000000ff000000, 0x0000000000000000) Reserved [0x0000000000000000, 0x00000000be000000) RAM SELFBOOT RETURNED! Boot failed. ======================================================= ...and 2GB (1 stick): coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change Current fid_cur: 0x2, fid_max: 0x12 Requested fid_new: 0x12 FidVid table step fidvid: 0xe FidVid table step fidvid: 0x10 200MHZ step fidvid: 0x12 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000ceee8 Device error Device error Device error Unbuffered 400MHz 400MHz Interleaved RAM end at 0x00200000 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce950 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=43 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 Writing 17161515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 Writing 17171918 of size 4 to nvram pos: 17 Writing 17191718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 Writing 33 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 Writing 111222 of size 4 to nvram pos: 30 Writing 0 of size 4 to nvram pos: 34 Writing 0 of size 4 to nvram pos: 38 Writing 0 of size 1 to nvram pos: 42 Writing 0 of size 4 to nvram pos: 43 Writing 2f2f2f2f of size 4 to nvram pos: 47 Writing 2f2f2f2f of size 4 to nvram pos: 51 Writing 0 of size 1 to nvram pos: 55 Writing 43 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 Writing 741080ab of size 4 to nvram pos: 60 DQS Training:tsc[00]=000000005eac6acb DQS Training:tsc[01]=000000006087914d DQS Training:tsc[02]=0000000060879156 DQS Training:tsc[03]=00000000df309c2e DQS Training:tsc[04]=00000000f2a194b3 Ram4 v_esp=000cef28 testx = 5a5a5a5a IN TEST WAKEUP 800Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (622592 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [1106/0336] ops VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled Capability: type 0x02 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x08 @ 0x60 flags: 0x0060 PCI: 00:00.0 count: 0003 static_count: 0014 PCI: 00:00.0 [1106/0336] enabled next_unitid: 0014 PCI: pci_scan_bus for bus 00 VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled PCI: 00:00.1 [1106/1336] ops K8x8xx: Enabling NB error reporting: Done VIA_X_1 device dump: 00: 06 11 36 13 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.1 [1106/1336] enabled PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops K8M890: UMA base is 7e000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff 30 00 80 19 00 80 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.3 [1106/3336] enabled PCI: 00:00.4 [1106/4336] enabled PCI: 00:00.5 [1106/5336] ops PCI: 00:00.5 [1106/5336] enabled PCI: 00:00.6 [1106/6290] enabled PCI: 00:00.7 [1106/7336] ops PCI: 00:00.7 [1106/7336] enabled PCI: 00:01.0 [1106/b188] bus ops B188 device dump 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 40: 91 40 08 44 31 3a 88 b1 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 0e 70 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 80 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.0 [1106/b188] enabled PCI: 00:02.0 [1106/a238] bus ops Configuring PCIe PEG 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c 12 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 07 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 PCIe link timeout 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 7c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c f0 40 81 00 00 03 00 01 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 0b 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 [1106/a238] enabled PCI: 00:03.0 [1106/c238] bus ops Configuring PCIe PEXs 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 PCIe link up after 15000 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 [1106/c238] enabled PCI: 00:0f.0 [1106/0591] ops PCI: 00:0f.0 [1106/0591] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled PCI: 00:11.0 [1106/3337] bus ops PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.0 [1106/337b] enabled Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.1 [1106/337a] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3230] ops PCI: 01:00.0 [1106/3230] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [197b/2363] enabled PCI: pci_scan_bus returning with max=003 Capability: type 0x01 @ 0x68 Capability: type 0x10 @ 0x50 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:11.0 smbus: PCI: 00:11.0[0]->I2C: 01:50 enabled smbus: PCI: 00:11.0[0]->I2C: 01:51 enabled smbus: PCI: 00:11.0[0]->I2C: 01:52 enabled smbus: PCI: 00:11.0[0]->I2C: 01:53 enabled PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 disabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:11.0 done do_pci_scan_bridge for PCI: 00:13.0 PCI: pci_scan_bus for bus 04 PCI: 04:01.0 [1106/3288] enabled PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:13.1 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:02.0 read_resources bus 2 link: 0 PCI: 00:02.0 read_resources bus 2 link: 0 done PCI: 00:03.0 read_resources bus 3 link: 0 PCI: 00:03.0 read_resources bus 3 link: 0 done PCI: 00:11.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:11.0 read_resources bus 1 link: 0 done PCI: 00:13.0 read_resources bus 4 link: 0 PCI: 00:13.0 read_resources bus 4 link: 0 done PCI: 00:13.1 read_resources bus 5 link: 0 PCI: 00:13.1 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8 PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 10000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 03:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 03:00.0 20 * [0x0 - 0xf] io PCI: 03:00.0 10 * [0x10 - 0x17] io PCI: 03:00.0 18 * [0x18 - 0x1f] io PCI: 03:00.0 14 * [0x20 - 0x23] io PCI: 03:00.0 1c * [0x24 - 0x27] io PCI: 00:03.0 compute_resources_io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 1c * [0x0 - 0xfff] io PCI: 00:0f.0 24 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI: 00:18.0 compute_resources_io: base: 14b8 size: 2000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 24 * [0x10000000 - 0x1fffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 14 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:01.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 30 * [0x0 - 0xffff] mem PCI: 03:00.0 24 * [0x10000 - 0x11fff] mem PCI: 00:03.0 compute_resources_mem: base: 12000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:01.0 10 * [0x0 - 0x3fff] mem PCI: 00:13.0 compute_resources_mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.5 61 * [0x0 - 0xfffffff] mem PCI: 00:01.0 20 * [0x10000000 - 0x110fffff] mem PCI: 00:03.0 20 * [0x11100000 - 0x111fffff] mem PCI: 00:13.0 20 * [0x11200000 - 0x112fffff] mem PCI: 00:10.4 10 * [0x11300000 - 0x113000ff] mem PCI: 00:18.0 compute_resources_mem: base: 11300100 size: 11400000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 02 * [0x0 - 0x1fffffff] prefmem PCI: 00:18.0 01 * [0x20000000 - 0x313fffff] mem PCI: 00:18.3 94 * [0x34000000 - 0x37ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.5 constrain_resources: PCI: 00:00.6 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:11.0 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.4 constrain_resources: PCI: 00:11.7 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 04:01.0 constrain_resources: PCI: 00:13.1 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:ffff Assigned: PCI: 00:03.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:0f.0 24 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI: 00:18.0 allocate_resources_io: next_base: 24b8 size: 2000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:00.0 20 * [0x1000 - 0x100f] io Assigned: PCI: 03:00.0 10 * [0x1010 - 0x1017] io Assigned: PCI: 03:00.0 18 * [0x1018 - 0x101f] io Assigned: PCI: 03:00.0 14 * [0x1020 - 0x1023] io Assigned: PCI: 03:00.0 1c * [0x1024 - 0x1027] io PCI: 00:03.0 allocate_resources_io: next_base: 1028 size: 1000 align: 12 gran: 12 done PCI: 00:13.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:13.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:febfffff Assigned: PCI: 00:18.0 02 * [0xc0000000 - 0xdfffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xe0000000 - 0xf13fffff] mem Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.0 10 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:01.0 24 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:d0000000 size:10000000 align:28 gran:20 limit:febfffff Assigned: PCI: 01:00.0 10 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: e0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:e0000000 size:11400000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.5 61 * [0xe0000000 - 0xefffffff] mem Assigned: PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem Assigned: PCI: 00:03.0 20 * [0xf1100000 - 0xf11fffff] mem Assigned: PCI: 00:13.0 20 * [0xf1200000 - 0xf12fffff] mem Assigned: PCI: 00:10.4 10 * [0xf1300000 - 0xf13000ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: f1300100 size: 11400000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:f0000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 01:00.0 14 * [0xf0000000 - 0xf0ffffff] mem Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf100ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: f1010000 size: 1100000 align: 24 gran: 20 done PCI: 00:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:f1100000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 03:00.0 30 * [0xf1100000 - 0xf110ffff] mem Assigned: PCI: 03:00.0 24 * [0xf1110000 - 0xf1111fff] mem PCI: 00:03.0 allocate_resources_mem: next_base: f1112000 size: 100000 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_mem: base:f1200000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 04:01.0 10 * [0xf1200000 - 0xf1203fff] mem PCI: 00:13.0 allocate_resources_mem: next_base: f1204000 size: 100000 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 node 0 : uma_memory_base/1024=0x001f8000, mmio_basek=0x00300000, basek=0x00000300, limitk=0x00200000 node 0: UMA memory starts below mmio_basek 0: mmio_basek=00300000, basek=00000300, limitk=00200000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 prefmem PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f13fffff] size 0x11400000 gran 0x14 mem PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:00.0 14 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f100ffff] size 0x00010000 gran 0x10 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:03.0 20 <- [0x00f1100000 - 0x00f11fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 03:00.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io PCI: 03:00.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io PCI: 03:00.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io PCI: 03:00.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 03:00.0 24 <- [0x00f1110000 - 0x00f1111fff] size 0x00002000 gran 0x0d mem PCI: 03:00.0 30 <- [0x00f1100000 - 0x00f110ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00f1300000 - 0x00f13000ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 1 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000230 - 0x0000000237] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PCI: 00:11.0 assign_resources, bus 1 link: 0 PCI: 00:13.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:13.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:13.0 20 <- [0x00f1200000 - 0x00f12fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 04:01.0 10 <- [0x00f1200000 - 0x00f1203fff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 00:13.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:13.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:13.1 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size 7df40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 7e000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff flags 60080100 index 1c0 PCI: 00:18.0 resource base c0000000 size 20000000 align 28 gran 20 limit febfffff flags 60081200 index 1b8 PCI: 00:18.0 resource base e0000000 size 11400000 align 28 gran 20 limit febfffff flags 60080200 index 1b0 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 70000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base d0000000 size 10000000 align 28 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base d0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 14 PCI: 01:00.0 resource base f1000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:03.0 resource base f1100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 03:00.0 resource base f1110000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 24 PCI: 03:00.0 resource base f1100000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base f1300000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.0 resource base f1200000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base f1200000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/0000 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/0000 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/0000 PCI: 00:00.0 cmd <- 02 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 cmd <- 06 PCI: 00:00.3 cmd <- 06 PCI: 00:00.4 cmd <- 06 PCI: 00:00.5 cmd <- 06 PCI: 00:00.6 cmd <- 06 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 001f PCI: 00:01.0 cmd <- 07 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 07 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 01 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:11.0 subsystem <- 1043/0000 PCI: 00:11.0 cmd <- 01 PCI: 00:11.7 cmd <- 00 PCI: 00:13.0 bridge ctrl <- 0003 PCI: 00:13.0 cmd <- 07 PCI: 00:13.1 bridge ctrl <- 0003 PCI: 00:13.1 cmd <- 01 PCI: 01:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 03 PCI: 04:01.0 cmd <- 02 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 50ff3 CPU: family 0f, model 5f, stepping 03 Enabling cache CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 2016MB, range: 32MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 Processor 4000+ Setting up local apic... apic_id: 0x00 done. Scrubbing Disabled ECC Disabled CPU #0 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:18.1 init Searching for pci1022,1101.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1101.rom'. PCI: 00:18.2 init Searching for pci1022,1102.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1102.rom'. PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:00.0 init PCI: 00:00.3 init K8M890: Using a 32MB framebuffer. PCI: 00:00.4 init Searching for pci1106,4336.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,4336.rom'. PCI: 00:00.6 init Searching for pci1106,6290.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,6290.rom'. PCI: 00:00.7 init K8x8xx: Initializing V-Link to VT8237R sb: VT8237R LPC not found ! PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0xb Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:11.0 init SLP_TYP type was 800 0 RTC Init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 00: 06 11 37 33 01 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 7f f8 0b 00 00 00 00 0c 20 00 00 44 00 00 08 50: c0 0d 09 00 00 00 00 00 43 80 00 0b 00 00 00 00 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 90: 00 06 19 88 a0 cc 00 00 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 08 00 24 69 10 80 00 00 00 00 04 00 00 00 f0: 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00 PCI: 00:11.7 init 00: 06 11 7e 28 00 00 10 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 50: 00 03 33 03 00 04 01 80 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: fd 3f df 00 00 00 00 e0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 50 ee 88 8a 88 00 03 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 19 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 b0 00 00 00 PCI: 01:00.0 init Chrome: Using 32MB Framebuffer at 0xD0000000. Chrome VGA Textmode initialized. PCI: 03:00.0 init Searching for pci197b,2363.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci197b,2363.rom'. On card, ROM address for PCI: 03:00.0 = f1100000 PCI expansion ROM, signature 0x7f7f, INIT size 0xfe00, data ptr 0x7f7f Incorrect expansion ROM header signature 7f7f PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.3 init PNP: 002e.4 init FAN_CTL: reg = 0x02a9, read value = 0x50 FAN_CTL: reg = 0x02a9, writing value = 0xd7 PCI: 04:01.0 init Searching for pci1106,3288.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,3288.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.5: enabled 1 PCI: 00:00.6: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.7: enabled 1 PCI: 01:00.0: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 Initializing CBMEM area to 0x7def0000 (1114112 bytes) Adding CBMEM entry as no. 1 Moving GDT to 7def0200...ok High Tables Base is 7def0000. Adding CBMEM entry as no. 2 ACPI: Writing ACPI tables at 7def0400... ACPI: * FACS ACPI: * DSDT @ 7def0540 Length ba5 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET ACPI: added table 2/32, length now 44 ACPI: * MADT ACPI: added table 3/32, length now 48 ACPI: * MCFG ACPI: added table 4/32, length now 52 ACPI: * SRAT SRAT: lapic cpu_index=00, node_id=00, apic_id=00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001f7d00 ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 ACPI: * SSDT processor_brand=AMD Athlon(tm) 64 Processor 4000+ Pstates Algorithm ... Pstate_freq[0] = 2600MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw Pstate_freq[1] = 2400MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 566975mw Pstate_freq[2] = 2200MHz Pstate_vid[2] = 12 Pstate_volt[2] = 1250mv Pstate_power[2] = 480516mw Pstate_freq[3] = 2000MHz Pstate_vid[3] = 14 Pstate_volt[3] = 1200mv Pstate_power[3] = 402585mw Pstate_freq[4] = 1000MHz Pstate_vid[4] = 18 Pstate_volt[4] = 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. ACPI tables: 4677 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 7defb800 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) PCI_DOMAIN: 0000 (AMD K8 Root Complex) PCI: 00:18.0 (AMD K8 Northbridge) PCI: 00:00.0 (VIA VT8237R Southbridge) PCI: 00:0f.1 (VIA VT8237R Southbridge) PCI: 00:11.0 (VIA VT8237R Southbridge) I2C: 01:50 () I2C: 01:51 () I2C: 01:52 () I2C: 01:53 () PNP: 002e.0 (ITE IT8716F Super I/O) PNP: 002e.1 (ITE IT8716F Super I/O) PNP: 002e.2 (ITE IT8716F Super I/O) PNP: 002e.3 (ITE IT8716F Super I/O) PNP: 002e.4 (ITE IT8716F Super I/O) PNP: 002e.5 (ITE IT8716F Super I/O) PNP: 002e.6 (ITE IT8716F Super I/O) PNP: 002e.7 (ITE IT8716F Super I/O) PNP: 002e.8 (ITE IT8716F Super I/O) PNP: 002e.9 (ITE IT8716F Super I/O) PNP: 002e.a (ITE IT8716F Super I/O) PCI: 00:12.0 (VIA VT8237R Southbridge) PCI: 00:13.0 (VIA VT8237R Southbridge) PCI: 00:13.1 (VIA VT8237R Southbridge) PCI: 00:18.1 (AMD K8 Northbridge) PCI: 00:18.2 (AMD K8 Northbridge) PCI: 00:18.3 (AMD K8 Northbridge) PCI: 00:00.1 () PCI: 00:00.2 () PCI: 00:00.3 () PCI: 00:00.4 () PCI: 00:00.5 () PCI: 00:00.6 () PCI: 00:00.7 () PCI: 00:01.0 () PCI: 00:02.0 () PCI: 00:03.0 () PCI: 00:0f.0 () PCI: 00:10.0 () PCI: 00:10.1 () PCI: 00:10.2 () PCI: 00:10.3 () PCI: 00:10.4 () PCI: 00:11.7 () PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () SMBIOS tables: 277 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum c1ee New low_table_end: 0x00000518 Now going to write high coreboot table at 0x7defc000 rom_table_end = 0x7defc000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x7defc000 to 0x7df00000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000007deeffff: RAM 3. 000000007def0000-000000007dffffff: CONFIGURATION TABLES 4. 000000007e000000-000000007fffffff: RESERVED 5. 00000000e0000000-00000000efffffff: RESERVED 6. 00000000fec00000-00000000fec000ff: RESERVED 7. 00000000fecc0000-00000000fecc00ff: RESERVED 8. 00000000ff000000-00000000ffffffff: RESERVED Wrote coreboot table at: 7defc000 - 7defc214 checksum 336b coreboot table: 532 bytes. Adding CBMEM entry as no. 5 Multiboot Information structure has been written. 0. FREE SPACE 7dffe000 00002000 1. GDT 7def0200 00000200 2. ACPI 7def0400 0000b400 3. SMBIOS 7defb800 00000800 4. COREBOOT 7defc000 00002000 5. ACPI RESUME7defe000 00100000 Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfffad538 data (compression=1) New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8aa (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8aa Loading segment from rom address 0xfffad554 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: 0x000000000000c8aa lb: [0x0000000000100000, 0x0000000000198000) Post relocation: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: 0x000000000000c8aa using LZMA [ 0x000e6b54, 00100000, 0x00100000) <- fffad570 dest 000e6b54, end 00100000, bouncebuffer 7ddc0000 Loaded segments Jumping to boot code at fc8e4 entry = 0x000fc8e4 lb_start = 0x00100000 lb_size = 0x00098000 adjust = 0x7dd58000 buffer = 0x7ddc0000 elf_boot_notes = 0x001270c8 adjusted_boot_notes = 0x7de7f0c8 Start bios (version 1.6.3-20120215_224505-debby) Found mainboard ASUS M2V-MX Found CBFS header at 0xfffffc00 Ram Size=0x7def0000 (0x0000000000000000 high) Relocating init from 0x000e7340 to 0x7ded5190 (size 44356) CPU Mhz=2603 Found 29 PCI devices (max PCI bus is 05) Found 1 cpu(s) max supported 1 cpu(s) Copying ACPI RSDP from 0x7def0400 to 0x000fdb40 Copying SMBIOS entry point from 0x7defb800 to 0x000fdb20 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.6.3-20120215_224505-debby) EHCI init on dev 00:10.4 (regs=0xf1300010) Found 1 lpt ports Found 1 serial ports ATA controller 1 at 24a0/24b0/0 (irq 0 dev 78) ATA controller 2 at 24a8/24b4/0 (irq 0 dev 78) ATA controller 3 at 1f0/3f4/0 (irq 14 dev 79) ATA controller 4 at 170/374/0 (irq 15 dev 79) ebda moved from 9fc00 to 9f400 AHCI controller at 60.0, iobase f1110000, irq 0 UHCI init on dev 00:10.0 (io=2400) UHCI init on dev 00:10.1 (io=2420) UHCI init on dev 00:10.2 (io=2440) UHCI init on dev 00:10.3 (io=2460) AHCI/0: link down AHCI/1: link down DVD/CD [ata1-0: PLDS DVD+/-RW DH-16AAS ATAPI-8 DVD/CD] Searching bootorder for: /pci at i0cf8/*@f/drive at 1/disk at 0 Got ps2 nak (status=d1) ebda moved from 9f400 to 9f000 USB keyboard initialized ata0-0: Hitachi HDT721010SLA360 ATA-8 Hard-Disk (931 GiBytes) Searching bootorder for: /pci at i0cf8/*@f/drive at 0/disk at 0 All threads complete. Scan for option roms Press F12 for boot menu. drive 0x000fda60: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168 Returned 53248 bytes of ZoneHigh e820 map has 9 items: 0: 0000000000000000 - 000000000009f000 = 1 RAM 1: 000000000009f000 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007deed000 = 1 RAM 4: 000000007deed000 - 0000000080000000 = 2 RESERVED 5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED 6: 00000000fec00000 - 00000000fec00100 = 2 RESERVED 7: 00000000fecc0000 - 00000000fecc0100 = 2 RESERVED 8: 00000000ff000000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... 606MB medium detected Booting from 0000:7c00 -------------- next part -------------- An HTML attachment was scrubbed... URL: From peter at stuge.se Wed Feb 22 04:40:06 2012 From: peter at stuge.se (Peter Stuge) Date: Wed, 22 Feb 2012 04:40:06 +0100 Subject: [coreboot] Asus M2V-MX memory init In-Reply-To: References: Message-ID: <20120222034006.29372.qmail@stuge.se> David Hillman wrote: > It looks like I am missing something to properly initialize memory > to get correct SPD info. Maybe SMBUS isn't working properly? I think SMBUS is OK and memory init too. Here's the diff between your two logs with some comments, but there may be more relevant stuff than what I see. Next time when posting logs please make sure that they do not wrap. One good way is to send them as attachments, under all circumstances with text/plain mime type. --- m2v_mx-2g 2012-02-22 04:13:21.309138502 +0100 +++ m2v_mx-4g 2012-02-22 04:13:02.663139149 +0100 @@ -1,4 +1,4 @@ -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings @@ -47,16 +47,21 @@ sdram_set_spd_registers: paramx :000ceee8 Device error Device error -Device error +Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved -RAM end at 0x00200000 kB +RAM end at 0x00400000 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB +Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB +Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB +Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB +Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB +Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done @@ -68,41 +73,45 @@ TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 - CTLRMaxDelay=43 + CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 -Writing 17161515 of size 4 to nvram pos: 4 +Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 -Writing 17171918 of size 4 to nvram pos: 17 -Writing 17191718 of size 4 to nvram pos: 21 +Writing 18171819 of size 4 to nvram pos: 17 +Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 -Writing 33 of size 1 to nvram pos: 26 +Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 -Writing 111222 of size 4 to nvram pos: 30 -Writing 0 of size 4 to nvram pos: 34 -Writing 0 of size 4 to nvram pos: 38 -Writing 0 of size 1 to nvram pos: 42 -Writing 0 of size 4 to nvram pos: 43 -Writing 2f2f2f2f of size 4 to nvram pos: 47 -Writing 2f2f2f2f of size 4 to nvram pos: 51 -Writing 0 of size 1 to nvram pos: 55 -Writing 43 of size 1 to nvram pos: 56 +Writing 113222 of size 4 to nvram pos: 30 +Writing 15141615 of size 4 to nvram pos: 34 +Writing 15141515 of size 4 to nvram pos: 38 +Writing 15 of size 1 to nvram pos: 42 +Writing 202520 of size 4 to nvram pos: 43 +Writing 17191818 of size 4 to nvram pos: 47 +Writing 18191716 of size 4 to nvram pos: 51 +Writing 16 of size 1 to nvram pos: 55 +Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 -Writing 741080ab of size 4 to nvram pos: 60 -DQS Training:tsc[00]=000000005eac6acb -DQS Training:tsc[01]=000000006087914d -DQS Training:tsc[02]=0000000060879156 -DQS Training:tsc[03]=00000000df309c2e -DQS Training:tsc[04]=00000000f2a194b3 +Writing 7410809b of size 4 to nvram pos: 60 +DQS Training:tsc[00]=000000008cbdd63c +DQS Training:tsc[01]=000000008f476e2e +DQS Training:tsc[02]=000000008f476e37 +DQS Training:tsc[03]=000000015b152149 +DQS Training:tsc[04]=000000016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a @@ -121,7 +130,7 @@ 0x100000 Stage: done loading. Jumping to image. -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 @@ -147,7 +156,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 -PCI: 00:12.0: enabled 0 +PCI: 00:12.0: enabled 1 Why is 12.0 enabled with 4G? What is 12.0? PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -177,7 +186,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 - PCI: 00:12.0: enabled 0 + PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -265,7 +274,7 @@ PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops -K8M890: UMA base is 7e000000 size is 32 (MB) +K8M890: UMA base is fa000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -275,7 +284,7 @@ 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80: ff ff ff 30 00 80 19 00 80 00 00 00 00 00 00 00 +80: ff ff ff 30 00 fc 19 00 fc 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -363,7 +372,7 @@ d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 -PCI: 00:03.0 PCIe link up after 15000 us +PCI: 00:03.0 PCIe link up after 15100 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 @@ -399,6 +408,7 @@ PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled +PCI: Static device PCI: 00:12.0 not found, disabling it. Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 @@ -978,10 +988,10 @@ PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 -node 0 : uma_memory_base/1024=0x001f8000, mmio_basek=0x00300000, -basek=0x00000300, limitk=0x00200000 -node 0: UMA memory starts below mmio_basek -0: mmio_basek=00300000, basek=00000300, limitk=00200000 +node 0 : uma_memory_base/1024=0x003e8000, mmio_basek=0x00300000, +basek=0x00000300, limitk=0x00400000 + split: 1088K table at =f9ef0000 +0: mmio_basek=00300000, basek=00300000, limitk=00400000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link @@ -1114,9 +1124,11 @@ limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 - PCI_DOMAIN: 0000 resource base c0000 size 7df40000 align 0 gran 0 limit 0 + PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 - PCI_DOMAIN: 0000 resource base 7e000000 size 2000000 align 0 gran 0 limit + PCI_DOMAIN: 0000 resource base c0000000 size 3fffe000000 align 0 gran 0 limit 0 flags e0004200 index 30 + PCI_DOMAIN: 0000 resource base fa000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 The size for the c0000000 domain is crazy. This is worth looking into further. I did some manual line unwrapping above. The email had extra line endings damaging the log messages. It will be easier for you if you fix that. PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff @@ -1368,7 +1380,9 @@ DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff -Setting variable MTRR 1, base: 2016MB, range: 32MB, type UC +Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB +ADDRESS_MASK_HIGH=0xff +Setting variable MTRR 2, base: 4000MB, range: 32MB, type UC Find out why the 32 MB framebuffer ends at TOM on 2GB, but ends at TOM-64MB on 4GB, what the top 64MB is for. Hopefully PCI resources but 64MB is unexpectedly small for that. Investigate. ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's @@ -1493,7 +1507,7 @@ 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 -90: 00 06 19 88 a0 cc 00 00 00 3a 00 00 00 00 00 00 +90: 00 04 99 88 a0 cc 00 02 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -1506,7 +1520,7 @@ 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 -50: 00 03 33 03 00 04 01 80 08 00 01 80 00 00 00 00 +50: 00 03 33 03 00 04 01 fc 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -1605,14 +1619,14 @@ PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 -Initializing CBMEM area to 0x7def0000 (1114112 bytes) -Adding CBMEM entry as no. 1 -Moving GDT to 7def0200...ok -High Tables Base is 7def0000. -Adding CBMEM entry as no. 2 -ACPI: Writing ACPI tables at 7def0400... +Initializing CBMEM area to 0xf9ef0000 (1114112 bytes) +ERROR: CBMEM was not initialized yet. +Error: Could not relocate GDT. +High Tables Base is f9ef0000. +ERROR: CBMEM was not initialized yet. This is very bad. Investigate. The CBMEM code should be easy to follow. +ACPI: Writing ACPI tables at f0000... ACPI: * FACS -ACPI: * DSDT @ 7def0540 Length ba5 +ACPI: * DSDT @ 000f0140 Length ba5 So with 2GB ACPI tables are written high, with 4GB because CBMEM fails they end up in F-segment. ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET @@ -1626,7 +1640,9 @@ set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 -set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001f7d00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00300000, sizek=ffff8000 At least the last one is bogus. ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 @@ -1645,9 +1661,8 @@ 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. -ACPI tables: 4677 bytes. -Adding CBMEM entry as no. 3 -smbios_write_tables: 7defb800 +ERROR: CBMEM was not initialized yet. +smbios_write_tables: 000f1400 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) @@ -1697,36 +1712,37 @@ PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () -SMBIOS tables: 277 bytes. -Adding CBMEM entry as no. 4 +SMBIOS size 277 bytes +ERROR: CBMEM was not initialized yet. Writing high table forward entry at 0x00000500 -Wrote coreboot table at: 00000500 - 00000518 checksum c1ee +Wrote coreboot table at: 00000500 - 00000518 checksum eaaf New low_table_end: 0x00000518 -Now going to write high coreboot table at 0x7defc000 -rom_table_end = 0x7defc000 +Now going to write high coreboot table at 0x000f1520 +rom_table_end = 0x000f1520 Adjust low_table_end from 0x00000518 to 0x00001000 -Adjust rom_table_end from 0x7defc000 to 0x7df00000 +Adjust rom_table_end from 0x000f1520 to 0x00100000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM - 2. 00000000000c0000-000000007deeffff: RAM - 3. 000000007def0000-000000007dffffff: CONFIGURATION TABLES - 4. 000000007e000000-000000007fffffff: RESERVED - 5. 00000000e0000000-00000000efffffff: RESERVED - 6. 00000000fec00000-00000000fec000ff: RESERVED - 7. 00000000fecc0000-00000000fecc00ff: RESERVED - 8. 00000000ff000000-00000000ffffffff: RESERVED -Wrote coreboot table at: 7defc000 - 7defc214 checksum 336b -coreboot table: 532 bytes. -Adding CBMEM entry as no. 5 + 2. 00000000000c0000-00000000000effff: RAM + 3. 00000000000f0000-00000000000fffff: CONFIGURATION TABLES + 4. 0000000000100000-00000000bfffffff: RAM + 5. 00000000c0000000-00000000dfffffff: RAM + 6. 00000000e0000000-00000000efffffff: RESERVED + 7. 00000000f0000000-00000000f9eeffff: RAM + 8. 00000000f9ef0000-00000000f9ffffff: CONFIGURATION TABLES + 9. 00000000fa000000-00000000fbffffff: RESERVED +10. 00000000fc000000-00000000febfffff: RAM +11. 00000000fec00000-00000000fec000ff: RESERVED +12. 00000000fec00100-00000000fecbffff: RAM +13. 00000000fecc0000-00000000fecc00ff: RESERVED +14. 00000000fecc0100-00000000feffffff: RAM +15. 00000000ff000000-00000000ffffffff: RESERVED +16. 0000000100000000-00000400bdffffff: RAM Here, coreboot says that you have almost 4 TB of RAM. Investigate. +Wrote coreboot table at: 000f1520 - 000f17d4 checksum f32e +ERROR: CBMEM was not initialized yet. Multiboot Information structure has been written. - 0. FREE SPACE 7dffe000 00002000 - 1. GDT 7def0200 00000200 - 2. ACPI 7def0400 0000b400 - 3. SMBIOS 7defb800 00000800 - 4. COREBOOT 7defc000 00002000 - 5. ACPI RESUME7defe000 00100000 Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom @@ -1737,26 +1753,30 @@ Loading segment from rom address 0xfffad538 data (compression=1) - New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8aa - (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8aa + New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8ba + (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8ba Loading segment from rom address 0xfffad554 Entry Point 0x00000000 -Loading Segment: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: -0x000000000000c8aa -lb: [0x0000000000100000, 0x0000000000198000) -Post relocation: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: -0x000000000000c8aa -using LZMA -[ 0x000e6b54, 00100000, 0x00100000) <- fffad570 -dest 000e6b54, end 00100000, bouncebuffer 7ddc0000 -Loaded segments -Jumping to boot code at fc8e4 -entry = 0x000fc8e4 -lb_start = 0x00100000 -lb_size = 0x00098000 -adjust = 0x7dd58000 -buffer = 0x7ddc0000 - elf_boot_notes = 0x001270c8 -adjusted_boot_notes = 0x7de7f0c8 -Start bios (version 1.6.3-20120215_224505-debby) +No matching ram area found for range: + [0x00000000000e6b54, 0x0000000000100000) And finally instead of the "Start bios" message from SeaBIOS it's not possible to load the payload to it's address, because.. +Ram areas + [0x0000000000000000, 0x0000000000001000) Reserved + [0x0000000000001000, 0x00000000000a0000) RAM + [0x00000000000c0000, 0x00000000000f0000) RAM + [0x00000000000f0000, 0x0000000000100000) Reserved ..the F segment has been marked reserved, because this is where the ACPI tables were written to, because the highmem address was not available, because CBMEM failed to initialize. The error isn't really with hardware init I believe, but with calculation, generation and preparation of system description data for the payload and later the operating system. You need to find out why coreboot gets upset with 4G of memory. //Peter From oliver at schinagl.nl Wed Feb 22 10:35:54 2012 From: oliver at schinagl.nl (Oliver Schinagl) Date: Wed, 22 Feb 2012 10:35:54 +0100 Subject: [coreboot] flash-chip (and compatibles) In-Reply-To: <20120216014402.29039.qmail@stuge.se> References: <4E4D2BC4.1010607@schinagl.nl> <4E4D2C9C.8050704@schinagl.nl> <4F3C553C.6060509@schinagl.nl> <20120216014402.29039.qmail@stuge.se> Message-ID: <4F44B6FA.8070509@schinagl.nl> Having trouble ordering from several webshops in Europe (The only want to send you parts if you order in huge quantities or if you are a company) I've found the following at digikey in the US. http://search.digikey.com/nl/en/products/SST25VF032B-80-4I-S2AF/SST25VF032B-80-4I-S2AF-ND/2297800 http://search.digikey.com/nl/en/products/W25Q64FVSSIG/W25Q64FVSSIG-ND/2815931 I know they are 8-SOIC but have ordered (and received) 8-SOIC -> 8-DIP pcb's so can easily convert between the sockets. I guess these should work just fine? On 16-02-12 02:44, Peter Stuge wrote: > Oliver Schinagl wrote: >> I was pointed to this one: A25L032-F >> http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085 >> >> (There's also a Q version, which I don't think is what I'd want). > Correct. Q is a WSON package which does not fit at all. Make sure you > buy farnell nr. 1907085 and nothing else. A25L032-F is indeed the > accurate manufacturer's part number, if you order somewhere else. > > >> I haven't found a 64Mbit chip yet, so I hope I could use a linux >> kernel as payload using a 4MB one (the current 32Mbit) > Winbond W25Q64CV > > But Winbond's distributors AVNET and Digi-Key, > > http://www.winbond-usa.com/winbondcms/Application/member/Distributors.aspx?partno=W25Q64CV > > only have SO-8 in stock, and you wanted DIP. You could look for > adapters, but then you must do some soldering. > > http://search.digikey.com/scripts/DkSearch/dksus.dll?site=us&lang=en&v=256&WT.z_supplier_id=256&WT.z_page_type=SP&WT.z_page_sub_type=SS&WT.z_oss_type=View+All&chp=0 > > AVNET only have SO-8 stock in Asia. You'll have to pay import fees > and tax. Digi-Keys f-ing website barfs some idiotic error at me > whenever I try to use it nowadays. > > > You can buy DIP from bios-repair.co.uk, but they only have the older > revision W25Q64BVAIG. For once they don't charge more than AVNET&co > in single quantity. > > http://bios-repair.co.uk/Products/EEPROM/SPI-SerialFlash-EEPROM.html > > Click Winbond, then there's W25Q64BVAIG 64Mb PDIP top left in the > product listing. > > > //Peter > -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Wed Feb 22 11:35:19 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 22 Feb 2012 11:35:19 +0100 Subject: [coreboot] Patch merged into coreboot/master: 3d3abb2 Remove old AMD fam10 fixme comment References: Message-ID: the following patch was just integrated into master: commit 3d3abb2e9ce3a175c9182b6bc3ad17bc3487735b Author: Marc Jones Date: Tue Feb 21 17:53:13 2012 -0700 Remove old AMD fam10 fixme comment The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones Reviewed-By: Patrick Georgi at Wed Feb 22 11:35:17 2012, giving +2 See http://review.coreboot.org/672 for details. -gerrit From lewurm at gmail.com Wed Feb 22 12:51:38 2012 From: lewurm at gmail.com (Bernhard Urban) Date: Wed, 22 Feb 2012 12:51:38 +0100 Subject: [coreboot] Coreboot support for ASUS M5 A99X EVO ? In-Reply-To: References: Message-ID: hi, so finally, I spent some time on porting coreboot to the asus board "m5a99x evo". http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ I was equipped with three DIP chips and decided to use my target machine also for developing. I had also set up a quite complicated configuration for serial debugging, as I didn't own a second machine with a rs232 board. Although the first try (just flash the "m5a88-v" configuration) showed some output :-) ( http://tinyurl.com/89a33m5 ), the build cycle was a pain in the ass. (0) building coreboot (takes some seconds...) (1) flashing the chip (~30seconds, without verifying) (2) reboot (~20sec) (3) starting coreboot and analyse the output (between 1sec and some minutes ;-)) (4) switch chip with vendor bios on it (some seconds) (5) booting vendor bios and linux (35sec + 11sec. yes, the vendor firmware takes three times longer than linux + x11. BOAR ;-)) (6) switch chip again. So I was looking for alternatives. I remembered the ft2232 stuff by Uwe. I had it anyway on my "order it some day"-list, so it was the right time ;-) In the meanwhile, I refit my old machine with a new hdd and a reasoneable graphic card. Luckily, it has also a serial port :-) I was a bit afraid of building a programmer (the ft2232 thingy) as I'm not really the hardware guy. However, the first dump was successful. Writing was working too. I was impressed :-) Thanks to Uwe at this point! So the build cycle is more convenient now: (0) building coreboot (takes longer than on my new machine, but it's okay ;-)) (1) flash the chip with the ft2232 thingy (~30 seconds, without verifying) (2) put the chip onto the mainboard (3) start machine and watch serial output all in all, it take like one minute to test one build. nice! So, now I was able to do some serious coreboot hacking. I started from the "m5a88-v" port. What I did: - Changed the southbridge from "SB800" to "SB900" - Adapted some compile-breaks due to this change. - hardcoded some pci device instead of locating it @ early.c -> ohai ramstage :-) - again, some pci related change/hack (aborting the enumeration earlier). I didn't really understand what I did here, I just figured out it hangs here (could be related with the quirk below). After that -> OHAI SEABIOS! I was very happy ;) However, SeaBIOS itself hang somewhere. In the meanwhile, Kerry pushed RD890 patches, which seemed to be more appropriate for my board (i used RS780 code so far, hence the ugly hacks mentioned above I guess). So I used them, and it felt much cleaner immediately. The payload was still loading -> nice. After that, I investigated a bit what the problem is with SeaBIOS. At this moment, it hanged after printing "Relocating init from 0x000e8450 to 0xcffd57a0 (size 42812)" (see http://tinyurl.com/78evzex ). I looked into the SeaBIOS code and found out, that you can disable relocation. So I did. The result was a bit more confusing. http://tinyurl.com/7uh8xty The output get distorted (which seems not to be deterministically, http://tinyurl.com/6opakzl ) and something issues a soft reset (but not everytime...). Eventually I gave up at this point (had to do other stuff anyway). I guess it is something wrong with RAM initialization as relocation in higher memory regions doesn't work. Also, the graphic card isn't found on the pci bus as the RD890 code inlcudes a quirk which "disable all pcie bridges" aka `sr56x0_rd890_disable_pcie_bridge()'. According to `lspci' (with vendor bios), the graphic card is on bus 1, so this seem reasonably. @Kerry: is there some way to enable it again after "early"? my WIP branch is available here (please tell me if you pull from it, because atm I'm rebasing stuff on it and using `git push -f' to overwrite it...): http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=shortlog;h=refs/heads/WIP full logs (including config and rom images) are available here: http://wien.tomnetworks.com/gitweb/?p=cbimages.git;a=tree Some questions: - What does "CIMX" stands for? I grep'd my #coreboot logs for it. One guy asked that already, but he didn't get an answer :-/ - What's the best/easiest way to verify if RAM init was successful? - I think it would be nice to have an entry on the wiki page for this board. How I get an account? Stefan? :-) I appreciate any comment, I know resources are short :-( anyways, it was fun and exciting so far :-) thanks! regards, bernhard On Wed, Nov 23, 2011 at 10:29 PM, Bernhard Urban wrote: > Hi Chris, > > I reported flashrom compatibility here: > http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html > > Regarding coreboot support: I'll try to port coreboot to this board. I > already have two additional flashchips and at the moment I'm waiting > for a serial port connector. I don't know how long it'll talke to port > it, but don't except anything useful in less than three months, since > I'm new to coreboot (and lazy :-)) > > > Bernhard > > On Sat, Nov 19, 2011 at 6:33 PM, Christopher Huang-Leaver > wrote: >> Hello, >> I noticed earlier versions of this board are fully supported, but not this >> one. >> I have attached the output of, ?lspci, ?flashrom and dmidecode, if that is >> any use to anyone. >> The spec sheet is easy to find by typing ASUS M5 A99X into Google. ?The >> board does have a neat feature of being able to flash the BIOS from within >> the BIOS menu, which I have already used to update it. >> Many thanks >> Chris From shekairui at gmail.com Wed Feb 22 17:23:47 2012 From: shekairui at gmail.com (She Kairui) Date: Thu, 23 Feb 2012 00:23:47 +0800 Subject: [coreboot] New patch to review for coreboot: 617edf7 Revert "Fix multipleVGA cards resource conflict on Windows" In-Reply-To: References: Message-ID: Hi Marc, > From: Marc Jones > Date: Wed, 22 Feb 2012 01:46:33 +0100 > Subject: [coreboot] New patch to review for coreboot: 617edf7 Revert > "Fix multipleVGA cards resource conflict on Windows" > To: coreboot at coreboot.org > > Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to > gerrit, which you can find at http://review.coreboot.org/671 > > -gerrit > > commit 617edf7e746df87616e4ada8a40decabe1231341 > Author: Marc Jones > Date: Tue Feb 21 17:44:35 2012 +0100 > > Revert "Fix multipleVGA cards resource conflict on Windows" > > This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e > > This commit has been found to cause problems with vbios and option rom > init > in seabios. It has been found by several people and requires more > analysis > before being recommitted. > http://review.coreboot.org/#change,489 Patch Set 4 is another way to resolve the multiVGA problem in windows. does your platform booting with this patch set? Thanks Kerry > Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230 > Signed-off-by: Marc Jones > --- > src/devices/device.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/devices/device.c b/src/devices/device.c > index 8ad9787..a2619bf 100644 > --- a/src/devices/device.c > +++ b/src/devices/device.c > @@ -932,6 +932,10 @@ void dev_configure(void) > struct device *root; > struct device *child; > > +#if CONFIG_VGA_BRIDGE_SETUP == 1 > + set_vga_bridge_bits(); > +#endif > + > printk(BIOS_INFO, "Allocating resources...\n"); > > root = &dev_root; > @@ -1024,10 +1028,6 @@ void dev_configure(void) > printk(BIOS_INFO, "Done setting resources.\n"); > print_resource_tree(root, BIOS_SPEW, "After assigning values."); > > -#if CONFIG_VGA_BRIDGE_SETUP == 1 > - set_vga_bridge_bits(); > -#endif > - > printk(BIOS_INFO, "Done allocating resources.\n"); > } > > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > From gerrit at coreboot.org Wed Feb 22 21:07:56 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 22 Feb 2012 21:07:56 +0100 Subject: [coreboot] New patch to review for coreboot: 1041a87 Update xcompile to search for x86_64 toolchain. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673 -gerrit commit 1041a87f618b4772f6ec9796c3224258888d3645 Author: Marc Jones Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones --- util/xcompile/xcompile | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4926394..f8a69bb 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -36,14 +36,19 @@ done GCCPREFIX=invalid XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} -echo '#XGCCPATH='${XGCCPATH} +echo '# XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE -# This should be a loop over all supported architectures -TARCH=i386 +# This loops over all supported architectures in TARCH +TARCH=('i386' 'x86_64') TWIDTH=32 -for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do +for search_for in "${TARCH[@]}"; do + TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-) +done +echo '# TARCH_SEARCH='${TARCH_SEARCH[@]} + +for gccprefixes in "${TARCH_SEARCH[@]}" ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi From gerrit at coreboot.org Wed Feb 22 21:15:53 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Wed, 22 Feb 2012 21:15:53 +0100 Subject: [coreboot] Patch set updated for coreboot: 7ba552e ACPI: More ../../.. removal References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/649 -gerrit commit 7ba552ebc7c8b7804741f918e0e80f836454e097 Author: Patrick Georgi Date: Thu Feb 16 19:16:14 2012 +0100 ACPI: More ../../.. removal CPP is ran with src/ as part of its search path, so using and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi --- src/mainboard/advansus/a785e-i/dsdt.asl | 4 ++-- src/mainboard/amd/bimini_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/dbm690t/dsdt.asl | 4 ++-- src/mainboard/amd/inagua/dsdt.asl | 4 ++-- src/mainboard/amd/mahogany/dsdt.asl | 4 ++-- src/mainboard/amd/mahogany_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/persimmon/dsdt.asl | 4 ++-- src/mainboard/amd/pistachio/dsdt.asl | 4 ++-- src/mainboard/amd/south_station/dsdt.asl | 4 ++-- src/mainboard/amd/tilapia_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/torpedo/dsdt.asl | 4 ++-- src/mainboard/amd/union_station/dsdt.asl | 4 ++-- src/mainboard/asrock/939a785gmh/dsdt.asl | 4 ++-- src/mainboard/asrock/e350m1/dsdt.asl | 4 ++-- src/mainboard/asus/m4a78-em/dsdt.asl | 4 ++-- src/mainboard/asus/m4a785-m/dsdt.asl | 4 ++-- src/mainboard/asus/m4a785t-m/dsdt.asl | 4 ++-- src/mainboard/asus/m5a88-v/dsdt.asl | 4 ++-- src/mainboard/avalue/eax-785e/dsdt.asl | 4 ++-- src/mainboard/getac/p470/dsdt.asl | 8 ++++---- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 4 ++-- src/mainboard/gigabyte/ma78gm/dsdt.asl | 4 ++-- src/mainboard/ibase/mb899/dsdt.asl | 8 ++++---- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 4 ++-- src/mainboard/intel/d945gclf/dsdt.asl | 8 ++++---- src/mainboard/iwave/iWRainbowG6/dsdt.asl | 8 ++++---- src/mainboard/jetway/pa78vm5/dsdt.asl | 4 ++-- src/mainboard/kontron/986lcd-m/dsdt.asl | 8 ++++---- src/mainboard/kontron/kt690/dsdt.asl | 4 ++-- src/mainboard/lenovo/t60/dsdt.asl | 8 ++++---- src/mainboard/lenovo/x60/dsdt.asl | 8 ++++---- src/mainboard/msi/ms9652_fam10/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/dsdt.asl | 8 ++++---- src/mainboard/supermicro/h8qgi/dsdt.asl | 4 ++-- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 4 ++-- src/mainboard/technexion/tim5690/dsdt.asl | 4 ++-- src/mainboard/technexion/tim8690/dsdt.asl | 4 ++-- 37 files changed, 89 insertions(+), 89 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 78d3220..52ca3b9 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 3ff6dab..e54723c 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 1b24e18..2b1aab8 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 4a61328..361adbb 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 33c4620..4920e2f 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1120,7 +1120,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 8bba547..b7e2a4a 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index c7ceb02..b480c33 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index bd5f73e..045db08 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1122,7 +1122,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index c4b69bd..7f03a43 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 93724e3..666cebe 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index bc812e4..a8a731d 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -798,7 +798,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 04952d3..5c8b661 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl index 70fca4d..da4d06a 100644 --- a/src/mainboard/asrock/939a785gmh/dsdt.asl +++ b/src/mainboard/asrock/939a785gmh/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ #include "northbridge/amd/amdk8/util.asl" Name(HPBA, 0xFED00000) /* Base address of HPET table */ @@ -460,7 +460,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 8dc40d0..97533c1 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index 7c28398..0d08d29 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index 34ddd3a..7ea5672 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index fe2bfa5..9e6ce88 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index b9a699b..a248766 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 1287f95..b835128 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 9728ea2..baca3da 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -35,7 +35,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -49,11 +49,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index fdd3a3e..a29bb2a 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 03d8fcd..c850b9e 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index f06b225..601c329 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 7ae6bd5..66f8254 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 49b6033..62fa0af 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -44,11 +44,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl index f19ffb9..5bf59a7 100644 --- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl +++ b/src/mainboard/iwave/iWRainbowG6/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/sch/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/sch/acpi/sch.asl" - #include "../../../southbridge/intel/sch/acpi/sch.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/sch/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 38de9b9..8f75019 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 2235f62..a32015f 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 20ecb5b..a740a8b 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 905c94a..52a5edb 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -43,13 +43,13 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 905c94a..52a5edb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -43,13 +43,13 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index fe34112..c889841 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - #include "../../../../src/northbridge/amd/amdk8/util.asl" + #include /* For now only define 2 power states: * - S0 which is fully on diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index e3a62a3..58e78ec 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include // General Purpose Events #include "acpi/gpe.asl" @@ -46,11 +46,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include + #include } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include } diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 3f10012..137a90d 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1132,7 +1132,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index e8139c4..dd3c897 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1180,7 +1180,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 409d941..9279b5f 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index 5fd3e3e..b13d2ec 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ From gerrit at coreboot.org Wed Feb 22 21:27:41 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Wed, 22 Feb 2012 21:27:41 +0100 Subject: [coreboot] New patch to review for coreboot: 448996a Rename vendor identifiers in Kconfig References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/674 -gerrit commit 448996ad975da9f3d620a2e4feb1373d1c67dfd9 Author: Patrick Georgi Date: Tue Jan 10 18:45:34 2012 +0100 Rename vendor identifiers in Kconfig Board identifiers use them without underscore, too. Unify that. Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d Signed-off-by: Patrick Georgi --- src/mainboard/Kconfig | 4 ++-- src/mainboard/artecgroup/Kconfig | 4 ++-- src/mainboard/digitallogic/Kconfig | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a73f445 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -16,7 +16,7 @@ config VENDOR_AMD bool "AMD" config VENDOR_ARIMA bool "Arima" -config VENDOR_ARTEC_GROUP +config VENDOR_ARTECGROUP bool "Artec Group" config VENDOR_ASI bool "ASI" @@ -42,7 +42,7 @@ config VENDOR_COMPAQ bool "Compaq" config VENDOR_DELL bool "Dell" -config VENDOR_DIGITAL_LOGIC +config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_EAGLELION bool "EagleLion" diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig index 5e63f09..b6923ae 100644 --- a/src/mainboard/artecgroup/Kconfig +++ b/src/mainboard/artecgroup/Kconfig @@ -1,4 +1,4 @@ -if VENDOR_ARTEC_GROUP +if VENDOR_ARTECGROUP choice prompt "Mainboard model" @@ -14,4 +14,4 @@ config MAINBOARD_VENDOR string default "Artec Group" -endif # VENDOR_ARTEC_GROUP +endif # VENDOR_ARTECGROUP diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig index a98aa1d..9f490b0 100644 --- a/src/mainboard/digitallogic/Kconfig +++ b/src/mainboard/digitallogic/Kconfig @@ -1,4 +1,4 @@ -if VENDOR_DIGITAL_LOGIC +if VENDOR_DIGITALLOGIC choice prompt "Mainboard model" @@ -20,4 +20,4 @@ config MAINBOARD_VENDOR string default "DIGITAL-LOGIC" -endif # VENDOR_DIGITAL_LOGIC +endif # VENDOR_DIGITALLOGIC From gerrit at coreboot.org Wed Feb 22 21:27:42 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Wed, 22 Feb 2012 21:27:42 +0100 Subject: [coreboot] New patch to review for coreboot: 20a9979 Drop support for BROKEN marker References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/675 -gerrit commit 20a9979ad93bed52c457dc263d0fe30872c9406c Author: Patrick Georgi Date: Tue Jan 10 19:25:23 2012 +0100 Drop support for BROKEN marker We used to support marking boards broken. We don't need that anymore. Change-Id: I9d21fdf22c9a8e0e69488fc7896f2a81bf629201 Signed-off-by: Patrick Georgi --- util/abuild/abuild | 23 +---------------------- 1 files changed, 1 insertions(+), 22 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 78a4718..74d2908 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -326,14 +326,6 @@ function compile_target fi } -function build_broken -{ - CURR=`pwd` - status="yes" - [ -r "$ROOT/src/mainboard/${VENDOR}/${MAINBOARD}/BROKEN" ] && status="no" - [ "$buildbroken" == "true" -o "$status" == "yes" ] -} - function build_target { VENDOR=$1 @@ -430,17 +422,6 @@ function build_target CC="$CC -fno-stack-protector" fi - build_broken $VENDOR $MAINBOARD || \ - { - printf " ( broken mainboard/$VENDOR/$MAINBOARD skipped )\n\n" - xml " knownbroken" - xml "" - xml "" - junit " " - junit "Board is marked as broken" - return 0 - } - stime=`perl -e 'print time();' 2>/dev/null || date +%s` create_buildenv $VENDOR $MAINBOARD $CONFIG if [ $? -eq 0 -a $configureonly -eq 0 ]; then @@ -534,7 +515,6 @@ function myhelp printf "Options:\n" printf " [-v|--verbose] print more messages\n" printf " [-a|--all] build previously succeeded ports as well\n" - printf " [-b|--broken] attempt to build ports that are known broken\n" printf " [-r|--remove] remove output dir after build\n" printf " [-t|--target ] attempt to build target vendor/board only\n" printf " [-p|--payloads ] use payloads in to build images\n" @@ -587,7 +567,7 @@ test "$ROOT" = "" && ROOT=$( cd ../..; pwd ) getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,junit,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache -o Vvhat:bp:Tc:sJxCl:rP:uy -- "$@"` + args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache -o Vvhat:p:Tc:sJxCl:rP:uy -- "$@"` eval set -- $args else # Detected non-GNU getopt @@ -606,7 +586,6 @@ while true ; do -J|--junit) shift; mode=junit; rm -f $XMLFILE ;; -t|--target) shift; target="$1"; shift;; -a|--all) shift; buildall=true;; - -b|--broken) shift; buildbroken=true;; -r|--remove) shift; remove=true;; -v|--verbose) shift; verbose=true; silent='V=1';; -V|--version) shift; myversion; exit 0;; From gerrit at coreboot.org Wed Feb 22 21:28:37 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Wed, 22 Feb 2012 21:28:37 +0100 Subject: [coreboot] New patch to review for coreboot: 5e10197 Unify Local APIC address definitions References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/676 -gerrit commit 5e10197722fa0177fe94d770fed10341f8c41f1d Author: Patrick Georgi Date: Thu Feb 16 18:43:25 2012 +0100 Unify Local APIC address definitions We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi --- src/arch/x86/boot/acpi.c | 3 +-- src/arch/x86/include/arch/smp/mpspec.h | 5 ++--- src/include/cpu/x86/lapic_def.h | 3 ++- src/mainboard/advansus/a785e-i/mptable.c | 2 +- src/mainboard/amd/bimini_fam10/mptable.c | 2 +- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/mptable.c | 2 +- .../amd/serengeti_cheetah/acpi/amd8111_isa.asl | 4 ++-- src/mainboard/amd/serengeti_cheetah/mptable.c | 2 +- .../serengeti_cheetah_fam10/acpi/amd8111_isa.asl | 4 ++-- .../amd/serengeti_cheetah_fam10/mptable.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/arima/hdama/mptable.c | 2 +- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/a8v-e_deluxe/mptable.c | 2 +- src/mainboard/asus/a8v-e_se/mptable.c | 2 +- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2v/mptable.c | 2 +- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/mptable.c | 2 +- src/mainboard/asus/p2b-d/mptable.c | 2 +- src/mainboard/asus/p2b-ds/mptable.c | 2 +- src/mainboard/avalue/eax-785e/mptable.c | 2 +- src/mainboard/broadcom/blast/mptable.c | 2 +- src/mainboard/dell/s1850/mptable.c | 2 +- src/mainboard/emulation/qemu-x86/northbridge.c | 3 ++- src/mainboard/getac/p470/mptable.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/hp/dl145_g1/mptable.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +- src/mainboard/ibase/mb899/mptable.c | 2 +- src/mainboard/ibm/e325/mptable.c | 2 +- src/mainboard/ibm/e326/mptable.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/intel/d945gclf/mptable.c | 2 +- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/jarrell/mptable.c | 2 +- src/mainboard/intel/mtarvon/mptable.c | 2 +- src/mainboard/intel/truxton/mptable.c | 2 +- src/mainboard/intel/xe7501devkit/mptable.c | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl | 4 ++-- src/mainboard/iwill/dk8_htx/mptable.c | 2 +- src/mainboard/iwill/dk8s2/mptable.c | 2 +- src/mainboard/iwill/dk8x/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/986lcd-m/mptable.c | 2 +- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/lenovo/t60/mptable.c | 2 +- src/mainboard/lenovo/x60/mptable.c | 2 +- src/mainboard/msi/ms7135/mptable.c | 2 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms9185/mptable.c | 2 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/mptable.c | 2 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 2 +- src/mainboard/roda/rk886ex/mptable.c | 2 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 4 ++-- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/mptable.c | 2 +- src/mainboard/supermicro/x6dhe_g/mptable.c | 2 +- src/mainboard/supermicro/x6dhe_g2/mptable.c | 2 +- src/mainboard/supermicro/x6dhr_ig/mptable.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 2 +- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/tyan/s2735/mptable.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 2 +- src/mainboard/tyan/s2875/mptable.c | 2 +- src/mainboard/tyan/s2880/mptable.c | 2 +- src/mainboard/tyan/s2881/mptable.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 2 +- src/mainboard/tyan/s2885/mptable.c | 2 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 2 +- src/mainboard/tyan/s4882/mptable.c | 2 +- src/mainboard/via/epia-n/mainboard.c | 3 ++- src/mainboard/via/epia-n/mptable.c | 2 +- src/mainboard/via/pc2500e/mptable.c | 2 +- src/mainboard/via/vt8454c/mptable.c | 2 +- 107 files changed, 115 insertions(+), 114 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..168933a 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,7 @@ #include #include #include +#include u8 acpi_checksum(u8 *table, u32 length) { @@ -188,8 +189,6 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, void acpi_create_madt(acpi_madt_t *madt) { -#define LOCAL_APIC_ADDR 0xfee00000ULL - acpi_header_t *header = &(madt->header); unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t); diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 2eb1813..e5e6195 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -2,6 +2,8 @@ #define __ASM_MPSPEC_H #include +#include + /* * Structure definitions for SMP machines following the * Intel Multiprocessing Specification 1.1 and 1.4. @@ -229,9 +231,6 @@ struct mp_exten_compatibility_address_space { */ } __attribute__((packed)); -/* Default local apic addr */ -#define LAPIC_ADDR 0xFEE00000 - void mptable_init(struct mp_config_table *mc, u32 lapic_addr); void *smp_next_mpc_entry(struct mp_config_table *mc); diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index 6035273..f96b53b 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -6,7 +6,8 @@ #define LAPIC_BASE_MSR_ENABLE (1 << 11) #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 -#define LAPIC_DEFAULT_BASE 0xfee00000 +#define LOCAL_APIC_ADDR 0xfee00000 +#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR #define LAPIC_ID 0x020 #define LAPIC_LVR 0x030 diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 6504049..8643320 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c index 2ab3f24..ae81411 100644 --- a/src/mainboard/amd/bimini_fam10/mptable.c +++ b/src/mainboard/amd/bimini_fam10/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 901591a..cf98ae3 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index b339348..b5a507f 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index f79a579..dabd2ed 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index b1a658b..c56952e 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 18a7707..61ddef1 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 901591a..cf98ae3 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl index 0f7efc9..d6e47fb 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl @@ -125,9 +125,9 @@ { Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index ebd4cbc..4214408 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl index f00069f..7a8317b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl @@ -141,9 +141,9 @@ { Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index d527f9c..e90b348 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 5242f69..99004b3 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 97db2b9..936a417 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); /*Inagua used dure core cpu with one die */ diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 5242f69..99004b3 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 466ba88..f67327e 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 95b1271..c0ca550 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index de9d7f4..7e8c947 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "ASROCK ", 8); smp_write_processors(mc); diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index 349ae74..9defdb5 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c index 999dd6c..eb7790f 100644 --- a/src/mainboard/asus/a8v-e_deluxe/mptable.c +++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c index 999dd6c..eb7790f 100644 --- a/src/mainboard/asus/a8v-e_se/mptable.c +++ b/src/mainboard/asus/a8v-e_se/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 673dfbe..48eee71 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 29b9d07..680dfa7 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c index 5dc340a..e6e600a 100644 --- a/src/mainboard/asus/m2v/mptable.c +++ b/src/mainboard/asus/m2v/mptable.c @@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v) mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index 516b915..ac8ed5e 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c index 43f3a85..4eed581 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b-d/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c index 153c62c..5333418 100644 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b-ds/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 021f635..6f541a0 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index b747d2e..5a1bf28 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c index a71dab0..0c7562c 100644 --- a/src/mainboard/dell/s1850/mptable.c +++ b/src/mainboard/dell/s1850/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 3f22437..b961e8b 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -80,7 +81,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) /* Reserve space for the LAPIC. There's one in every processor, but * the space only needs to be reserved once, so we do it here. */ res = new_resource(dev, 3); - res->base = 0xfee00000UL; + res->base = LOCAL_APIC_ADDR; res->size = 0x10000UL; res->limit = 0xffffffffUL; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 5954c97..9b59bb4 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index b52cda9..914b25a 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 5aa7e61..f493514 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index e33f681..35dedde 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 466b7fc..609432a 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index c246721..00234a3 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 0ff1896..1baf728 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 6431f32..7d1b8f3 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index e81bf8f..b963a0c 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 66423e5..a26fbde 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index ab537cb..b0360bf 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 8571864..809feec 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index b665703..6662329 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c index 0c025f0..364d077 100644 --- a/src/mainboard/intel/mtarvon/mptable.c +++ b/src/mainboard/intel/mtarvon/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index 506a1d0..0cc8f6b 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index 99fd5af..cc7eda5 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -122,7 +122,7 @@ static void *smp_write_config_table(void* v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index bf94b8c..953f16a 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -29,7 +29,7 @@ void *smp_write_config_table(void *v) int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl index 0f7efc9..d6e47fb 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl @@ -125,9 +125,9 @@ { Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index fd53bd7..3977673 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c index d78ce20..f22fd9d 100644 --- a/src/mainboard/iwill/dk8s2/mptable.c +++ b/src/mainboard/iwill/dk8s2/mptable.c @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c index d78ce20..f22fd9d 100644 --- a/src/mainboard/iwill/dk8x/mptable.c +++ b/src/mainboard/iwill/dk8x/mptable.c @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 11b4357..b8caa23 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index ab63b45..03f7370 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 21a0d05..4ffba6f 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index a74aca8..312e30d 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 0ce10ed..f21e76f 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c index 4262af1..7d7ba53 100644 --- a/src/mainboard/msi/ms7135/mptable.c +++ b/src/mainboard/msi/ms7135/mptable.c @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index bef81ef..41f5bf7 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 0f97dca..fe65d7d 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index baba6b5..0559844 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 5e45380..35d1172 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c index 4017fce..8ee6e15 100644 --- a/src/mainboard/newisys/khepri/mptable.c +++ b/src/mainboard/newisys/khepri/mptable.c @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index 5d13701..b7e1a88 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index 5954c97..9b59bb4 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 8ad0f82..6ad5597 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -418,8 +418,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02) If (PCIF) { - Store (0xFEC00000, MB01) - Store (0xFEE00000, MB02) + Store (IO_APIC_ADDR, MB01) + Store (LOCAL_APIC_ADDR, MB02) Store (0x1000, ML01) Store (0x1000, ML02) } diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index ba2c1e4..dc98382 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index c00c4b8..1ba1dcf 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index cdbe7d6..93fea87 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 734fac9..f54e18f 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index f2ee7a8..6ed5840 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 92771bd..61a7bd4 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v) u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 2e7c4af..e6d4280 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index b2c1c92..0c75d1a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index acd719d..6ba5309 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -13,7 +13,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index f5f4100..4504d34 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index e39a700..087bb9e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index 143138d..5d0a08d 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index a374f5c..b6c94d3 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 21a0d05..4ffba6f 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 21a0d05..4ffba6f 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9612a4c..9073728 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -12,7 +12,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 5144cec..08027f4 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); { diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 67de027..c3765f2 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index e0058fa..2d34c8b 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 80b35bc..7df5e87 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index b028abb..47c39a7 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); { diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index fc5109f..26081c7 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index 12d6e78..cb49434 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 7af319a..882ac69 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index a383cb2..20fa92c 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 49720dc..9fe7ab7 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index 393362b..8b5f365 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index 6646718..9111a63 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index c1da3e5..bca26a0 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c index 9227f0a..6e11a00 100644 --- a/src/mainboard/via/epia-n/mainboard.c +++ b/src/mainboard/via/epia-n/mainboard.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "chip.h" int add_mainboard_resources(struct lb_memory *mem) @@ -33,7 +34,7 @@ int add_mainboard_resources(struct lb_memory *mem) lb_add_memory_range(mem, LB_MEM_RESERVED, IO_APIC_ADDR, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, - 0xFEE00000ULL, 0x1000); + LOCAL_APIC_ADDR, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, 0xFFFF0000ULL, 0x10000); #endif diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c index c7c554a..de25d0e 100644 --- a/src/mainboard/via/epia-n/mptable.c +++ b/src/mainboard/via/epia-n/mptable.c @@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c index 939f21d..fa69bbe 100644 --- a/src/mainboard/via/pc2500e/mptable.c +++ b/src/mainboard/via/pc2500e/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c index 575237f..fc9cb99 100644 --- a/src/mainboard/via/vt8454c/mptable.c +++ b/src/mainboard/via/vt8454c/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); From gerrit at coreboot.org Wed Feb 22 21:28:39 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Wed, 22 Feb 2012 21:28:39 +0100 Subject: [coreboot] New patch to review for coreboot: 9ac8fd2 Unify IO APIC address specification References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/677 -gerrit commit 9ac8fd289ca9b3118a3880a6f7d8e52f997a98ba Author: Patrick Georgi Date: Thu Feb 16 18:54:37 2012 +0100 Unify IO APIC address specification Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi --- src/mainboard/amd/torpedo/platform_cfg.h | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/northbridge/intel/i945/acpi/hostbridge.asl | 2 +- src/northbridge/intel/sch/acpi/hostbridge.asl | 2 +- src/southbridge/amd/cimx/sb700/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb800/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb900/lpc.c | 4 ++-- src/southbridge/amd/sb800/lpc.c | 4 ++-- src/southbridge/amd/sb800/sm.c | 8 +++----- src/southbridge/intel/sch/lpc.c | 4 ++-- 10 files changed, 17 insertions(+), 19 deletions(-) diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index d97d034..cf31c6a 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -137,7 +137,7 @@ * @section WatchDogTimerBase */ // #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 +// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR // #endif /** diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 953f16a..87de022 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -34,7 +34,7 @@ void *smp_write_config_table(void *v) smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index a76d8e2..b5f86ae 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -211,7 +211,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_BASE,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl index 7e92a0e..17a95a4 100644 --- a/src/northbridge/intel/sch/acpi/hostbridge.asl +++ b/src/northbridge/intel/sch/acpi/hostbridge.asl @@ -211,7 +211,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_ADDR,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index e43193a..5bfd68a 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -61,8 +61,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..efbc585 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -45,8 +45,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 48bfe36..2d60f97 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -45,8 +45,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 6b72a62..4e2031f 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -91,8 +91,8 @@ static void sb800_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - //res = new_resource(dev, 3); /* IOAPIC */ - //res->base = 0xfec00000; + //res = new_resource(dev, 3); + //res->base = IO_APIC_ADDR; //res->size = 0x00001000; //res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 9347c42..50a8f0b 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -84,16 +84,14 @@ static void sm_init(device_t dev) { u8 byte; - u32 ioapic_base; printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = 0xFEC00000;//pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. * We need to check out why and change back. */ - clear_ioapic(ioapic_base); - //setup_ioapic(ioapic_base, 0); + clear_ioapic(IO_APIC_ADDR); + //setup_ioapic(IO_APIC_ADDR, 0); /* enable serial irq */ byte = pm_ioread(0x54); @@ -277,7 +275,7 @@ static void sb800_sm_read_resources(device_t dev) /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFEFFFFFUL; /* res->base + res->size -1; */ res->align = 8; diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index ab180bb..7c203bf 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -164,8 +164,8 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } From gerrit at coreboot.org Wed Feb 22 21:12:15 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Wed, 22 Feb 2012 21:12:15 +0100 Subject: [coreboot] Patch set updated for coreboot: 5cb35be amd/sb600: Move HAVE_HARD_RESET to southbridge References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/660 -gerrit commit 5cb35be4906ab6df74545feeca67b10a444ab8bd Author: Patrick Georgi Date: Thu Feb 16 19:45:56 2012 +0100 amd/sb600: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0 Signed-off-by: Patrick Georgi --- src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim8690/Kconfig | 1 - src/southbridge/amd/sb600/Kconfig | 1 + 7 files changed, 1 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 3d3a04c..d1bf72f 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 487a599..d140878 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 91d6b67..6a1909f 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES select GFXUMA - select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index 1bc7406..b2cae03 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 21cfa7b..404ddfe 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 5af6ace..293590c 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 07028a0..8ec3967 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB600 config BOOTBLOCK_SOUTHBRIDGE_INIT From gerrit at coreboot.org Wed Feb 22 22:09:02 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 22 Feb 2012 22:09:02 +0100 Subject: [coreboot] Patch merged into coreboot/master: 5cb35be amd/sb600: Move HAVE_HARD_RESET to southbridge References: Message-ID: the following patch was just integrated into master: commit 5cb35be4906ab6df74545feeca67b10a444ab8bd Author: Patrick Georgi Date: Thu Feb 16 19:45:56 2012 +0100 amd/sb600: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0 Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Wed Feb 22 22:08:58 2012, giving +2 See http://review.coreboot.org/660 for details. -gerrit From gerrit at coreboot.org Wed Feb 22 22:16:23 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 22 Feb 2012 22:16:23 +0100 Subject: [coreboot] Patch merged into coreboot/master: 7ba552e ACPI: More ../../.. removal References: Message-ID: the following patch was just integrated into master: commit 7ba552ebc7c8b7804741f918e0e80f836454e097 Author: Patrick Georgi Date: Thu Feb 16 19:16:14 2012 +0100 ACPI: More ../../.. removal CPP is ran with src/ as part of its search path, so using and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi Reviewed-By: Patrick Georgi at Wed Feb 22 22:13:33 2012, giving +2 See http://review.coreboot.org/649 for details. -gerrit From gerrit at coreboot.org Thu Feb 23 01:29:38 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Thu, 23 Feb 2012 01:29:38 +0100 Subject: [coreboot] Patch merged into coreboot/master: 617edf7 Revert "Fix multipleVGA cards resource conflict on Windows" References: Message-ID: the following patch was just integrated into master: commit 617edf7e746df87616e4ada8a40decabe1231341 Author: Marc Jones Date: Tue Feb 21 17:44:35 2012 +0100 Revert "Fix multipleVGA cards resource conflict on Windows" This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e This commit has been found to cause problems with vbios and option rom init in seabios. It has been found by several people and requires more analysis before being recommitted. Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230 Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Wed Feb 22 02:03:44 2012, giving +1 Reviewed-By: Marc Jones at Thu Feb 23 01:29:35 2012, giving +2 See http://review.coreboot.org/671 for details. -gerrit From gerrit at coreboot.org Thu Feb 23 01:40:18 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Thu, 23 Feb 2012 01:40:18 +0100 Subject: [coreboot] Patch set updated for coreboot: a22698c Update xcompile to search for x86_64 toolchain. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673 -gerrit commit a22698cc7ec072ce8664ccb9d79ff9f99ddc2634 Author: Marc Jones Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones --- util/xcompile/xcompile | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4926394..cbdc076 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -36,14 +36,19 @@ done GCCPREFIX=invalid XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} -echo '#XGCCPATH='${XGCCPATH} +echo '# XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE -# This should be a loop over all supported architectures -TARCH=i386 +# This loops over all supported architectures in TARCH +TARCH=('i386' 'x86_64') TWIDTH=32 -for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do +for search_for in "${TARCH[@]}"; do + TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-) +done +echo '# TARCH_SEARCH='${TARCH_SEARCH[@]} + +for gccprefixes in "${TARCH_SEARCH[@]}" ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi @@ -63,8 +68,8 @@ for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS=--32 - CFLAGS="-m32 " - LDFLAGS="-b elf32-i386" + CFLAGS="-m32 -Wl,-b -Wl,elf32-i386 -Wl,-melf_i386 " + LDFLAGS="-b elf32-i386 -melf_i386" break fi fi From oliver at schinagl.nl Thu Feb 23 10:04:34 2012 From: oliver at schinagl.nl (Oliver Schinagl) Date: Thu, 23 Feb 2012 10:04:34 +0100 Subject: [coreboot] Dual SPI Flash Message-ID: <4F460122.9000304@schinagl.nl> Hi list, I noticed an intersting hack on the coreboot wiki: http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash It lists a neat trick to double stack two spi flash modules to make testing/developping/flashing coreboot easier. However there's no schematic or other information available on how to actually build this setup. Could the author possibly supply this extra information? Since not even the resitor values or switch connection is documented. Thanks, Oliver From gerrit at coreboot.org Thu Feb 23 12:18:08 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 23 Feb 2012 12:18:08 +0100 Subject: [coreboot] Patch set updated for coreboot: 3dea10d Auto-generate bootblock initialisation References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473 -gerrit commit 3dea10d666a76c3f81dca0ba5381709d0f277044 Author: Ky?sti M?lkki Date: Sun Dec 4 21:35:38 2011 +0200 Auto-generate bootblock initialisation The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init The following no-operation bootblock.c files were removed: - northbridge/amd/agesa/family10/bootblock.c - northbridge/amd/agesa/family12/bootblock.c - northbridge/amd/agesa/family14/bootblock.c A new init function called from bootblock is declared as: - unsigned long init_mainboard(int bsp_cpu) For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock calls init_mainboard(false). Usually AP CPU has nothing to do here. By default, build toolchain creates and includes an init_mainboard() function in file build/mainboard/x/x/bootblock_autogen.h that executes init functions from any bootblock.c files for all chips listed in mainboard/devtree.cb. Alternatively a mainboard/x/x/bootblock.c file is added in the bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set. One should copy the auto-generated init_mainboard() to this file, and optionally read various bootstrap signals or status bits from super-io and southbridge component to gain some control over the selection of romstage to boot via the return value. Samples of such (yet not implemented) controls for boot behaviour: - Reset CMOS to defaults on user request (jumper). - Use fallback prefix after power-button 4s override. - Refuse boot after intruder detection. - On remote wakeup, request network boot. Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Kconfig | 7 +---- src/arch/x86/Makefile.inc | 9 +++++- src/arch/x86/include/bootblock_common.h | 17 +------------- src/arch/x86/init/bootblock_normal.c | 8 +++--- src/arch/x86/init/bootblock_simple.c | 10 ++++---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +--- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 10 +++++++- src/northbridge/amd/agesa/family10/Kconfig | 3 -- src/northbridge/amd/agesa/family10/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family12/Kconfig | 4 --- src/northbridge/amd/agesa/family12/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family14/Kconfig | 4 --- src/northbridge/amd/agesa/family14/bootblock.c | 29 ------------------------ src/northbridge/amd/amdfam10/Kconfig | 4 --- src/northbridge/amd/amdfam10/bootblock.c | 2 +- src/northbridge/amd/amdk8/Kconfig | 4 --- src/northbridge/amd/amdk8/bootblock.c | 2 +- src/southbridge/amd/amd8111/Kconfig | 4 --- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 3 -- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 3 -- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/Kconfig | 3 -- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/Kconfig | 5 ---- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/Kconfig | 5 ---- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/Kconfig | 4 --- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/i82371eb/Kconfig | 5 ---- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/Kconfig | 5 ---- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/nvidia/ck804/Kconfig | 6 ++-- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/Kconfig | 6 ++-- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/Kconfig | 7 +++-- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/Kconfig | 4 --- src/southbridge/via/vt8237r/bootblock.c | 2 +- 43 files changed, 54 insertions(+), 208 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..07ad95f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -67,8 +67,8 @@ config PC80_SYSTEM bool default y -config BOOTBLOCK_NORTHBRIDGE_INIT - string +config HAS_MAINBOARD_BOOTBLOCK + def_bool n config HAVE_CMOS_DEFAULT def_bool n @@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE string depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config BIG_ENDIAN bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 624b510..e1a9f6d 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -324,11 +324,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig + @printf " SCONFIG $(subst $(src)/,,$(<)) (bootblock)\n" + mkdir -p $(@D) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F) $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index bd19682..69ab22c 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,22 +1,7 @@ #include -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#else -static void bootblock_cpu_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - #include +#include "bootblock_autogen.h" #if CONFIG_USE_OPTION_TABLE #include diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index f8ae13b..48b4131 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -4,13 +4,13 @@ static void main(unsigned long bist) { unsigned long entry; + int bsp_cpu = boot_cpu(); int boot_mode; - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); + if (bsp_cpu) { #if CONFIG_USE_OPTION_TABLE sanitize_cmos(); #endif diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 41f73b4..f4e4bbf 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -2,15 +2,15 @@ static void main(unsigned long bist) { - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + int bsp_cpu = boot_cpu(); + + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); #if CONFIG_USE_OPTION_TABLE + if (bsp_cpu) sanitize_cmos(); #endif - } const char* target1 = "fallback/romstage"; unsigned long entry; diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index cdff24f..547cc21 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAS_MAINBOARD_BOOTBLOCK select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO @@ -90,10 +91,6 @@ config HEAP_SIZE hex default 0xc0000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "mainboard/hp/dl165_g6_fam10/bootblock.c" - config MMCONF_SUPPORT_DEFAULT bool default y diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 2c56c4c..e7c0680 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) +/* FIXME: This appears to be a super-io initialisation, + * placed in the mainboard directory. + */ void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); @@ -43,6 +46,11 @@ void shc4307_init(void) shc4307_exit_ext_func_mode(CMOS_DEV); } -static void bootblock_southbridge_init(void) { +static unsigned long init_mainboard(int bsp_cpu) +{ + if (!bsp_cpu) return 0; + init_northbridge_amd_amdfam10(); + //init_southbridge_broadcom_bcm5785(); shc4307_init(); + return 0; } diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index 62a6cd4..0bb16d9 100755 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family10/bootblock.c" endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family10/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index fc3c436..8ab5de8 100755 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -73,7 +73,3 @@ if DIMM_DDR3 endif endif -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family12/bootblock.c" - depends on NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family12/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 44f93c1..e462153 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER int default 16 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family14/bootblock.c" - endif diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family14/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index a14339e..633d378 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a..328e9ad 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -3,7 +3,7 @@ #include #include "northbridge/amd/amdfam10/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdfam10(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 70e75e9..b94ef42 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -51,10 +51,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdk8/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bb..8afd507 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -3,6 +3,6 @@ #include #include "northbridge/amd/amdk8/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdk8(void) { enumerate_ht_chain(); } diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index fd244c8..03d0f29 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -22,7 +22,3 @@ config SOUTHBRIDGE_AMD_AMD8111 select IOAPIC select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/amd8111/bootblock.c" - depends on SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 3009c0b..d4660de 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -41,7 +41,7 @@ static void amd8111_enable_rom(void) pci_io_write_config8(dev, 0x43, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_amd8111(void) { amd8111_enable_rom(); } diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 79624e0..fc15c42 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB800 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..9e00219 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -104,7 +104,7 @@ static void enable_clocks(void) *acpi_mmio = reg32; } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb800(void) { /* Setup the rom access for 2M */ enable_rom(); diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 253d73f..09edd1b 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -49,8 +49,5 @@ config ACPI_SCI_IRQ help Set SCI IRQ to 9. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e84743b..f3b53d0 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -90,7 +90,7 @@ static void sb900_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb900(void) { /* Setup the rom access for 2M */ sb900_enable_rom(); diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 8ec3967..d440212 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_SB600 select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB600 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb600/bootblock.c" config EHCI_BAR hex diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 45991ee..0184f73 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -64,7 +64,7 @@ static void sb600_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb600(void) { sb600_enable_rom(); } diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 05f7d09..a6fc722 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -28,11 +28,6 @@ config SOUTHBRIDGE_AMD_SP5100 select IOAPIC select HAVE_USBDEBUG -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb700/bootblock.c" - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) - config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 370cff9..b4bb686 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -64,7 +64,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb700(void) { sb700_enable_rom(); } diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 592f9a7..5490c56 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -23,11 +23,6 @@ config SOUTHBRIDGE_AMD_SB800 select HAVE_USBDEBUG select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb800/bootblock.c" - depends on SOUTHBRIDGE_AMD_SB800 - config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 30d6ac6..6245dca 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -62,7 +62,7 @@ static void sb800_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb800(void) { sb800_enable_rom(); } diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index d72afd8..286c19b 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/broadcom/bcm5785/bootblock.c" - depends on SOUTHBRIDGE_BROADCOM_BCM5785 diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index cadda53..e1e5f31 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void) pci_write_config8(dev, 0x41, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_broadcom_bcm5785(void) { bcm5785_enable_rom(); } diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 7e5109a..a5c5eb8 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB - diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07fa0bc..a875723 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void) pci_write_config16(dev, XBCS, reg16); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82371eb(void) { i82371eb_enable_rom(); } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 3550954..a50e0b1 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT int default 1 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801gx/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82801GX - endif diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 39b0bd4..a0f73b3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -33,7 +33,7 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82801gx(void) { enable_spi_prefetch(); } diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 97927d7..01cff02 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -6,9 +6,9 @@ config SOUTHBRIDGE_NVIDIA_CK804 if SOUTHBRIDGE_NVIDIA_CK804 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/ck804/bootblock.c" +config ID_SECTION_OFFSET + hex + default 0x80 config EHCI_BAR hex diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 29c10c8..3175606 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -42,7 +42,7 @@ static void ck804_enable_rom(void) pci_write_config8(addr, 0x88, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_ck804(void) { ck804_enable_rom(); } diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..e1bb06d 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -6,9 +6,9 @@ config SOUTHBRIDGE_NVIDIA_MCP55 if SOUTHBRIDGE_NVIDIA_MCP55 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/mcp55/bootblock.c" +config ID_SECTION_OFFSET + hex + default 0x80 config EHCI_BAR hex diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index affb025..6fb6dbb 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -53,7 +53,7 @@ static void mcp55_enable_rom(void) pci_write_config16(addr, 0x90, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_mcp55(void) { mcp55_enable_rom(); } diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..ae9a139 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,9 +4,9 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 +config ID_SECTION_OFFSET + hex + default 0x80 if SOUTHBRIDGE_SIS_SIS966 config EHCI_BAR hex @@ -15,3 +15,4 @@ config EHCI_BAR config EHCI_DEBUG_OFFSET hex default 0x98 if SOUTHBRIDGE_SIS_SIS966 + diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index 1ff3cda..45ab81b 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -41,7 +41,7 @@ static void sis966_enable_rom(void) pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); } -static void bootblock_southbridge_init(void) +static void init_southbridge_sis_sis966(void) { sis966_enable_rom(); } diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..9aa1b97 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT default n depends on SOUTHBRIDGE_VIA_VT8237R -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/via/vt8237r/bootblock.c" - depends on SOUTHBRIDGE_VIA_VT8237R diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 8df37aa..0ca0533 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -21,7 +21,7 @@ #include #include -static void bootblock_southbridge_init(void) +static void init_southbridge_via_vt8237r(void) { device_t dev; /* don't walk other busses, HT is not enabled */ From darmawan.salihun at gmail.com Thu Feb 23 12:58:42 2012 From: darmawan.salihun at gmail.com (Darmawan Salihun) Date: Thu, 23 Feb 2012 18:58:42 +0700 Subject: [coreboot] Asus M2V-MX memory init In-Reply-To: <20120222034006.29372.qmail@stuge.se> References: <20120222034006.29372.qmail@stuge.se> Message-ID: Hi guys, Does this have something to do with remapping the RAM "shadowed" by PCI devices to above 4GB? Anyway, I haven't know yet whether Coreboot remaps RAM "shadowed" by PCI devices. Regards, Darmawan On 2/22/12, Peter Stuge wrote: > David Hillman wrote: >> It looks like I am missing something to properly initialize memory >> to get correct SPD info. Maybe SMBUS isn't working properly? > > I think SMBUS is OK and memory init too. Here's the diff between your > two logs with some comments, but there may be more relevant stuff > than what I see. > > Next time when posting logs please make sure that they do not wrap. > One good way is to send them as attachments, under all circumstances > with text/plain mime type. > > > --- m2v_mx-2g 2012-02-22 04:13:21.309138502 +0100 > +++ m2v_mx-4g 2012-02-22 04:13:02.663139149 +0100 > @@ -1,4 +1,4 @@ > -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... > +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... > now booting... > Enabling routing table for node 00 done. > Enabling UP settings > @@ -47,16 +47,21 @@ > sdram_set_spd_registers: paramx :000ceee8 > Device error > Device error > -Device error > +Enabling dual channel memory > Unbuffered > 400MHz > 400MHz > Interleaved > -RAM end at 0x00200000 kB > +RAM end at 0x00400000 kB > Ram3 > IN TEST WAKEUP > 800Initializing memory: done > Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB > +Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB > +Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB > +Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB > +Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB > +Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB > DQS Training:RcvrEn:Pass1: 00 > CTLRMaxDelay=1d > done > @@ -68,41 +73,45 @@ > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > TrainDQSPos: MutualCSPassW[48] :000ce828 > +TrainDQSPos: MutualCSPassW[48] :000ce828 > +TrainDQSPos: MutualCSPassW[48] :000ce828 > +TrainDQSPos: MutualCSPassW[48] :000ce828 > +TrainDQSPos: MutualCSPassW[48] :000ce828 > done > DQS Training:RcvrEn:Pass2: 00 > - CTLRMaxDelay=43 > + CTLRMaxDelay=34 > done > DQS SAVE NVRAM: c2000 > Writing 113222 of size 4 to nvram pos: 0 > -Writing 17161515 of size 4 to nvram pos: 4 > +Writing 17151515 of size 4 to nvram pos: 4 > Writing 17171615 of size 4 to nvram pos: 8 > Writing 15 of size 1 to nvram pos: 12 > Writing 202520 of size 4 to nvram pos: 13 > -Writing 17171918 of size 4 to nvram pos: 17 > -Writing 17191718 of size 4 to nvram pos: 21 > +Writing 18171819 of size 4 to nvram pos: 17 > +Writing 18181718 of size 4 to nvram pos: 21 > Writing 17 of size 1 to nvram pos: 25 > -Writing 33 of size 1 to nvram pos: 26 > +Writing 32 of size 1 to nvram pos: 26 > Writing 0 of size 1 to nvram pos: 27 > Writing 0 of size 1 to nvram pos: 28 > Writing 0 of size 1 to nvram pos: 29 > -Writing 111222 of size 4 to nvram pos: 30 > -Writing 0 of size 4 to nvram pos: 34 > -Writing 0 of size 4 to nvram pos: 38 > -Writing 0 of size 1 to nvram pos: 42 > -Writing 0 of size 4 to nvram pos: 43 > -Writing 2f2f2f2f of size 4 to nvram pos: 47 > -Writing 2f2f2f2f of size 4 to nvram pos: 51 > -Writing 0 of size 1 to nvram pos: 55 > -Writing 43 of size 1 to nvram pos: 56 > +Writing 113222 of size 4 to nvram pos: 30 > +Writing 15141615 of size 4 to nvram pos: 34 > +Writing 15141515 of size 4 to nvram pos: 38 > +Writing 15 of size 1 to nvram pos: 42 > +Writing 202520 of size 4 to nvram pos: 43 > +Writing 17191818 of size 4 to nvram pos: 47 > +Writing 18191716 of size 4 to nvram pos: 51 > +Writing 16 of size 1 to nvram pos: 55 > +Writing 34 of size 1 to nvram pos: 56 > Writing 0 of size 1 to nvram pos: 57 > Writing 0 of size 1 to nvram pos: 58 > Writing 0 of size 1 to nvram pos: 59 > -Writing 741080ab of size 4 to nvram pos: 60 > -DQS Training:tsc[00]=000000005eac6acb > -DQS Training:tsc[01]=000000006087914d > -DQS Training:tsc[02]=0000000060879156 > -DQS Training:tsc[03]=00000000df309c2e > -DQS Training:tsc[04]=00000000f2a194b3 > +Writing 7410809b of size 4 to nvram pos: 60 > +DQS Training:tsc[00]=000000008cbdd63c > +DQS Training:tsc[01]=000000008f476e2e > +DQS Training:tsc[02]=000000008f476e37 > +DQS Training:tsc[03]=000000015b152149 > +DQS Training:tsc[04]=000000016daed79e > Ram4 > v_esp=000cef28 > testx = 5a5a5a5a > @@ -121,7 +130,7 @@ > 0x100000 > Stage: done loading. > Jumping to image. > -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... > +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... > Enumerating buses... > Show all devs...Before device enumeration. > Root Device: enabled 1 > @@ -147,7 +156,7 @@ > PNP: 002e.8: enabled 0 > PNP: 002e.9: enabled 0 > PNP: 002e.a: enabled 0 > -PCI: 00:12.0: enabled 0 > +PCI: 00:12.0: enabled 1 > > Why is 12.0 enabled with 4G? What is 12.0? > > > PCI: 00:13.0: enabled 1 > PCI: 00:13.1: enabled 1 > PCI: 00:18.1: enabled 1 > @@ -177,7 +186,7 @@ > PNP: 002e.8: enabled 0 > PNP: 002e.9: enabled 0 > PNP: 002e.a: enabled 0 > - PCI: 00:12.0: enabled 0 > + PCI: 00:12.0: enabled 1 > PCI: 00:13.0: enabled 1 > PCI: 00:13.1: enabled 1 > PCI: 00:18.1: enabled 1 > @@ -265,7 +274,7 @@ > PCI: 00:00.2 [1106/2336] ops > PCI: 00:00.2 [1106/2336] enabled > PCI: 00:00.3 [1106/3336] ops > -K8M890: UMA base is 7e000000 size is 32 (MB) > +K8M890: UMA base is fa000000 size is 32 (MB) > VIA_X_3 device dump: > 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > @@ -275,7 +284,7 @@ > 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 > 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > -80: ff ff ff 30 00 80 19 00 80 00 00 00 00 00 00 00 > +80: ff ff ff 30 00 fc 19 00 fc 00 00 00 00 00 00 00 > 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > @@ -363,7 +372,7 @@ > d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 > e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 > f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 > -PCI: 00:03.0 PCIe link up after 15000 us > +PCI: 00:03.0 PCIe link up after 15100 us > 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 > 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 > 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 > @@ -399,6 +408,7 @@ > PCI: 00:11.0 [1106/3337] enabled > PCI: 00:11.7 [1106/287e] ops > PCI: 00:11.7 [1106/287e] enabled > +PCI: Static device PCI: 00:12.0 not found, disabling it. > Capability: type 0x08 @ 0x60 > Capability: type 0x0d @ 0x70 > Capability: type 0x08 @ 0x60 > @@ -978,10 +988,10 @@ > PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 > gran: 20 done > Root Device assign_resources, bus 0 link: 0 > -node 0 : uma_memory_base/1024=0x001f8000, mmio_basek=0x00300000, > -basek=0x00000300, limitk=0x00200000 > -node 0: UMA memory starts below mmio_basek > -0: mmio_basek=00300000, basek=00000300, limitk=00200000 > +node 0 : uma_memory_base/1024=0x003e8000, mmio_basek=0x00300000, > +basek=0x00000300, limitk=0x00400000 > + split: 1088K table at =f9ef0000 > +0: mmio_basek=00300000, basek=00300000, limitk=00400000 > Adding UMA memory area > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link > @@ -1114,9 +1124,11 @@ > limit febfffff flags 40040200 index 10000100 > PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags > e0004200 index 10 > - PCI_DOMAIN: 0000 resource base c0000 size 7df40000 align 0 gran 0 limit 0 > + PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 > flags e0004200 index 20 > - PCI_DOMAIN: 0000 resource base 7e000000 size 2000000 align 0 gran 0 limit > + PCI_DOMAIN: 0000 resource base c0000000 size 3fffe000000 align 0 gran 0 > limit 0 flags e0004200 index 30 > + PCI_DOMAIN: 0000 resource base fa000000 size 2000000 align 0 gran 0 limit > 0 flags f0000200 index 7 > > The size for the c0000000 domain is crazy. This is worth looking into > further. I did some manual line unwrapping above. The email had extra > line endings damaging the log messages. It will be easier for you if > you fix that. > > > PCI: 00:18.0 child on link 0 PCI: 00:00.0 > PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff > @@ -1368,7 +1380,9 @@ > DONE fixed MTRRs > Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB > ADDRESS_MASK_HIGH=0xff > -Setting variable MTRR 1, base: 2016MB, range: 32MB, type UC > +Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB > +ADDRESS_MASK_HIGH=0xff > +Setting variable MTRR 2, base: 4000MB, range: 32MB, type UC > > Find out why the 32 MB framebuffer ends at TOM on 2GB, but ends at > TOM-64MB on 4GB, what the top 64MB is for. Hopefully PCI resources > but 64MB is unexpectedly small for that. Investigate. > > > ADDRESS_MASK_HIGH=0xff > DONE variable MTRRs > Clear out the extra MTRR's > @@ -1493,7 +1507,7 @@ > 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 > 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 > -90: 00 06 19 88 a0 cc 00 00 00 3a 00 00 00 00 00 00 > +90: 00 04 99 88 a0 cc 00 02 00 3a 00 00 00 00 00 00 > a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 > @@ -1506,7 +1520,7 @@ > 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 > 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 > 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 > -50: 00 03 33 03 00 04 01 80 08 00 01 80 00 00 00 00 > +50: 00 03 33 03 00 04 01 fc 08 00 01 80 00 00 00 00 > 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 > 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 > 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > @@ -1605,14 +1619,14 @@ > PCI: 03:00.0: enabled 1 > PCI: 04:01.0: enabled 1 > cbmem_initialize: acpi_slp_type=0 > -Initializing CBMEM area to 0x7def0000 (1114112 bytes) > -Adding CBMEM entry as no. 1 > -Moving GDT to 7def0200...ok > -High Tables Base is 7def0000. > -Adding CBMEM entry as no. 2 > -ACPI: Writing ACPI tables at 7def0400... > +Initializing CBMEM area to 0xf9ef0000 (1114112 bytes) > +ERROR: CBMEM was not initialized yet. > +Error: Could not relocate GDT. > +High Tables Base is f9ef0000. > +ERROR: CBMEM was not initialized yet. > > This is very bad. Investigate. The CBMEM code should be easy to > follow. > > > +ACPI: Writing ACPI tables at f0000... > ACPI: * FACS > -ACPI: * DSDT @ 7def0540 Length ba5 > +ACPI: * DSDT @ 000f0140 Length ba5 > > So with 2GB ACPI tables are written high, with 4GB because CBMEM > fails they end up in F-segment. > > > ACPI: * FADT > ACPI: added table 1/32, length now 40 > ACPI: * HPET > @@ -1626,7 +1640,9 @@ > set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, > sizek=00000280 > -set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, > sizek=001f7d00 > +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, > sizek=002ffd00 > +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00300000, > sizek=ffff8000 > > At least the last one is bogus. > > > ACPI: added table 5/32, length now 56 > ACPI: * SLIT > ACPI: added table 6/32, length now 60 > @@ -1645,9 +1661,8 @@ > 1100mv Pstate_power[4] = 169141mw > ACPI: added table 7/32, length now 64 > ACPI: done. > -ACPI tables: 4677 bytes. > -Adding CBMEM entry as no. 3 > -smbios_write_tables: 7defb800 > +ERROR: CBMEM was not initialized yet. > +smbios_write_tables: 000f1400 > Root Device (ASUS M2V-MX Mainboard) > APIC_CLUSTER: 0 (AMD K8 Root Complex) > APIC: 00 (Socket AM2 CPU) > @@ -1697,36 +1712,37 @@ > PCI: 01:00.0 () > PCI: 03:00.0 () > PCI: 04:01.0 () > -SMBIOS tables: 277 bytes. > -Adding CBMEM entry as no. 4 > +SMBIOS size 277 bytes > +ERROR: CBMEM was not initialized yet. > Writing high table forward entry at 0x00000500 > -Wrote coreboot table at: 00000500 - 00000518 checksum c1ee > +Wrote coreboot table at: 00000500 - 00000518 checksum eaaf > New low_table_end: 0x00000518 > -Now going to write high coreboot table at 0x7defc000 > -rom_table_end = 0x7defc000 > +Now going to write high coreboot table at 0x000f1520 > +rom_table_end = 0x000f1520 > Adjust low_table_end from 0x00000518 to 0x00001000 > -Adjust rom_table_end from 0x7defc000 to 0x7df00000 > +Adjust rom_table_end from 0x000f1520 to 0x00100000 > Adding high table area > coreboot memory table: > 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES > 1. 0000000000001000-000000000009ffff: RAM > - 2. 00000000000c0000-000000007deeffff: RAM > - 3. 000000007def0000-000000007dffffff: CONFIGURATION TABLES > - 4. 000000007e000000-000000007fffffff: RESERVED > - 5. 00000000e0000000-00000000efffffff: RESERVED > - 6. 00000000fec00000-00000000fec000ff: RESERVED > - 7. 00000000fecc0000-00000000fecc00ff: RESERVED > - 8. 00000000ff000000-00000000ffffffff: RESERVED > -Wrote coreboot table at: 7defc000 - 7defc214 checksum 336b > -coreboot table: 532 bytes. > -Adding CBMEM entry as no. 5 > + 2. 00000000000c0000-00000000000effff: RAM > + 3. 00000000000f0000-00000000000fffff: CONFIGURATION TABLES > + 4. 0000000000100000-00000000bfffffff: RAM > + 5. 00000000c0000000-00000000dfffffff: RAM > + 6. 00000000e0000000-00000000efffffff: RESERVED > + 7. 00000000f0000000-00000000f9eeffff: RAM > + 8. 00000000f9ef0000-00000000f9ffffff: CONFIGURATION TABLES > + 9. 00000000fa000000-00000000fbffffff: RESERVED > +10. 00000000fc000000-00000000febfffff: RAM > +11. 00000000fec00000-00000000fec000ff: RESERVED > +12. 00000000fec00100-00000000fecbffff: RAM > +13. 00000000fecc0000-00000000fecc00ff: RESERVED > +14. 00000000fecc0100-00000000feffffff: RAM > +15. 00000000ff000000-00000000ffffffff: RESERVED > +16. 0000000100000000-00000400bdffffff: RAM > > Here, coreboot says that you have almost 4 TB of RAM. Investigate. > > > +Wrote coreboot table at: 000f1520 - 000f17d4 checksum f32e > +ERROR: CBMEM was not initialized yet. > Multiboot Information structure has been written. > - 0. FREE SPACE 7dffe000 00002000 > - 1. GDT 7def0200 00000200 > - 2. ACPI 7def0400 0000b400 > - 3. SMBIOS 7defb800 00000800 > - 4. COREBOOT 7defc000 00002000 > - 5. ACPI RESUME7defe000 00100000 > Searching for fallback/payload > Check cmos_layout.bin > Check pci1106,3230.rom > @@ -1737,26 +1753,30 @@ > Loading segment from rom address 0xfffad538 > data (compression=1) > - New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize > 0xc8aa > - (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 > filesize 0xc8aa > + New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize > 0xc8ba > + (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 > filesize 0xc8ba > Loading segment from rom address 0xfffad554 > Entry Point 0x00000000 > -Loading Segment: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: > -0x000000000000c8aa > -lb: [0x0000000000100000, 0x0000000000198000) > -Post relocation: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: > -0x000000000000c8aa > -using LZMA > -[ 0x000e6b54, 00100000, 0x00100000) <- fffad570 > -dest 000e6b54, end 00100000, bouncebuffer 7ddc0000 > -Loaded segments > -Jumping to boot code at fc8e4 > -entry = 0x000fc8e4 > -lb_start = 0x00100000 > -lb_size = 0x00098000 > -adjust = 0x7dd58000 > -buffer = 0x7ddc0000 > - elf_boot_notes = 0x001270c8 > -adjusted_boot_notes = 0x7de7f0c8 > -Start bios (version 1.6.3-20120215_224505-debby) > +No matching ram area found for range: > + [0x00000000000e6b54, 0x0000000000100000) > > And finally instead of the "Start bios" message from SeaBIOS it's not > possible to load the payload to it's address, because.. > > > +Ram areas > + [0x0000000000000000, 0x0000000000001000) Reserved > + [0x0000000000001000, 0x00000000000a0000) RAM > + [0x00000000000c0000, 0x00000000000f0000) RAM > + [0x00000000000f0000, 0x0000000000100000) Reserved > > ..the F segment has been marked reserved, because this is where the > ACPI tables were written to, because the highmem address was not > available, because CBMEM failed to initialize. > > > The error isn't really with hardware init I believe, but with > calculation, generation and preparation of system description data > for the payload and later the operating system. You need to find out > why coreboot gets upset with 4G of memory. > > > //Peter > > -- > coreboot mailing list: coreboot at coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- From gerrit at coreboot.org Thu Feb 23 13:20:03 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 23 Feb 2012 13:20:03 +0100 Subject: [coreboot] Patch set updated for coreboot: 0e08243 Auto-generate bootblock initialisation References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473 -gerrit commit 0e0824334189ff17f31d211c5488b86206c61035 Author: Ky?sti M?lkki Date: Thu Feb 23 14:17:53 2012 +0200 Auto-generate bootblock initialisation The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init The following no-operation bootblock.c files were removed: - northbridge/amd/agesa/family10/bootblock.c - northbridge/amd/agesa/family12/bootblock.c - northbridge/amd/agesa/family14/bootblock.c - northbridge/amd/agesa/family15/bootblock.c A new init function called from bootblock is declared as: - unsigned long init_mainboard(int bsp_cpu) For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock calls init_mainboard(false). Usually AP CPU has nothing to do here. By default, build toolchain creates and includes an init_mainboard() function in file build/mainboard/x/x/bootblock_autogen.h that executes init functions from any bootblock.c files for all chips listed in mainboard/devtree.cb. Alternatively a mainboard/x/x/bootblock.c file is added in the bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set. One should copy the auto-generated init_mainboard() to this file, and optionally read various bootstrap signals or status bits from super-io and southbridge component to gain some control over the selection of romstage to boot via the return value. Samples of such (yet not implemented) controls for boot behaviour: - Reset CMOS to defaults on user request (jumper). - Use fallback prefix after power-button 4s override. - Refuse boot after intruder detection. - On remote wakeup, request network boot. Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Kconfig | 7 +---- src/arch/x86/Makefile.inc | 9 +++++- src/arch/x86/include/bootblock_common.h | 17 +------------- src/arch/x86/init/bootblock_normal.c | 8 +++--- src/arch/x86/init/bootblock_simple.c | 10 ++++---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +--- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 10 +++++++- src/northbridge/amd/agesa/family10/Kconfig | 3 -- src/northbridge/amd/agesa/family10/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family12/Kconfig | 4 --- src/northbridge/amd/agesa/family12/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family14/Kconfig | 4 --- src/northbridge/amd/agesa/family14/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family15/Kconfig | 3 -- src/northbridge/amd/agesa/family15/bootblock.c | 25 -------------------- src/northbridge/amd/amdfam10/Kconfig | 4 --- src/northbridge/amd/amdfam10/bootblock.c | 2 +- src/northbridge/amd/amdk8/Kconfig | 4 --- src/northbridge/amd/amdk8/bootblock.c | 2 +- src/southbridge/amd/amd8111/Kconfig | 4 --- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/Kconfig | 3 -- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 3 -- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb900/Kconfig | 3 -- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/Kconfig | 3 -- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/Kconfig | 5 ---- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/Kconfig | 5 ---- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/Kconfig | 4 --- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/i82371eb/Kconfig | 5 ---- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/Kconfig | 5 ---- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/nvidia/ck804/Kconfig | 6 ++-- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/Kconfig | 6 ++-- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/Kconfig | 7 +++-- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/Kconfig | 4 --- src/southbridge/via/vt8237r/bootblock.c | 2 +- 47 files changed, 55 insertions(+), 240 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e71d0f3..07ad95f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -67,8 +67,8 @@ config PC80_SYSTEM bool default y -config BOOTBLOCK_NORTHBRIDGE_INIT - string +config HAS_MAINBOARD_BOOTBLOCK + def_bool n config HAVE_CMOS_DEFAULT def_bool n @@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE string depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config BIG_ENDIAN bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 624b510..e1a9f6d 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -324,11 +324,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig + @printf " SCONFIG $(subst $(src)/,,$(<)) (bootblock)\n" + mkdir -p $(@D) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F) $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index bd19682..69ab22c 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,22 +1,7 @@ #include -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#else -static void bootblock_cpu_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - #include +#include "bootblock_autogen.h" #if CONFIG_USE_OPTION_TABLE #include diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index f8ae13b..48b4131 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -4,13 +4,13 @@ static void main(unsigned long bist) { unsigned long entry; + int bsp_cpu = boot_cpu(); int boot_mode; - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); + if (bsp_cpu) { #if CONFIG_USE_OPTION_TABLE sanitize_cmos(); #endif diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 41f73b4..f4e4bbf 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -2,15 +2,15 @@ static void main(unsigned long bist) { - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + int bsp_cpu = boot_cpu(); + + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); #if CONFIG_USE_OPTION_TABLE + if (bsp_cpu) sanitize_cmos(); #endif - } const char* target1 = "fallback/romstage"; unsigned long entry; diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index cdff24f..547cc21 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAS_MAINBOARD_BOOTBLOCK select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO @@ -90,10 +91,6 @@ config HEAP_SIZE hex default 0xc0000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "mainboard/hp/dl165_g6_fam10/bootblock.c" - config MMCONF_SUPPORT_DEFAULT bool default y diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 2c56c4c..e7c0680 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) +/* FIXME: This appears to be a super-io initialisation, + * placed in the mainboard directory. + */ void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); @@ -43,6 +46,11 @@ void shc4307_init(void) shc4307_exit_ext_func_mode(CMOS_DEV); } -static void bootblock_southbridge_init(void) { +static unsigned long init_mainboard(int bsp_cpu) +{ + if (!bsp_cpu) return 0; + init_northbridge_amd_amdfam10(); + //init_southbridge_broadcom_bcm5785(); shc4307_init(); + return 0; } diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index 62a6cd4..0bb16d9 100755 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family10/bootblock.c" endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family10/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index fc3c436..8ab5de8 100755 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -73,7 +73,3 @@ if DIMM_DDR3 endif endif -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family12/bootblock.c" - depends on NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family12/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 44f93c1..e462153 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER int default 16 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family14/bootblock.c" - endif diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family14/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig index 52f7a1e..382c1af 100644 --- a/src/northbridge/amd/agesa/family15/Kconfig +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int default 64 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family15/bootblock.c" endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c deleted file mode 100644 index fc62c3e..0000000 --- a/src/northbridge/amd/agesa/family15/bootblock.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index a14339e..633d378 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a..328e9ad 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -3,7 +3,7 @@ #include #include "northbridge/amd/amdfam10/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdfam10(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 70e75e9..b94ef42 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -51,10 +51,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdk8/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bb..8afd507 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -3,6 +3,6 @@ #include #include "northbridge/amd/amdk8/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdk8(void) { enumerate_ht_chain(); } diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index fd244c8..03d0f29 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -22,7 +22,3 @@ config SOUTHBRIDGE_AMD_AMD8111 select IOAPIC select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/amd8111/bootblock.c" - depends on SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 3009c0b..d4660de 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -41,7 +41,7 @@ static void amd8111_enable_rom(void) pci_io_write_config8(dev, 0x43, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_amd8111(void) { amd8111_enable_rom(); } diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 27338fc..ea5adf3 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -47,9 +47,6 @@ config ACPI_SCI_IRQ default 0x9 help Set SCI IRQ to 9. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb700/bootblock.c" config REDIRECT_SBCIMX_TRACE_TO_SERIAL bool "Redirect AMD Southbridge CIMX Trace to serial console" diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 401c039..657fbdd 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -90,7 +90,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb700(void) { /* Setup the rom access for 2M */ sb700_enable_rom(); diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 79624e0..fc15c42 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB800 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..9e00219 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -104,7 +104,7 @@ static void enable_clocks(void) *acpi_mmio = reg32; } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb800(void) { /* Setup the rom access for 2M */ enable_rom(); diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 253d73f..09edd1b 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -49,8 +49,5 @@ config ACPI_SCI_IRQ help Set SCI IRQ to 9. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e84743b..f3b53d0 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -90,7 +90,7 @@ static void sb900_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb900(void) { /* Setup the rom access for 2M */ sb900_enable_rom(); diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 8ec3967..d440212 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_SB600 select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB600 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb600/bootblock.c" config EHCI_BAR hex diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 45991ee..0184f73 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -64,7 +64,7 @@ static void sb600_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb600(void) { sb600_enable_rom(); } diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 05f7d09..a6fc722 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -28,11 +28,6 @@ config SOUTHBRIDGE_AMD_SP5100 select IOAPIC select HAVE_USBDEBUG -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb700/bootblock.c" - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) - config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 370cff9..b4bb686 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -64,7 +64,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb700(void) { sb700_enable_rom(); } diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 592f9a7..5490c56 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -23,11 +23,6 @@ config SOUTHBRIDGE_AMD_SB800 select HAVE_USBDEBUG select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb800/bootblock.c" - depends on SOUTHBRIDGE_AMD_SB800 - config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 30d6ac6..6245dca 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -62,7 +62,7 @@ static void sb800_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb800(void) { sb800_enable_rom(); } diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index d72afd8..286c19b 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/broadcom/bcm5785/bootblock.c" - depends on SOUTHBRIDGE_BROADCOM_BCM5785 diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index cadda53..e1e5f31 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void) pci_write_config8(dev, 0x41, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_broadcom_bcm5785(void) { bcm5785_enable_rom(); } diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 7e5109a..a5c5eb8 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB - diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07fa0bc..a875723 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void) pci_write_config16(dev, XBCS, reg16); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82371eb(void) { i82371eb_enable_rom(); } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 3550954..a50e0b1 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT int default 1 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801gx/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82801GX - endif diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 39b0bd4..a0f73b3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -33,7 +33,7 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82801gx(void) { enable_spi_prefetch(); } diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 97927d7..01cff02 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -6,9 +6,9 @@ config SOUTHBRIDGE_NVIDIA_CK804 if SOUTHBRIDGE_NVIDIA_CK804 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/ck804/bootblock.c" +config ID_SECTION_OFFSET + hex + default 0x80 config EHCI_BAR hex diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 29c10c8..3175606 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -42,7 +42,7 @@ static void ck804_enable_rom(void) pci_write_config8(addr, 0x88, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_ck804(void) { ck804_enable_rom(); } diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..e1bb06d 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -6,9 +6,9 @@ config SOUTHBRIDGE_NVIDIA_MCP55 if SOUTHBRIDGE_NVIDIA_MCP55 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/mcp55/bootblock.c" +config ID_SECTION_OFFSET + hex + default 0x80 config EHCI_BAR hex diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index affb025..6fb6dbb 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -53,7 +53,7 @@ static void mcp55_enable_rom(void) pci_write_config16(addr, 0x90, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_mcp55(void) { mcp55_enable_rom(); } diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..ae9a139 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,9 +4,9 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 +config ID_SECTION_OFFSET + hex + default 0x80 if SOUTHBRIDGE_SIS_SIS966 config EHCI_BAR hex @@ -15,3 +15,4 @@ config EHCI_BAR config EHCI_DEBUG_OFFSET hex default 0x98 if SOUTHBRIDGE_SIS_SIS966 + diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index 1ff3cda..45ab81b 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -41,7 +41,7 @@ static void sis966_enable_rom(void) pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); } -static void bootblock_southbridge_init(void) +static void init_southbridge_sis_sis966(void) { sis966_enable_rom(); } diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..9aa1b97 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT default n depends on SOUTHBRIDGE_VIA_VT8237R -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/via/vt8237r/bootblock.c" - depends on SOUTHBRIDGE_VIA_VT8237R diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 8df37aa..0ca0533 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -21,7 +21,7 @@ #include #include -static void bootblock_southbridge_init(void) +static void init_southbridge_via_vt8237r(void) { device_t dev; /* don't walk other busses, HT is not enabled */ From gerrit at coreboot.org Thu Feb 23 13:40:00 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Thu, 23 Feb 2012 13:40:00 +0100 Subject: [coreboot] New patch to review for coreboot: aafcf93 Ati video: Apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/678 -gerrit commit aafcf93e1a8d5b51ccdf4e7f4bd62de5a5c81f15 Author: Ky?sti M?lkki Date: Thu Feb 23 13:54:23 2012 +0200 Ati video: Apply un-written naming rules Rename Kconfig to match directory name. Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61 Signed-off-by: Ky?sti M?lkki --- src/drivers/ati/ragexl/Kconfig | 2 +- src/drivers/ati/ragexl/Makefile.inc | 2 +- src/mainboard/intel/jarrell/Kconfig | 2 +- src/mainboard/iwill/dk8s2/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/ati/ragexl/Kconfig b/src/drivers/ati/ragexl/Kconfig index 117aa66..86109b1 100644 --- a/src/drivers/ati/ragexl/Kconfig +++ b/src/drivers/ati/ragexl/Kconfig @@ -1,2 +1,2 @@ -config ATI_RAGE_XL +config DRIVERS_ATI_RAGEXL bool diff --git a/src/drivers/ati/ragexl/Makefile.inc b/src/drivers/ati/ragexl/Makefile.inc index 107885e..8b59597 100644 --- a/src/drivers/ati/ragexl/Makefile.inc +++ b/src/drivers/ati/ragexl/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_ATI_RAGE_XL) += xlinit.c +driver-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 282ec4b..a3c34f4 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select UDELAY_TSC select USE_WATCHDOG_ON_BOOT - select ATI_RAGE_XL + select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_2048 config MAINBOARD_DIR diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index f9f1b57..1c35cb2 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT - select ATI_RAGE_XL + select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT From peter at stuge.se Thu Feb 23 14:16:46 2012 From: peter at stuge.se (Peter Stuge) Date: Thu, 23 Feb 2012 14:16:46 +0100 Subject: [coreboot] Dual SPI Flash In-Reply-To: <4F460122.9000304@schinagl.nl> References: <4F460122.9000304@schinagl.nl> Message-ID: <20120223131646.4021.qmail@stuge.se> Oliver Schinagl wrote: > I noticed an intersting hack on the coreboot wiki: > http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash > > It lists a neat trick to double stack two spi flash modules to make > testing/developping/flashing coreboot easier. However there's no > schematic or other information available on how to actually build > this setup. Could the author possibly supply this extra information? > Since not even the resitor values or switch connection is documented. I'm not the author but there is documentation at http://stuge.se/m57sli/ for what is called the "simple" modification. Resistor values are generally not critical and the switch connection should be obvious after study of the flash chip data sheet. //Peter From hillmands at gmail.com Thu Feb 23 18:58:38 2012 From: hillmands at gmail.com (David Hillman) Date: Thu, 23 Feb 2012 12:58:38 -0500 Subject: [coreboot] Asus M2V-MX memory init Message-ID: <7yed0nt4i28t7qpm7x9erba1.1330019918542@email.android.com> Thanks for the quick reply. ?My experience with Coreboot is very limited; I started playing with the code a few weeks ago. ?As far as getting this particular board going, I started with the code from the Asus M2V-MX_SE (different SuperIO, mainly). ?Then, I changed info in devicetree.cb, romstage.c, mainboard.c and Kconfig files as needed. "what is 12.0?" It is listed as VIA LAN in devicetree.cb. ?I turned it off because M2V-MX has separate Realtek chip. ?I don't know why it is still there. What do fn_ctrl_lo and fn_ctrl_hi in devicetree.cb do? ?I don't really understand them, so I left them alone. It seems devicetree.cb needs to be looked at. I will investigate more to get a better understanding. coreboot-request at coreboot.org wrote: Send coreboot mailing list submissions to coreboot at coreboot.org To subscribe or unsubscribe via the World Wide Web, visit http://www.coreboot.org/mailman/listinfo/coreboot or, via email, send a message with subject or body 'help' to coreboot-request at coreboot.org You can reach the person managing the list at coreboot-owner at coreboot.org When replying, please edit your Subject line so it is more specific than "Re: Contents of coreboot digest..." Today's Topics: ?? 1. Re: Asus M2V-MX memory init (Peter Stuge) ?? 2. Re: flash-chip (and compatibles) (Oliver Schinagl) ?? 3. Patch merged into coreboot/master: 3d3abb2 Remove old AMD ????? fam10 fixme comment (gerrit at coreboot.org) ?? 4. Re: Coreboot support for ASUS M5 A99X EVO ? (Bernhard Urban) ---------------------------------------------------------------------- Message: 1 Date: Wed, 22 Feb 2012 04:40:06 +0100 From: Peter Stuge To: coreboot at coreboot.org Subject: Re: [coreboot] Asus M2V-MX memory init Message-ID: <20120222034006.29372.qmail at stuge.se> Content-Type: text/plain; charset=us-ascii David Hillman wrote: > It looks like I am missing something to properly initialize memory > to get correct SPD info.? Maybe SMBUS isn't working properly? I think SMBUS is OK and memory init too. Here's the diff between your two logs with some comments, but there may be more relevant stuff than what I see. Next time when posting logs please make sure that they do not wrap. One good way is to send them as attachments, under all circumstances with text/plain mime type. --- m2v_mx-2g 2012-02-22 04:13:21.309138502 +0100 +++ m2v_mx-4g 2012-02-22 04:13:02.663139149 +0100 @@ -1,4 +1,4 @@ -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings @@ -47,16 +47,21 @@ sdram_set_spd_registers: paramx :000ceee8 Device error Device error -Device error +Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved -RAM end at 0x00200000 kB +RAM end at 0x00400000 kB Ram3 IN TEST WAKEUP 800Initializing memory:? done Setting variable MTRR 2, base:??? 0MB, range: 2048MB, type WB +Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB +Setting variable MTRR 4, base: 3072MB, range:? 512MB, type WB +Setting variable MTRR 5, base: 3584MB, range:? 256MB, type WB +Setting variable MTRR 6, base: 3840MB, range:? 128MB, type WB +Setting variable MTRR 7, base: 3968MB, range:?? 64MB, type WB DQS Training:RcvrEn:Pass1: 00 ? CTLRMaxDelay=1d ? done @@ -68,41 +73,45 @@ TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 ? done DQS Training:RcvrEn:Pass2: 00 - CTLRMaxDelay=43 + CTLRMaxDelay=34 ? done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 -Writing 17161515 of size 4 to nvram pos: 4 +Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 -Writing 17171918 of size 4 to nvram pos: 17 -Writing 17191718 of size 4 to nvram pos: 21 +Writing 18171819 of size 4 to nvram pos: 17 +Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 -Writing 33 of size 1 to nvram pos: 26 +Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 -Writing 111222 of size 4 to nvram pos: 30 -Writing 0 of size 4 to nvram pos: 34 -Writing 0 of size 4 to nvram pos: 38 -Writing 0 of size 1 to nvram pos: 42 -Writing 0 of size 4 to nvram pos: 43 -Writing 2f2f2f2f of size 4 to nvram pos: 47 -Writing 2f2f2f2f of size 4 to nvram pos: 51 -Writing 0 of size 1 to nvram pos: 55 -Writing 43 of size 1 to nvram pos: 56 +Writing 113222 of size 4 to nvram pos: 30 +Writing 15141615 of size 4 to nvram pos: 34 +Writing 15141515 of size 4 to nvram pos: 38 +Writing 15 of size 1 to nvram pos: 42 +Writing 202520 of size 4 to nvram pos: 43 +Writing 17191818 of size 4 to nvram pos: 47 +Writing 18191716 of size 4 to nvram pos: 51 +Writing 16 of size 1 to nvram pos: 55 +Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 -Writing 741080ab of size 4 to nvram pos: 60 -DQS Training:tsc[00]=000000005eac6acb -DQS Training:tsc[01]=000000006087914d -DQS Training:tsc[02]=0000000060879156 -DQS Training:tsc[03]=00000000df309c2e -DQS Training:tsc[04]=00000000f2a194b3 +Writing 7410809b of size 4 to nvram pos: 60 +DQS Training:tsc[00]=000000008cbdd63c +DQS Training:tsc[01]=000000008f476e2e +DQS Training:tsc[02]=000000008f476e37 +DQS Training:tsc[03]=000000015b152149 +DQS Training:tsc[04]=000000016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a @@ -121,7 +130,7 @@ 0x100000 Stage: done loading. Jumping to image. -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 @@ -147,7 +156,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 -PCI: 00:12.0: enabled 0 +PCI: 00:12.0: enabled 1 Why is 12.0 enabled with 4G? What is 12.0? PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -177,7 +186,7 @@ ???? PNP: 002e.8: enabled 0 ???? PNP: 002e.9: enabled 0 ???? PNP: 002e.a: enabled 0 -?? PCI: 00:12.0: enabled 0 +?? PCI: 00:12.0: enabled 1 ??? PCI: 00:13.0: enabled 1 ??? PCI: 00:13.1: enabled 1 ?? PCI: 00:18.1: enabled 1 @@ -265,7 +274,7 @@ PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops -K8M890: UMA base is 7e000000 size is 32 (MB) +K8M890: UMA base is fa000000 size is 32 (MB) ? VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -275,7 +284,7 @@ 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80: ff ff ff 30 00 80 19 00 80 00 00 00 00 00 00 00 +80: ff ff ff 30 00 fc 19 00 fc 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -363,7 +372,7 @@ d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 -PCI: 00:03.0 PCIe link up after 15000 us +PCI: 00:03.0 PCIe link up after 15100 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 @@ -399,6 +408,7 @@ PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled +PCI: Static device PCI: 00:12.0 not found, disabling it. Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 @@ -978,10 +988,10 @@ PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 -node 0 : uma_memory_base/1024=0x001f8000, mmio_basek=0x00300000, -basek=0x00000300, limitk=0x00200000 -node 0: UMA memory starts below mmio_basek -0: mmio_basek=00300000, basek=00000300, limitk=00200000 +node 0 : uma_memory_base/1024=0x003e8000, mmio_basek=0x00300000, +basek=0x00000300, limitk=0x00400000 + split: 1088K table at =f9ef0000 +0: mmio_basek=00300000, basek=00300000, limitk=00400000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link @@ -1114,9 +1124,11 @@ limit febfffff flags 40040200 index 10000100 ?? PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 -? PCI_DOMAIN: 0000 resource base c0000 size 7df40000 align 0 gran 0 limit 0 +? PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 -? PCI_DOMAIN: 0000 resource base 7e000000 size 2000000 align 0 gran 0 limit +? PCI_DOMAIN: 0000 resource base c0000000 size 3fffe000000 align 0 gran 0 limit 0 flags e0004200 index 30 +? PCI_DOMAIN: 0000 resource base fa000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 The size for the c0000000 domain is crazy. This is worth looking into further. I did some manual line unwrapping above. The email had extra line endings damaging the log messages. It will be easier for you if you fix that. ??? PCI: 00:18.0 child on link 0 PCI: 00:00.0 ??? PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff @@ -1368,7 +1380,9 @@ DONE fixed MTRRs Setting variable MTRR 0, base:??? 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff -Setting variable MTRR 1, base: 2016MB, range:?? 32MB, type UC +Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB +ADDRESS_MASK_HIGH=0xff +Setting variable MTRR 2, base: 4000MB, range:?? 32MB, type UC Find out why the 32 MB framebuffer ends at TOM on 2GB, but ends at TOM-64MB on 4GB, what the top 64MB is for. Hopefully PCI resources but 64MB is unexpectedly small for that. Investigate. ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's @@ -1493,7 +1507,7 @@ 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 -90: 00 06 19 88 a0 cc 00 00 00 3a 00 00 00 00 00 00 +90: 00 04 99 88 a0 cc 00 02 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -1506,7 +1520,7 @@ 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 -50: 00 03 33 03 00 04 01 80 08 00 01 80 00 00 00 00 +50: 00 03 33 03 00 04 01 fc 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -1605,14 +1619,14 @@ PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 -Initializing CBMEM area to 0x7def0000 (1114112 bytes) -Adding CBMEM entry as no. 1 -Moving GDT to 7def0200...ok -High Tables Base is 7def0000. -Adding CBMEM entry as no. 2 -ACPI: Writing ACPI tables at 7def0400... +Initializing CBMEM area to 0xf9ef0000 (1114112 bytes) +ERROR: CBMEM was not initialized yet. +Error: Could not relocate GDT. +High Tables Base is f9ef0000. +ERROR: CBMEM was not initialized yet. This is very bad. Investigate. The CBMEM code should be easy to follow. +ACPI: Writing ACPI tables at f0000... ACPI:???? * FACS -ACPI:???? * DSDT @ 7def0540 Length ba5 +ACPI:???? * DSDT @ 000f0140 Length ba5 So with 2GB ACPI tables are written high, with 4GB because CBMEM fails they end up in F-segment. ACPI:???? * FADT ACPI: added table 1/32, length now 40 ACPI:??? * HPET @@ -1626,7 +1640,9 @@ set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 -set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001f7d00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00300000, sizek=ffff8000 At least the last one is bogus. ACPI: added table 5/32, length now 56 ACPI:??? * SLIT ACPI: added table 6/32, length now 60 @@ -1645,9 +1661,8 @@ 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. -ACPI tables: 4677 bytes. -Adding CBMEM entry as no. 3 -smbios_write_tables: 7defb800 +ERROR: CBMEM was not initialized yet. +smbios_write_tables: 000f1400 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) @@ -1697,36 +1712,37 @@ PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () -SMBIOS tables: 277 bytes. -Adding CBMEM entry as no. 4 +SMBIOS size 277 bytes +ERROR: CBMEM was not initialized yet. Writing high table forward entry at 0x00000500 -Wrote coreboot table at: 00000500 - 00000518? checksum c1ee +Wrote coreboot table at: 00000500 - 00000518? checksum eaaf New low_table_end: 0x00000518 -Now going to write high coreboot table at 0x7defc000 -rom_table_end = 0x7defc000 +Now going to write high coreboot table at 0x000f1520 +rom_table_end = 0x000f1520 Adjust low_table_end from 0x00000518 to 0x00001000 -Adjust rom_table_end from 0x7defc000 to 0x7df00000 +Adjust rom_table_end from 0x000f1520 to 0x00100000 Adding high table area coreboot memory table: ? 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES ? 1. 0000000000001000-000000000009ffff: RAM - 2. 00000000000c0000-000000007deeffff: RAM - 3. 000000007def0000-000000007dffffff: CONFIGURATION TABLES - 4. 000000007e000000-000000007fffffff: RESERVED - 5. 00000000e0000000-00000000efffffff: RESERVED - 6. 00000000fec00000-00000000fec000ff: RESERVED - 7. 00000000fecc0000-00000000fecc00ff: RESERVED - 8. 00000000ff000000-00000000ffffffff: RESERVED -Wrote coreboot table at: 7defc000 - 7defc214? checksum 336b -coreboot table: 532 bytes. -Adding CBMEM entry as no. 5 + 2. 00000000000c0000-00000000000effff: RAM + 3. 00000000000f0000-00000000000fffff: CONFIGURATION TABLES + 4. 0000000000100000-00000000bfffffff: RAM + 5. 00000000c0000000-00000000dfffffff: RAM + 6. 00000000e0000000-00000000efffffff: RESERVED + 7. 00000000f0000000-00000000f9eeffff: RAM + 8. 00000000f9ef0000-00000000f9ffffff: CONFIGURATION TABLES + 9. 00000000fa000000-00000000fbffffff: RESERVED +10. 00000000fc000000-00000000febfffff: RAM +11. 00000000fec00000-00000000fec000ff: RESERVED +12. 00000000fec00100-00000000fecbffff: RAM +13. 00000000fecc0000-00000000fecc00ff: RESERVED +14. 00000000fecc0100-00000000feffffff: RAM +15. 00000000ff000000-00000000ffffffff: RESERVED +16. 0000000100000000-00000400bdffffff: RAM Here, coreboot says that you have almost 4 TB of RAM. Investigate. +Wrote coreboot table at: 000f1520 - 000f17d4? checksum f32e +ERROR: CBMEM was not initialized yet. Multiboot Information structure has been written. - 0. FREE SPACE 7dffe000 00002000 - 1. GDT??????? 7def0200 00000200 - 2. ACPI?????? 7def0400 0000b400 - 3. SMBIOS???? 7defb800 00000800 - 4. COREBOOT?? 7defc000 00002000 - 5. ACPI RESUME7defe000 00100000 Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom @@ -1737,26 +1753,30 @@ Loading segment from rom address 0xfffad538 ?? data (compression=1) -? New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8aa -? (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8aa +? New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8ba +? (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8ba Loading segment from rom address 0xfffad554 ?? Entry Point 0x00000000 -Loading Segment: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: -0x000000000000c8aa -lb: [0x0000000000100000, 0x0000000000198000) -Post relocation: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: -0x000000000000c8aa -using LZMA -[ 0x000e6b54, 00100000, 0x00100000) <- fffad570 -dest 000e6b54, end 00100000, bouncebuffer 7ddc0000 -Loaded segments -Jumping to boot code at fc8e4 -entry??? = 0x000fc8e4 -lb_start = 0x00100000 -lb_size? = 0x00098000 -adjust?? = 0x7dd58000 -buffer?? = 0x7ddc0000 -???? elf_boot_notes = 0x001270c8 -adjusted_boot_notes = 0x7de7f0c8 -Start bios (version 1.6.3-20120215_224505-debby) +No matching ram area found for range: +? [0x00000000000e6b54, 0x0000000000100000) And finally instead of the "Start bios" message from SeaBIOS it's not possible to load the payload to it's address, because.. +Ram areas +? [0x0000000000000000, 0x0000000000001000) Reserved +? [0x0000000000001000, 0x00000000000a0000) RAM +? [0x00000000000c0000, 0x00000000000f0000) RAM +? [0x00000000000f0000, 0x0000000000100000) Reserved ..the F segment has been marked reserved, because this is where the ACPI tables were written to, because the highmem address was not available, because CBMEM failed to initialize. The error isn't really with hardware init I believe, but with calculation, generation and preparation of system description data for the payload and later the operating system. You need to find out why coreboot gets upset with 4G of memory. //Peter ------------------------------ Message: 2 Date: Wed, 22 Feb 2012 10:35:54 +0100 From: Oliver Schinagl To: coreboot at coreboot.org Subject: Re: [coreboot] flash-chip (and compatibles) Message-ID: <4F44B6FA.8070509 at schinagl.nl> Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Having trouble ordering from several webshops in Europe (The only want to send you parts if you order in huge quantities or if you are a company) I've found the following at digikey in the US. http://search.digikey.com/nl/en/products/SST25VF032B-80-4I-S2AF/SST25VF032B-80-4I-S2AF-ND/2297800 http://search.digikey.com/nl/en/products/W25Q64FVSSIG/W25Q64FVSSIG-ND/2815931 I know they are 8-SOIC but have ordered (and received)? 8-SOIC -> 8-DIP pcb's so can easily convert between the sockets. I guess these should work just fine? On 16-02-12 02:44, Peter Stuge wrote: > Oliver Schinagl wrote: >> I was pointed to this one: A25L032-F >> http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085 >> >> (There's also a Q version, which I don't think is what I'd want). > Correct. Q is a WSON package which does not fit at all. Make sure you > buy farnell nr. 1907085 and nothing else. A25L032-F is indeed the > accurate manufacturer's part number, if you order somewhere else. > > >> I haven't found a 64Mbit chip yet, so I hope I could use a linux >> kernel as payload using a 4MB one (the current 32Mbit) > Winbond W25Q64CV > > But Winbond's distributors AVNET and Digi-Key, > > http://www.winbond-usa.com/winbondcms/Application/member/Distributors.aspx?partno=W25Q64CV > > only have SO-8 in stock, and you wanted DIP. You could look for > adapters, but then you must do some soldering. > > http://search.digikey.com/scripts/DkSearch/dksus.dll?site=us&lang=en&v=256&WT.z_supplier_id=256&WT.z_page_type=SP&WT.z_page_sub_type=SS&WT.z_oss_type=View+All&chp=0 > > AVNET only have SO-8 stock in Asia. You'll have to pay import fees > and tax. Digi-Keys f-ing website barfs some idiotic error at me > whenever I try to use it nowadays. > > > You can buy DIP from bios-repair.co.uk, but they only have the older > revision W25Q64BVAIG. For once they don't charge more than AVNET&co > in single quantity. > > http://bios-repair.co.uk/Products/EEPROM/SPI-SerialFlash-EEPROM.html > > Click Winbond, then there's W25Q64BVAIG 64Mb PDIP top left in the > product listing. > > > //Peter > -------------- next part -------------- An HTML attachment was scrubbed... URL: ------------------------------ Message: 3 Date: Wed, 22 Feb 2012 11:35:19 +0100 From: gerrit at coreboot.org To: coreboot at coreboot.org Subject: [coreboot] Patch merged into coreboot/master: 3d3abb2 Remove old AMD fam10 fixme comment Message-ID: Content-Type: text/plain; charset="UTF-8" the following patch was just integrated into master: commit 3d3abb2e9ce3a175c9182b6bc3ad17bc3487735b Author: Marc Jones Date:?? Tue Feb 21 17:53:13 2012 -0700 ??? Remove old AMD fam10 fixme comment ??? ??? The family10 code had a very slow decompress before the cache settings were ??? fixed. This has been fixed for some time. Remove all the old messages from the ??? serial stream. ??? ??? Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 ??? Signed-off-by: Marc Jones Reviewed-By: Patrick Georgi at Wed Feb 22 11:35:17 2012, giving +2 See http://review.coreboot.org/672 for details. -gerrit ------------------------------ Message: 4 Date: Wed, 22 Feb 2012 12:51:38 +0100 From: Bernhard Urban To: coreboot at coreboot.org Cc: Chris Leaver Subject: Re: [coreboot] Coreboot support for ASUS M5 A99X EVO ? Message-ID: Content-Type: text/plain; charset=ISO-8859-1 hi, so finally, I spent some time on porting coreboot to the asus board "m5a99x evo". http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ I was equipped with three DIP chips and decided to use my target machine also for developing. I had also set up a quite complicated configuration for serial debugging, as I didn't own a second machine with a rs232 board. Although the first try (just flash the "m5a88-v" configuration) showed some output :-) ( http://tinyurl.com/89a33m5 ), the build cycle was a pain in the ass. (0) building coreboot (takes some seconds...) (1) flashing the chip (~30seconds, without verifying) (2) reboot (~20sec) (3) starting coreboot and analyse the output (between 1sec and some minutes ;-)) (4) switch chip with vendor bios on it (some seconds) (5) booting vendor bios and linux (35sec + 11sec. yes, the vendor firmware takes three times longer than linux + x11. BOAR ;-)) (6) switch chip again. So I was looking for alternatives. I remembered the ft2232 stuff by Uwe. I had it anyway on my "order it some day"-list, so it was the right time ;-) In the meanwhile, I refit my old machine with a new hdd and a reasoneable graphic card. Luckily, it has also a serial port :-) I was a bit afraid of building a programmer (the ft2232 thingy) as I'm not really the hardware guy. However, the first dump was successful. Writing was working too. I was impressed :-) Thanks to Uwe at this point! So the build cycle is more convenient now: (0) building coreboot (takes longer than on my new machine, but it's okay ;-)) (1) flash the chip with the ft2232 thingy (~30 seconds, without verifying) (2) put the chip onto the mainboard (3) start machine and watch serial output all in all, it take like one minute to test one build. nice! So, now I was able to do some serious coreboot hacking. I started from the "m5a88-v" port. What I did: - Changed the southbridge from "SB800" to "SB900" - Adapted some compile-breaks due to this change. - hardcoded some pci device instead of locating it @ early.c -> ohai ramstage :-) - again, some pci related change/hack (aborting the enumeration earlier). I didn't really understand what I did here, I just figured out it hangs here (could be related with the quirk below). After that -> OHAI SEABIOS! I was very happy ;) However, SeaBIOS itself hang somewhere. In the meanwhile, Kerry pushed RD890 patches, which seemed to be more appropriate for my board (i used RS780 code so far, hence the ugly hacks mentioned above I guess). So I used them, and it felt much cleaner immediately. The payload was still loading -> nice. After that, I investigated a bit what the problem is with SeaBIOS. At this moment, it hanged after printing "Relocating init from 0x000e8450 to 0xcffd57a0 (size 42812)" (see http://tinyurl.com/78evzex ). I looked into the SeaBIOS code and found out, that you can disable relocation. So I did. The result was a bit more confusing. http://tinyurl.com/7uh8xty The output get distorted (which seems not to be deterministically, http://tinyurl.com/6opakzl ) and something issues a soft reset (but not everytime...). Eventually I gave up at this point (had to do other stuff anyway). I guess it is something wrong with RAM initialization as relocation in higher memory regions doesn't work. Also, the graphic card isn't found on the pci bus as the RD890 code inlcudes a quirk which "disable all pcie bridges" aka `sr56x0_rd890_disable_pcie_bridge()'. According to `lspci' (with vendor bios), the graphic card is on bus 1, so this seem reasonably. @Kerry: is there some way to enable it again after "early"? my WIP branch is available here (please tell me if you pull from it, because atm I'm rebasing stuff on it and using `git push -f' to overwrite it...): http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=shortlog;h=refs/heads/WIP full logs (including config and rom images) are available here: http://wien.tomnetworks.com/gitweb/?p=cbimages.git;a=tree Some questions: - What does "CIMX" stands for? I grep'd my #coreboot logs for it. One guy asked that already, but he didn't get an answer :-/ - What's the best/easiest way to verify if RAM init was successful? - I think it would be nice to have an entry on the wiki page for this board. How I get an account? Stefan? :-) I appreciate any comment, I know resources are short :-( anyways, it was fun and exciting so far :-) thanks! regards, bernhard On Wed, Nov 23, 2011 at 10:29 PM, Bernhard Urban wrote: > Hi Chris, > > I reported flashrom compatibility here: > http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html > > Regarding coreboot support: I'll try to port coreboot to this board. I > already have two additional flashchips and at the moment I'm waiting > for a serial port connector. I don't know how long it'll talke to port > it, but don't except anything useful in less than three months, since > I'm new to coreboot (and lazy :-)) > > > Bernhard > > On Sat, Nov 19, 2011 at 6:33 PM, Christopher Huang-Leaver > wrote: >> Hello, >> I noticed earlier versions of this board are fully supported, but not this >> one. >> I have attached the output of, ?lspci, ?flashrom and dmidecode, if that is >> any use to anyone. >> The spec sheet is easy to find by typing ASUS M5 A99X into Google. ?The >> board does have a neat feature of being able to flash the BIOS from within >> the BIOS menu, which I have already used to update it. >> Many thanks >> Chris ------------------------------ _______________________________________________ coreboot mailing list coreboot at coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot End of coreboot Digest, Vol 84, Issue 68 **************************************** -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Fri Feb 24 11:21:49 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Fri, 24 Feb 2012 11:21:49 +0100 Subject: [coreboot] Patch merged into coreboot/master: aafcf93 Ati video: Apply un-written naming rules References: Message-ID: the following patch was just integrated into master: commit aafcf93e1a8d5b51ccdf4e7f4bd62de5a5c81f15 Author: Ky?sti M?lkki Date: Thu Feb 23 13:54:23 2012 +0200 Ati video: Apply un-written naming rules Rename Kconfig to match directory name. Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61 Signed-off-by: Ky?sti M?lkki Reviewed-By: Patrick Georgi at Fri Feb 24 11:21:47 2012, giving +2 See http://review.coreboot.org/678 for details. -gerrit From gerrit at coreboot.org Fri Feb 24 22:08:10 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Fri, 24 Feb 2012 22:08:10 +0100 Subject: [coreboot] Patch set updated for coreboot: 3bbce45 Update xcompile to search for x86_64 toolchain. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673 -gerrit commit 3bbce4576d5a61da1831d0ca749ffcf78d357697 Author: Marc Jones Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones --- util/xcompile/xcompile | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4926394..3930460 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -36,14 +36,19 @@ done GCCPREFIX=invalid XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} -echo '#XGCCPATH='${XGCCPATH} +echo '# XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE -# This should be a loop over all supported architectures -TARCH=i386 +# This loops over all supported architectures in TARCH +TARCH=('i386' 'x86_64') TWIDTH=32 -for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do +for search_for in "${TARCH[@]}"; do + TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-) +done +echo '# TARCH_SEARCH='${TARCH_SEARCH[@]} + +for gccprefixes in "${TARCH_SEARCH[@]}" ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi @@ -63,8 +68,8 @@ for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS=--32 - CFLAGS="-m32 " - LDFLAGS="-b elf32-i386" + CFLAGS="-m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 " + LDFLAGS="-b elf32-i386 -melf_i386" break fi fi From dayscondor at gmail.com Sat Feb 18 19:00:36 2012 From: dayscondor at gmail.com (3days) Date: Sat, 18 Feb 2012 12:00:36 -0600 Subject: [coreboot] one of those please - reports... Message-ID: miro:~/sysinfo# msrtool > msrtool.log msrtool 4091 Detected target K8: AMD K8 Family Unable to detect the current operating system! On Linux, please do 'modprobe msr' and retry. Please send a report or patch to coreboot at coreboot.org. Thanks for your help! miro:~/sysinfo# modprobe msr WARNING: All config files need .conf: /etc/modprobe.d/kqemu, it will be ignored in a future release. WARNING: All config files need .conf: /etc/modprobe.d/OLD_oss-compat, it will be ignored in a future release. WARNING: All config files need .conf: /etc/modprobe.d/OLD_linux-sound-base_noOSS, it will be ignored in a future release. miro:~/sysinfo# msrtool > msrtool.log msrtool 4091 Detected system linux: Linux with /dev/cpu/*/msr Detected target K8: AMD K8 Family Debian Linux OS: Linux miro 3.2.0-1-amd64 #1 SMP Sun Feb 5 15:17:15 UTC 2012 x86_64 GNU/Linux miro:~/sysinfo# cat msrtool.log syntax: msrtool [-hvqrkl] [-c cpu] [-m system] [-t target ...] [-i addr=hi[:]lo] | [-s file] | [-d [:]file] | addr... -h show this help text -v be verbose -q be quiet (overrides -v) -r include [Reserved] values -k list all known systems and targets -l list MSRs and bit fields for current target(s) (-kl for ALL targets!) -c access MSRs on the specified CPU, default=0 -m force a system, e.g: -m linux -t force a target, can be used multiple times, e.g: -t geodelx -t cs5536 -i immediate mode decode hex addr=hi:lo for the target without reading hw value e.g: -i 4c00000f=f2f100ff56960004 -s stream mode read one MSR address per line and append current hw value to the line use the filename - for stdin/stdout using -l -s ignores input and will output all MSRs with values -d diff mode read one address and value per line and compare with current hw value, printing differences to stdout. use the filename - to read from stdin use :file or :- to reverse diff, normally hw values are considered new addr.. direct mode, read and decode values for the given MSR address(es) No mode or address(es) specified! -------------- next part -------------- An HTML attachment was scrubbed... URL: From r.marek at assembler.cz Sat Feb 25 01:00:17 2012 From: r.marek at assembler.cz (Rudolf Marek) Date: Sat, 25 Feb 2012 01:00:17 +0100 Subject: [coreboot] Asus M2V-MX memory init In-Reply-To: References: Message-ID: <4F482491.8090209@assembler.cz> Hi, I think something wrong went with PCI/memory mapping. It looks somehow a hole for PCI is not created. Try setting CONFIG_HW_MEM_HOLE_SIZEK. it should create 0-3GB ram and 1GB hole by default. Also I did not check if VIA chipset will work with memory above 4GB (in fact never owned so much memory :) maybe correct top of memory needs to be present for the chipset. The option above will configure the memory hole which will allow the PCI devices to exists and rest of memory will be remapped above. Again, never played with that but it might work. Thanks Rudolf From gerrit at coreboot.org Sat Feb 25 13:31:49 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sat, 25 Feb 2012 13:31:49 +0100 Subject: [coreboot] New patch to review for coreboot: b2b6c53 AMD southbridge: remove sp5100 References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/679 -gerrit commit b2b6c535a1e8cdd5d39fc1a13267b14ac1fd2edb Author: Ky?sti M?lkki Date: Thu Feb 23 18:42:55 2012 +0200 AMD southbridge: remove sp5100 Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Ky?sti M?lkki --- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 +- src/mainboard/supermicro/h8scm_fam10/devicetree.cb | 4 +- src/southbridge/amd/Makefile.inc | 1 - src/southbridge/amd/sb700/Kconfig | 19 +++++++---- src/southbridge/amd/sb700/early_setup.c | 8 ++-- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sata.c | 5 +-- src/southbridge/amd/sb700/sb700.c | 4 +- src/southbridge/amd/sp5100/chip.h | 33 -------------------- 9 files changed, 24 insertions(+), 56 deletions(-) diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index cbd3119..844763e 100755 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -8,14 +8,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 select SUPERIO_WINBOND_W83627HF select SUPERIO_NUVOTON_WPCM450 select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index c6ccecb..9aa4406 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -36,7 +36,7 @@ chip northbridge/amd/amdfam10/root_complex register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 register "port_enable" = "0x1ffc" end - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB @@ -92,7 +92,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sp5100 + end #southbridge/amd/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 54245f2..65e4729 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -8,7 +8,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 05f7d09..924e2df 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -19,29 +19,34 @@ config SOUTHBRIDGE_AMD_SB700 bool + +if SOUTHBRIDGE_AMD_SB700 + +config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET -config SOUTHBRIDGE_AMD_SP5100 +# Set for southbridge SP5100 which also uses SB700 driver +config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool - select IOAPIC - select HAVE_USBDEBUG + default n config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/sb700/bootblock.c" - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config EHCI_BAR hex - default 0xfef00000 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0xe0 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) + default 0xe0 + +endif # SOUTHBRIDGE_AMD_SB700 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 1f46da2..2dc84d8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -154,7 +154,7 @@ void sb7xx_51xx_lpc_init(void) reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 post_code(0x66); dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); @@ -168,7 +168,7 @@ void sb7xx_51xx_lpc_init(void) // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 #if CONFIG_TTYS0_BASE == 0x2f8 reg8 |= 1 << 7; #endif @@ -358,7 +358,7 @@ static void sb700_devices_por_init(void) { device_t dev; u8 byte; -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; #endif @@ -494,7 +494,7 @@ static void sb700_devices_por_init(void) /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ pci_write_config8(dev, 0x50, 0x01); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* SP5100 default SATA mode is RAID5 MODE */ dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); /* Set SATA Operation Mode, Set to IDE mode */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 3e596c2..5dd7d69 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 58b72ad..bdbb08a 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -86,9 +86,6 @@ static void sata_init(struct device *dev) u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; - struct southbridge_ati_sb700_config *conf; - conf = dev->chip_info; - device_t sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -189,7 +186,7 @@ static void sata_init(struct device *dev) byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* Master Latency Timer */ pci_write_config32(dev, 0xC, 0x00004000); #endif diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 845c82c..304bd07 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -226,8 +226,8 @@ void sb7xx_51xx_enable(device_t dev) } } -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 -struct chip_operations southbridge_amd_sp5100_ops = { +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +struct chip_operations southbridge_amd_sb700_ops = { CHIP_NAME("ATI SP5100") .enable_dev = sb7xx_51xx_enable, }; diff --git a/src/southbridge/amd/sp5100/chip.h b/src/southbridge/amd/sp5100/chip.h deleted file mode 100644 index 569e511..0000000 --- a/src/southbridge/amd/sp5100/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SP5100_CHIP_H -#define SP5100_CHIP_H - -struct southbridge_amd_sp5100_config -{ - u32 ide0_enable : 1; - u32 sata0_enable : 1; - u32 boot_switch_sata_ide : 1; - u32 hda_viddid; -}; -struct chip_operations; -extern struct chip_operations southbridge_amd_sp5100_ops; - -#endif /* SP5100_CHIP_H */ From gerrit at coreboot.org Sat Feb 25 15:31:24 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 25 Feb 2012 15:31:24 +0100 Subject: [coreboot] New patch to review for coreboot: a4cc213 Fix lint test for build directories References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/680 -gerrit commit a4cc21352ce28579466fe338dc4ee6ef3b4711e9 Author: Patrick Georgi Date: Sat Feb 25 15:33:43 2012 +0100 Fix lint test for build directories config files are rename()d, which fails across filesystem borders. So force temporary config files in current directory. Change-Id: I583c2ab9a822a6f99f838778aa17ffd2d47eaed1 Signed-off-by: Patrick Georgi --- util/lint/lint-002-build-dir-handling | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/lint/lint-002-build-dir-handling b/util/lint/lint-002-build-dir-handling index f10db17..c4f57d6 100755 --- a/util/lint/lint-002-build-dir-handling +++ b/util/lint/lint-002-build-dir-handling @@ -47,7 +47,7 @@ if [ "$MAKE" = "" ]; then fi # prepare a config to use -TMPCONFIG=`mktemp` +TMPCONFIG=`mktemp .tmpconfig.XXXXXX` rm -f $TMPCONFIG $MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null From gerrit at coreboot.org Sat Feb 25 19:50:27 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 25 Feb 2012 19:50:27 +0100 Subject: [coreboot] New patch to review for coreboot: c0f82a7 lint: create two classes of tests, stable and dev References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/681 -gerrit commit c0f82a75b480ad90d9b4eff48a1ebf08ef592aec Author: Patrick Georgi Date: Sat Feb 25 19:42:59 2012 +0100 lint: create two classes of tests, stable and dev We have tests that pass (and should be enforced soonish) and those that don't pass yet (and thus shouldn't break the build). The plan is simple: As soon as a test passes, it's marked stable so things remain that way. "make lint" runs all tests, "make lint-stable" runs only those that shouldn't fail. Change-Id: Iaa85d71141606d9756e29b37c7a34c2a15e573ac Signed-off-by: Patrick Georgi --- Makefile.inc | 6 +- util/lint/lint-002-build-dir-handling | 63 -------------------------- util/lint/lint-003-whitespace | 39 ---------------- util/lint/lint-stable-002-build-dir-handling | 63 ++++++++++++++++++++++++++ util/lint/lint-stable-003-whitespace | 39 ++++++++++++++++ 5 files changed, 105 insertions(+), 105 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index e12cc92..0f040e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -34,7 +34,7 @@ coreboot: $(obj)/coreboot.rom ####################################################################### # our phony targets -PHONY+= clean-abuild coreboot +PHONY+= clean-abuild coreboot lint lint-stable ####################################################################### # root source directories of coreboot @@ -218,9 +218,9 @@ printcrt0s: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF -lint: +lint lint-stable: FAILED=0; LINTLOG=`mktemp`; \ - for script in util/lint/lint-*; do \ + for script in util/lint/$@-*; do \ echo; echo `basename $$script`; \ grep "^# DESCR:" $$script | sed "s,.*DESCR: *,," ; \ echo ========; \ diff --git a/util/lint/lint-002-build-dir-handling b/util/lint/lint-002-build-dir-handling deleted file mode 100755 index c4f57d6..0000000 --- a/util/lint/lint-002-build-dir-handling +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Patrick Georgi -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# DESCR: Check that build directories can be chosen freely - -# $1: command to test for GNU make -search_make() { -if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi -} - -# if $1 and $2 differ, exit with failure -compare_output() { -if ! [ "$1" = "$2" ]; then - echo \'$1\' should be \'$2\' - exit 1 -fi -} - -# $1: object directory -run_printall() { -$MAKE CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s, ,\n,g" -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," -} - -# find GNU make -search_make make -search_make gmake -search_make gnumake - -if [ "$MAKE" = "" ]; then - echo Could not identify GNU make - exit 1 -fi - -# prepare a config to use -TMPCONFIG=`mktemp .tmpconfig.XXXXXX` -rm -f $TMPCONFIG -$MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null - -# look up parent directory -PARENTDIR=`dirname $PWD` - -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" - -rm -f $TMPCONFIG - diff --git a/util/lint/lint-003-whitespace b/util/lint/lint-003-whitespace deleted file mode 100755 index fe305bf..0000000 --- a/util/lint/lint-003-whitespace +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Patrick Georgi -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# DESCR: Check for superfluous whitespace in the tree - -LC_ALL=C export LC_ALL -find src util -name .svn -type d -prune -o \ - -name .git -type d -prune -o \ - -name README -prune -o \ - -name LICENSE -prune -o \ - -name TODO -prune -o \ - -name COPYING -prune -o \ - -name \*.txt -prune -o \ - -name microcode-\*.h -prune -o \ - -name \*.?_shipped -prune -o \ - -name \*.[18] -prune -o \ - -name kconfig -type d -prune -o \ - -name romcc -type d -prune -o \ - -name crossgcc -type d -prune -o \ - -name vendorcode -type d -prune -o \ - -type f -exec \ - grep -l "[[:space:]][[:space:]]*$" {} + | \ - sed -e "s,^.*$,File & has lines ending with whitespace.," - diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling new file mode 100755 index 0000000..c4f57d6 --- /dev/null +++ b/util/lint/lint-stable-002-build-dir-handling @@ -0,0 +1,63 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Patrick Georgi +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# DESCR: Check that build directories can be chosen freely + +# $1: command to test for GNU make +search_make() { +if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi +} + +# if $1 and $2 differ, exit with failure +compare_output() { +if ! [ "$1" = "$2" ]; then + echo \'$1\' should be \'$2\' + exit 1 +fi +} + +# $1: object directory +run_printall() { +$MAKE CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s, ,\n,g" -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +} + +# find GNU make +search_make make +search_make gmake +search_make gnumake + +if [ "$MAKE" = "" ]; then + echo Could not identify GNU make + exit 1 +fi + +# prepare a config to use +TMPCONFIG=`mktemp .tmpconfig.XXXXXX` +rm -f $TMPCONFIG +$MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null + +# look up parent directory +PARENTDIR=`dirname $PWD` + +compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" + +rm -f $TMPCONFIG + diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace new file mode 100755 index 0000000..fe305bf --- /dev/null +++ b/util/lint/lint-stable-003-whitespace @@ -0,0 +1,39 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Patrick Georgi +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# DESCR: Check for superfluous whitespace in the tree + +LC_ALL=C export LC_ALL +find src util -name .svn -type d -prune -o \ + -name .git -type d -prune -o \ + -name README -prune -o \ + -name LICENSE -prune -o \ + -name TODO -prune -o \ + -name COPYING -prune -o \ + -name \*.txt -prune -o \ + -name microcode-\*.h -prune -o \ + -name \*.?_shipped -prune -o \ + -name \*.[18] -prune -o \ + -name kconfig -type d -prune -o \ + -name romcc -type d -prune -o \ + -name crossgcc -type d -prune -o \ + -name vendorcode -type d -prune -o \ + -type f -exec \ + grep -l "[[:space:]][[:space:]]*$" {} + | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," + From gerrit at coreboot.org Sat Feb 25 19:50:27 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 25 Feb 2012 19:50:27 +0100 Subject: [coreboot] New patch to review for coreboot: 5326f5c gitconfig: Add lint-stable as pre-commit hook References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/682 -gerrit commit 5326f5c7e6a9d56bc0f030c81651050d6d280150 Author: Patrick Georgi Date: Sat Feb 25 19:52:45 2012 +0100 gitconfig: Add lint-stable as pre-commit hook When configuring the tree with "make gitconfig", a pre-commit hook is installed that runs the stable lint tests. If any of these fail, the log is visible (on stdout) and the commit is aborted. Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e Signed-off-by: Patrick Georgi --- Makefile.inc | 2 +- util/gitconfig/pre-commit | 2 ++ 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0f040e9..2f61a45 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -239,7 +239,7 @@ lint lint-stable: rm -f $$LINTLOG gitconfig: - if ! [ -x .git/hooks/commit-msg ]; then cp util/gitconfig/commit-msg .git/hooks/commit-msg; chmod +x .git/hooks/commit-msg; fi + for hook in commit-msg pre-commit; do if ! [ -x .git/hooks/$$hook ]; then cp util/gitconfig/$$hook .git/hooks/$$hook; chmod +x .git/hooks/$$hook; fi; done (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email at example.com\n'; exit 1) crossgcc: clean-for-update diff --git a/util/gitconfig/pre-commit b/util/gitconfig/pre-commit new file mode 100755 index 0000000..8ab3e56 --- /dev/null +++ b/util/gitconfig/pre-commit @@ -0,0 +1,2 @@ +#!/bin/sh +exec make lint-stable From gerrit at coreboot.org Sat Feb 25 21:24:47 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 25 Feb 2012 21:24:47 +0100 Subject: [coreboot] Patch set updated for coreboot: cf90fa4 Unify IO APIC address specification References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/677 -gerrit commit cf90fa465617a92de7cf65d61f2a395fd7afd8c0 Author: Patrick Georgi Date: Thu Feb 16 18:54:37 2012 +0100 Unify IO APIC address specification Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi --- src/mainboard/amd/torpedo/platform_cfg.h | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/northbridge/intel/i945/acpi/hostbridge.asl | 2 +- src/northbridge/intel/sch/acpi/hostbridge.asl | 2 +- src/southbridge/amd/cimx/sb700/lpc.c | 5 +++-- src/southbridge/amd/cimx/sb800/lpc.c | 5 +++-- src/southbridge/amd/cimx/sb900/lpc.c | 5 +++-- src/southbridge/amd/sb800/lpc.c | 4 ++-- src/southbridge/amd/sb800/sm.c | 8 +++----- src/southbridge/intel/sch/lpc.c | 4 ++-- 10 files changed, 20 insertions(+), 19 deletions(-) diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index d97d034..cf31c6a 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -137,7 +137,7 @@ * @section WatchDogTimerBase */ // #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 +// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR // #endif /** diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 953f16a..87de022 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -34,7 +34,7 @@ void *smp_write_config_table(void *v) smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index a76d8e2..b5f86ae 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -211,7 +211,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_BASE,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl index 7e92a0e..17a95a4 100644 --- a/src/northbridge/intel/sch/acpi/hostbridge.asl +++ b/src/northbridge/intel/sch/acpi/hostbridge.asl @@ -211,7 +211,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_ADDR,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index e43193a..7157a55 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -21,6 +21,7 @@ #include "lpc.h" #include #include +#include #include /* printk */ #include @@ -61,8 +62,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..856b8b3 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -19,6 +19,7 @@ #include #include +#include #include "lpc.h" @@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 48bfe36..9873d37 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -20,6 +20,7 @@ #include #include "lpc.h" #include /* printk */ +#include void lpc_read_resources(device_t dev) @@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 6b72a62..4e2031f 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -91,8 +91,8 @@ static void sb800_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - //res = new_resource(dev, 3); /* IOAPIC */ - //res->base = 0xfec00000; + //res = new_resource(dev, 3); + //res->base = IO_APIC_ADDR; //res->size = 0x00001000; //res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 9347c42..50a8f0b 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -84,16 +84,14 @@ static void sm_init(device_t dev) { u8 byte; - u32 ioapic_base; printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = 0xFEC00000;//pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. * We need to check out why and change back. */ - clear_ioapic(ioapic_base); - //setup_ioapic(ioapic_base, 0); + clear_ioapic(IO_APIC_ADDR); + //setup_ioapic(IO_APIC_ADDR, 0); /* enable serial irq */ byte = pm_ioread(0x54); @@ -277,7 +275,7 @@ static void sb800_sm_read_resources(device_t dev) /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFEFFFFFUL; /* res->base + res->size -1; */ res->align = 8; diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index ab180bb..7c203bf 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -164,8 +164,8 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } From gerrit at coreboot.org Sat Feb 25 21:24:48 2012 From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de)) Date: Sat, 25 Feb 2012 21:24:48 +0100 Subject: [coreboot] Patch set updated for coreboot: a437df3 Unify Local APIC address definitions References: Message-ID: Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/676 -gerrit commit a437df37ea4d4baf1a4d7e5f42cc59c37774ee66 Author: Patrick Georgi Date: Thu Feb 16 18:43:25 2012 +0100 Unify Local APIC address definitions We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi --- Makefile.inc | 2 +- src/arch/x86/boot/acpi.c | 3 +-- src/arch/x86/include/arch/ioapic.h | 4 +++- src/arch/x86/include/arch/smp/mpspec.h | 5 ++--- src/include/cpu/x86/lapic_def.h | 3 ++- src/mainboard/advansus/a785e-i/mptable.c | 2 +- src/mainboard/amd/bimini_fam10/mptable.c | 2 +- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dinar/mptable.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/mptable.c | 2 +- .../amd/serengeti_cheetah/acpi/amd8111_isa.asl | 7 +++++-- src/mainboard/amd/serengeti_cheetah/mptable.c | 2 +- .../serengeti_cheetah_fam10/acpi/amd8111_isa.asl | 7 +++++-- .../amd/serengeti_cheetah_fam10/mptable.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/arima/hdama/mptable.c | 2 +- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/a8v-e_deluxe/mptable.c | 2 +- src/mainboard/asus/a8v-e_se/mptable.c | 2 +- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2v/mptable.c | 2 +- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/mptable.c | 2 +- src/mainboard/asus/p2b-d/mptable.c | 2 +- src/mainboard/asus/p2b-ds/mptable.c | 2 +- src/mainboard/avalue/eax-785e/mptable.c | 2 +- src/mainboard/broadcom/blast/mptable.c | 2 +- src/mainboard/dell/s1850/mptable.c | 2 +- src/mainboard/emulation/qemu-x86/northbridge.c | 3 ++- src/mainboard/getac/p470/mptable.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/hp/dl145_g1/mptable.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +- src/mainboard/ibase/mb899/mptable.c | 2 +- src/mainboard/ibm/e325/mptable.c | 2 +- src/mainboard/ibm/e326/mptable.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/intel/d945gclf/mptable.c | 2 +- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/jarrell/mptable.c | 2 +- src/mainboard/intel/mtarvon/mptable.c | 2 +- src/mainboard/intel/truxton/mptable.c | 2 +- src/mainboard/intel/xe7501devkit/mptable.c | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl | 7 +++++-- src/mainboard/iwill/dk8_htx/mptable.c | 2 +- src/mainboard/iwill/dk8s2/mptable.c | 2 +- src/mainboard/iwill/dk8x/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/986lcd-m/mptable.c | 2 +- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/lenovo/t60/mptable.c | 2 +- src/mainboard/lenovo/x60/mptable.c | 2 +- src/mainboard/msi/ms7135/mptable.c | 2 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms9185/mptable.c | 2 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/mptable.c | 2 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 2 +- src/mainboard/roda/rk886ex/mptable.c | 2 +- src/mainboard/siemens/sitemp_g1p1/dsdt.asl | 6 ++++-- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/mptable.c | 2 +- src/mainboard/supermicro/x6dhe_g/mptable.c | 2 +- src/mainboard/supermicro/x6dhe_g2/mptable.c | 2 +- src/mainboard/supermicro/x6dhr_ig/mptable.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 2 +- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/tyan/s2735/mptable.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 2 +- src/mainboard/tyan/s2875/mptable.c | 2 +- src/mainboard/tyan/s2880/mptable.c | 2 +- src/mainboard/tyan/s2881/mptable.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 2 +- src/mainboard/tyan/s2885/mptable.c | 2 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 2 +- src/mainboard/tyan/s4882/mptable.c | 2 +- src/mainboard/via/epia-n/mainboard.c | 3 ++- src/mainboard/via/epia-n/mptable.c | 2 +- src/mainboard/via/pc2500e/mptable.c | 2 +- src/mainboard/via/vt8454c/mptable.c | 2 +- 110 files changed, 131 insertions(+), 117 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index e12cc92..24f3017 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -69,7 +69,7 @@ romstage-c-deps:=$$(OPTION_TABLE_H) define ramstage-objs_asl_template $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" - $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl + $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-y)/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$@)).asl mv $$(basename $$@).hex $$(basename $$@).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index f1be034..168933a 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -31,6 +31,7 @@ #include #include #include +#include u8 acpi_checksum(u8 *table, u32 length) { @@ -188,8 +189,6 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, void acpi_create_madt(acpi_madt_t *madt) { -#define LOCAL_APIC_ADDR 0xfee00000ULL - acpi_header_t *header = &(madt->header); unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t); diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 623f617..5d7e196 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -20,7 +20,7 @@ #ifndef __I386_ARCH_IOAPIC_H #define __I386_ARCH_IOAPIC_H -#define IO_APIC_ADDR 0xfec00000UL +#define IO_APIC_ADDR 0xfec00000 #define IO_APIC_INTERRUPTS 24 #define ALL (0xff << 24) @@ -38,7 +38,9 @@ #define SMI (2 << 8) #define INT (1 << 8) +#ifndef __ACPI__ void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); +#endif #endif diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 2eb1813..e5e6195 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -2,6 +2,8 @@ #define __ASM_MPSPEC_H #include +#include + /* * Structure definitions for SMP machines following the * Intel Multiprocessing Specification 1.1 and 1.4. @@ -229,9 +231,6 @@ struct mp_exten_compatibility_address_space { */ } __attribute__((packed)); -/* Default local apic addr */ -#define LAPIC_ADDR 0xFEE00000 - void mptable_init(struct mp_config_table *mc, u32 lapic_addr); void *smp_next_mpc_entry(struct mp_config_table *mc); diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index 6035273..f96b53b 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -6,7 +6,8 @@ #define LAPIC_BASE_MSR_ENABLE (1 << 11) #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 -#define LAPIC_DEFAULT_BASE 0xfee00000 +#define LOCAL_APIC_ADDR 0xfee00000 +#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR #define LAPIC_ID 0x020 #define LAPIC_LVR 0x030 diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 6504049..8643320 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c index 2ab3f24..ae81411 100644 --- a/src/mainboard/amd/bimini_fam10/mptable.c +++ b/src/mainboard/amd/bimini_fam10/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 901591a..cf98ae3 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index b43080d..4938be0 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -44,7 +44,7 @@ static void *smp_write_config_table(void *v) u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index b339348..b5a507f 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index f79a579..dabd2ed 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index b1a658b..c56952e 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 18a7707..61ddef1 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 901591a..cf98ae3 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl index 0f7efc9..56c0a16 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl @@ -1,3 +1,6 @@ +#include +#include + /* * Copyright 2005 AMD */ @@ -125,9 +128,9 @@ { Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index ebd4cbc..4214408 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl index f00069f..3b79453 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl @@ -17,6 +17,9 @@ // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA // +#include +#include + //AMD8111 isa Device (ISA) @@ -141,9 +144,9 @@ { Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index d527f9c..e90b348 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 5242f69..99004b3 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 97db2b9..936a417 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); /*Inagua used dure core cpu with one die */ diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 5242f69..99004b3 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 466ba88..f67327e 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 95b1271..c0ca550 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index de9d7f4..7e8c947 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "ASROCK ", 8); smp_write_processors(mc); diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index 349ae74..9defdb5 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c index 999dd6c..eb7790f 100644 --- a/src/mainboard/asus/a8v-e_deluxe/mptable.c +++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c index 999dd6c..eb7790f 100644 --- a/src/mainboard/asus/a8v-e_se/mptable.c +++ b/src/mainboard/asus/a8v-e_se/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 673dfbe..48eee71 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 29b9d07..680dfa7 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c index 5dc340a..e6e600a 100644 --- a/src/mainboard/asus/m2v/mptable.c +++ b/src/mainboard/asus/m2v/mptable.c @@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v) mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index 516b915..ac8ed5e 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c index 43f3a85..4eed581 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b-d/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c index 153c62c..5333418 100644 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b-ds/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 021f635..6f541a0 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index b747d2e..5a1bf28 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c index a71dab0..0c7562c 100644 --- a/src/mainboard/dell/s1850/mptable.c +++ b/src/mainboard/dell/s1850/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 3f22437..b961e8b 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -80,7 +81,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) /* Reserve space for the LAPIC. There's one in every processor, but * the space only needs to be reserved once, so we do it here. */ res = new_resource(dev, 3); - res->base = 0xfee00000UL; + res->base = LOCAL_APIC_ADDR; res->size = 0x10000UL; res->limit = 0xffffffffUL; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 5954c97..9b59bb4 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index b52cda9..914b25a 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 5aa7e61..f493514 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index e33f681..35dedde 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 466b7fc..609432a 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index c246721..00234a3 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 0ff1896..1baf728 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 6431f32..7d1b8f3 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index e81bf8f..b963a0c 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 66423e5..a26fbde 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index ab537cb..b0360bf 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 8571864..809feec 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index b665703..6662329 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c index 0c025f0..364d077 100644 --- a/src/mainboard/intel/mtarvon/mptable.c +++ b/src/mainboard/intel/mtarvon/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index 506a1d0..0cc8f6b 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index 99fd5af..cc7eda5 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -122,7 +122,7 @@ static void *smp_write_config_table(void* v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index bf94b8c..953f16a 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -29,7 +29,7 @@ void *smp_write_config_table(void *v) int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl index 0f7efc9..56c0a16 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl @@ -1,3 +1,6 @@ +#include +#include + /* * Copyright 2005 AMD */ @@ -125,9 +128,9 @@ { Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index fd53bd7..3977673 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c index d78ce20..f22fd9d 100644 --- a/src/mainboard/iwill/dk8s2/mptable.c +++ b/src/mainboard/iwill/dk8s2/mptable.c @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c index d78ce20..f22fd9d 100644 --- a/src/mainboard/iwill/dk8x/mptable.c +++ b/src/mainboard/iwill/dk8x/mptable.c @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 11b4357..b8caa23 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index ab63b45..03f7370 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 21a0d05..4ffba6f 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index a74aca8..312e30d 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 0ce10ed..f21e76f 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c index 4262af1..7d7ba53 100644 --- a/src/mainboard/msi/ms7135/mptable.c +++ b/src/mainboard/msi/ms7135/mptable.c @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &bus_isa); diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index bef81ef..41f5bf7 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index 0f97dca..fe65d7d 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index baba6b5..0559844 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 5e45380..35d1172 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c index 4017fce..8ee6e15 100644 --- a/src/mainboard/newisys/khepri/mptable.c +++ b/src/mainboard/newisys/khepri/mptable.c @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index 5d13701..b7e1a88 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index 5954c97..9b59bb4 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 8ad0f82..e03e665 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -18,6 +18,8 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) { @@ -418,8 +420,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02) If (PCIF) { - Store (0xFEC00000, MB01) - Store (0xFEE00000, MB02) + Store (IO_APIC_ADDR, MB01) + Store (LOCAL_APIC_ADDR, MB02) Store (0x1000, ML01) Store (0x1000, ML02) } diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index ba2c1e4..dc98382 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index c00c4b8..1ba1dcf 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index cdbe7d6..93fea87 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 734fac9..f54e18f 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index f2ee7a8..6ed5840 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 92771bd..61a7bd4 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v) u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 2e7c4af..e6d4280 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index b2c1c92..0c75d1a 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index acd719d..6ba5309 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -13,7 +13,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index f5f4100..4504d34 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index e39a700..087bb9e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index 143138d..5d0a08d 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index a374f5c..b6c94d3 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 21a0d05..4ffba6f 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 21a0d05..4ffba6f 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9612a4c..9073728 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -12,7 +12,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 5144cec..08027f4 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); { diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 67de027..c3765f2 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index e0058fa..2d34c8b 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 80b35bc..7df5e87 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index b028abb..47c39a7 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); { diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index fc5109f..26081c7 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index 12d6e78..cb49434 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 7af319a..882ac69 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index a383cb2..20fa92c 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 49720dc..9fe7ab7 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index 393362b..8b5f365 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index 6646718..9111a63 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index c1da3e5..bca26a0 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c index 9227f0a..6e11a00 100644 --- a/src/mainboard/via/epia-n/mainboard.c +++ b/src/mainboard/via/epia-n/mainboard.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "chip.h" int add_mainboard_resources(struct lb_memory *mem) @@ -33,7 +34,7 @@ int add_mainboard_resources(struct lb_memory *mem) lb_add_memory_range(mem, LB_MEM_RESERVED, IO_APIC_ADDR, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, - 0xFEE00000ULL, 0x1000); + LOCAL_APIC_ADDR, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, 0xFFFF0000ULL, 0x10000); #endif diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c index c7c554a..de25d0e 100644 --- a/src/mainboard/via/epia-n/mptable.c +++ b/src/mainboard/via/epia-n/mptable.c @@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c index 939f21d..fa69bbe 100644 --- a/src/mainboard/via/pc2500e/mptable.c +++ b/src/mainboard/via/pc2500e/mptable.c @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c index 575237f..fc9cb99 100644 --- a/src/mainboard/via/vt8454c/mptable.c +++ b/src/mainboard/via/vt8454c/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); From gerrit at coreboot.org Sat Feb 25 23:57:15 2012 From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz)) Date: Sat, 25 Feb 2012 23:57:15 +0100 Subject: [coreboot] New patch to review for coreboot: 904a808 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu. References: Message-ID: Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/683 -gerrit commit 904a8089cf7017480da09c0c1b1754af404e08e3 Author: Rudolf Marek Date: Sat Feb 25 23:51:12 2012 +0100 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek --- src/arch/x86/boot/smbios.c | 49 ++++++++++++++++++++++++-------------- src/arch/x86/include/arch/cpu.h | 29 +++++++++++++++++++++++ src/arch/x86/lib/cpu.c | 29 ----------------------- 3 files changed, 60 insertions(+), 47 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index e5156d9..7e2729c 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -76,34 +76,41 @@ int smbios_string_table_len(char *start) static int smbios_cpu_vendor(char *start) { - char tmp[13]; + char tmp[13] = "Unknown"; u32 *_tmp = (u32 *)tmp; - struct cpuid_result res = cpuid(0); + struct cpuid_result res; - _tmp[0] = res.ebx; - _tmp[1] = res.edx; - _tmp[2] = res.ecx; - tmp[12] = '\0'; - return smbios_add_string(start, tmp); + if (have_cpuid_p()) { + res = cpuid(0); + _tmp[0] = res.ebx; + _tmp[1] = res.edx; + _tmp[2] = res.ecx; + tmp[12] = '\0'; + } + return smbios_add_string(start, tmp); } static int smbios_processor_name(char *start) { - char tmp[49]; + char tmp[49] = "Unknown Processor Name"; u32 *_tmp = (u32 *)tmp; struct cpuid_result res; int i; - for (i = 0; i < 3; i++) { - res = cpuid(0x80000002 + i); - _tmp[i * 4 + 0] = res.eax; - _tmp[i * 4 + 1] = res.ebx; - _tmp[i * 4 + 2] = res.ecx; - _tmp[i * 4 + 3] = res.edx; + if (have_cpuid_p()) { + res = cpuid(0x80000000); + if (res.eax > 0x80000004) { + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + _tmp[i * 4 + 0] = res.eax; + _tmp[i * 4 + 1] = res.ebx; + _tmp[i * 4 + 2] = res.ecx; + _tmp[i * 4 + 3] = res.edx; + } + tmp[48] = 0; + } } - - tmp[48] = 0; return smbios_add_string(start, tmp); } @@ -184,7 +191,13 @@ static int smbios_write_type4(unsigned long *current, int handle) struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); - res = cpuid(1); + /* Provide sane defaults even for CPU without CPUID */ + res.eax = res.edx = 0; + res.ebx = 0x10000; + + if (have_cpuid_p()) { + res = cpuid(1); + } memset(t, 0, sizeof(struct smbios_type4)); t->type = SMBIOS_PROCESSOR_INFORMATION; @@ -194,7 +207,7 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); t->processor_version = smbios_processor_name(t->eos); - t->processor_family = 0x0c; + t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ t->processor_upgrade = 0x06; t->core_count = (res.ebx >> 16) & 0xff; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 85357d7..4f395ce 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -29,6 +29,35 @@ struct cpuid_result { uint32_t edx; }; +/* Standard macro to see if a specific flag is changeable */ +static inline int flag_is_changeable_p(uint32_t flag) +{ + uint32_t f1, f2; + + asm( + "pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r" (f1), "=&r" (f2) + : "ir" (flag)); + return ((f1^f2) & flag) != 0; +} + + +/* Probe for the CPUID instruction */ +static int have_cpuid_p(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + + /* * Generic CPUID function */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index ada57e2..60296be 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,35 +9,6 @@ #include #include #include - -/* Standard macro to see if a specific flag is changeable */ -static inline int flag_is_changeable_p(uint32_t flag) -{ - uint32_t f1, f2; - - asm( - "pushfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "movl %0,%1\n\t" - "xorl %2,%0\n\t" - "pushl %0\n\t" - "popfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "popfl\n\t" - : "=&r" (f1), "=&r" (f2) - : "ir" (flag)); - return ((f1^f2) & flag) != 0; -} - - -/* Probe for the CPUID instruction */ -static int have_cpuid_p(void) -{ - return flag_is_changeable_p(X86_EFLAGS_ID); -} - /* * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected * by the fact that they preserve the flags across the division of 5/2. From juergen.trapp at alice.de Sun Feb 26 00:41:11 2012 From: juergen.trapp at alice.de (=?iso-8859-1?Q?J=FCrgen_Trapp?=) Date: Sun, 26 Feb 2012 00:41:11 +0100 Subject: [coreboot] Will coreboot work on my machine, HP XW9300? Message-ID: <5B9632B43753F047BE43BF138DCF777401F3B072@HSNMST02V05.hsn.alice-dsl.net> The Board is a OEM by HP, but the builder is TYAN with the board name S2895. 1.) system: HP XW9300 board vendor: HP (Tyan) board name: S2895 CPU: 2x AMD 275 northbridge: NVIDIA 2200 Prof. southbridge: NVIDIA 2050 Prof 2.)-+-[0000:80]-+-00.0 nVidia Corporation CK804 Memory Controller [10de:005e] | +-01.0 nVidia Corporation CK804 Memory Controller [10de:00d3] | \-0e.0-[81]----00.0 nVidia Corporation NV41 [Quadro FX 3450/4000 SDI] [10de:00cd] +-[0000:40]-+-01.0-[41]-- | +-01.1 Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC [1022:7451] | +-02.0-[61]--+-06.0 LSI Logic / Symbios Logic 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI [1000:0030] | | \-06.1 LSI Logic / Symbios Logic 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI [1000:0030] | \-02.1 Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC [1022:7451] \-[0000:00]-+-00.0 nVidia Corporation CK804 Memory Controller [10de:005e] +-01.0 nVidia Corporation CK804 ISA Bridge [10de:0051] +-01.1 nVidia Corporation CK804 SMBus [10de:0052] +-02.0 nVidia Corporation CK804 USB Controller [10de:005a] +-02.1 nVidia Corporation CK804 USB Controller [10de:005b] +-04.0 nVidia Corporation CK804 AC'97 Audio Controller [10de:0059] +-06.0 nVidia Corporation CK804 IDE [10de:0053] +-07.0 nVidia Corporation CK804 Serial ATA Controller [10de:0054] +-08.0 nVidia Corporation CK804 Serial ATA Controller [10de:0055] +-09.0-[05]----05.0 Texas Instruments TSB43AB22A IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx] [104c:8023] +-0a.0 nVidia Corporation CK804 Ethernet Controller [10de:0057] +-0e.0-[0a]----00.0 nVidia Corporation NV41 [Quadro FX 3450/4000 SDI] [10de:00cd] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] +-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] +-19.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-19.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-19.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] \-19.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] 3.)Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC LPC47B397 (id=0x6f, rev=0x01) at 0x2e No dump available for this Super I/O 4.)flashrom v0.9.5-r1507 on Linux 3.0.0-12-generic (i686), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 4001 usecs, 729M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 0 us, 10000 myus = 8001 us, 16004 myus = 16001 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP xw9300 Workstation" DMI string system-version: " " DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "09C4h" DMI string baseboard-version: "Not Specified" DMI string chassis-type: "Mini Tower" Found chipset "NVIDIA CK804" with PCI ID 10de:0051. Enabling flash write... OK. WARNING: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom at flashrom.org with 'CHIPSET: your board name' in the subject line. The following protocols are supported: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x20, id2 0x20 Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x20, id2 0x20 Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x20, id2 0x20 Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x20, id2 0x20 Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0x65, id2 0xd0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x20, id2 0x20, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x48, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xe4, id2 0xb9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Found SST flash chip "SST49LF080A" (1024 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Thank you for help. -------------- next part -------------- An HTML attachment was scrubbed... URL: From jakllsch at kollasch.net Sun Feb 26 01:53:47 2012 From: jakllsch at kollasch.net (Jonathan A. Kollasch) Date: Sat, 25 Feb 2012 18:53:47 -0600 Subject: [coreboot] Will coreboot work on my machine, HP XW9300? In-Reply-To: <5B9632B43753F047BE43BF138DCF777401F3B072@HSNMST02V05.hsn.alice-dsl.net> References: <5B9632B43753F047BE43BF138DCF777401F3B072@HSNMST02V05.hsn.alice-dsl.net> Message-ID: <20120226005335.GF20317@tazenda.kollasch.net> On Sun, Feb 26, 2012 at 12:41:11AM +0100, J?rgen Trapp wrote: > The Board is a OEM by HP, but the builder is TYAN with the board name S2895. Unlike the Tyan version of the board, I believe the HP version has a soldered-on ROM chip. Otherwise, there's a fairly good chance it could work. Jonathan Kollasch From juergen.trapp at alice.de Sun Feb 26 12:59:16 2012 From: juergen.trapp at alice.de (=?iso-8859-1?Q?J=FCrgen_Trapp?=) Date: Sun, 26 Feb 2012 12:59:16 +0100 Subject: [coreboot] Will coreboot work on my machine, HP XW9300? References: <5B9632B43753F047BE43BF138DCF777401F3B072@HSNMST02V05.hsn.alice-dsl.net> <20120226005335.GF20317@tazenda.kollasch.net> Message-ID: <5B9632B43753F047BE43BF138DCF777401F3B073@HSNMST02V05.hsn.alice-dsl.net> Hi, thanks for you reply. The board has three different: 1.) you have right with soldered-on Rom chip 2.) the HP board has only one networkcard 3.) he has a other vedor-id for MAC-adress J?rgen Trapp -----Original Message----- From: Jonathan A. Kollasch [mailto:jakllsch at kollasch.net] Sent: Sun 2/26/2012 1:53 AM To: J?rgen Trapp Cc: coreboot at coreboot.org Subject: Re: [coreboot] Will coreboot work on my machine, HP XW9300? On Sun, Feb 26, 2012 at 12:41:11AM +0100, J?rgen Trapp wrote: > The Board is a OEM by HP, but the builder is TYAN with the board name S2895. Unlike the Tyan version of the board, I believe the HP version has a soldered-on ROM chip. Otherwise, there's a fairly good chance it could work. Jonathan Kollasch -------------- next part -------------- An HTML attachment was scrubbed... URL: From juergen.trapp at alice.de Sun Feb 26 13:51:21 2012 From: juergen.trapp at alice.de (=?iso-8859-1?Q?J=FCrgen_Trapp?=) Date: Sun, 26 Feb 2012 13:51:21 +0100 Subject: [coreboot] HP XW9300 the coreboot.rom failed Message-ID: <5B9632B43753F047BE43BF138DCF777401F3B074@HSNMST02V05.hsn.alice-dsl.net> Hi, the HP XW9300 with coreboot failed. I have before flashing the coreboot.rom, a backup from the bios OUTPUT: sudo flashrom -w coreboot.rom flashrom v0.9.4-r1394 on Linux 3.0.0-12-generic (i686), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA CK804". Enabling flash write... OK. WARNING: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom at flashrom.org with 'CHIPSET: your board name' in the subject line. This chipset supports the following protocols: Non-SPI. Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. Note: If the following flash access fails, try -m :. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x48, failed byte count from 0x00000000-0x00000fff: 0x100 ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x48, failed byte count from 0x00000000-0x0000ffff: 0x100 ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom at flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. sudo flashrom -w hp.rom flashrom v0.9.4-r1394 on Linux 3.0.0-12-generic (i686), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA CK804". Enabling flash write... OK. WARNING: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom at flashrom.org with 'CHIPSET: your board name' in the subject line. This chipset supports the following protocols: Non-SPI. Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. -------------- next part -------------- An HTML attachment was scrubbed... URL: From paulepanter at users.sourceforge.net Sun Feb 26 14:57:43 2012 From: paulepanter at users.sourceforge.net (Paul Menzel) Date: Sun, 26 Feb 2012 14:57:43 +0100 Subject: [coreboot] HP XW9300 the coreboot.rom failed In-Reply-To: <5B9632B43753F047BE43BF138DCF777401F3B074@HSNMST02V05.hsn.alice-dsl.net> References: <5B9632B43753F047BE43BF138DCF777401F3B074@HSNMST02V05.hsn.alice-dsl.net> Message-ID: <1330264663.3039.4.camel@mattotaupa> Dear J?rgen, Am Sonntag, den 26.02.2012, 13:51 +0100 schrieb J?rgen Trapp: > the HP XW9300 with coreboot failed. > I have before flashing the coreboot.rom, a backup from the bios > > OUTPUT: > > sudo flashrom -w coreboot.rom > flashrom v0.9.4-r1394 on Linux 3.0.0-12-generic (i686), built with > libpci 3.1.7, GCC 4.6.1, little endian > flashrom is free software, get the source code at > http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "NVIDIA CK804". Enabling flash write... OK. > WARNING: unexpected second chipset match: "NVIDIA CK804" > ignoring, please report lspci and board URL to flashrom at flashrom.org > with 'CHIPSET: your board name' in the subject line. > This chipset supports the following protocols: Non-SPI. > Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address > 0xfff00000. > Note: If the following flash access fails, try -m > :. > Reading old flash chip contents... done. > Erasing and writing flash chip... ERASE FAILED at 0x00000000! > Expected=0xff, Read=0x48, failed byte count from > 0x00000000-0x00000fff: 0x100 > ERASE FAILED! > Reading current flash chip contents... done. ERASE FAILED at > 0x00000000! Expected=0xff, Read=0x48, failed byte count from > 0x00000000-0x0000ffff: 0x100 > ERASE FAILED! > FAILED! > Uh oh. Erase/write failed. Checking if anything changed. > Good. It seems nothing was changed. > Writing to the flash chip apparently didn't do anything. > This means we have to add special support for your board, programmer > or flash chip. > Please report this on IRC at irc.freenode.net (channel #flashrom) or > mail flashrom at flashrom.org! > ------------------------------------------------------------------------------- > You may now reboot or simply leave the machine running. As the output says. Please contact the Flashrom list. Three more annotations. 1. They are interested in verbose log files, so please also use the parameter -V (or -VV). 2. Flashrom 0.9.5.1 has been released already. Using latest development version is always appreciated [1]. 3. Please just send plain text messages and no HTML messages to lists [2]. Thanks, Paul [1] http://flashrom.org/Downloads [2] http://en.opensuse.org/openSUSE:Mailing_list_netiquette -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 198 bytes Desc: This is a digitally signed message part URL: From gerrit at coreboot.org Sun Feb 26 23:07:21 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 26 Feb 2012 23:07:21 +0100 Subject: [coreboot] New patch to review for coreboot: 4fd599c Intel northbridge I945: Apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/684 -gerrit commit 4fd599cf9ae96f0ae13c816a1e2dd7955c05eec3 Author: Ky?sti M?lkki Date: Fri Feb 24 16:08:18 2012 +0200 Intel northbridge I945: Apply un-written naming rules Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build. Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time which model of I945 the driver is built for. Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4 Signed-off-by: Ky?sti M?lkki --- src/mainboard/getac/p470/Kconfig | 3 ++- src/mainboard/ibase/mb899/Kconfig | 3 ++- src/mainboard/intel/d945gclf/Kconfig | 3 ++- src/mainboard/kontron/986lcd-m/Kconfig | 3 ++- src/mainboard/lenovo/t60/Kconfig | 3 ++- src/mainboard/lenovo/x60/Kconfig | 3 ++- src/mainboard/roda/rk886ex/Kconfig | 3 ++- src/northbridge/intel/Makefile.inc | 3 +-- src/northbridge/intel/i945/Kconfig | 14 +++++++++----- src/northbridge/intel/i945/early_init.c | 4 ++-- src/northbridge/intel/i945/raminit.c | 18 +++++++++--------- 11 files changed, 35 insertions(+), 25 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 6ca11e5..8a4a003 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -22,7 +22,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 - select NORTHBRIDGE_INTEL_I945GM + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCIXX12 diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index ac87466..30f9a70 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -4,7 +4,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 - select NORTHBRIDGE_INTEL_I945GM + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index efc8025..331e945 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -22,7 +22,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_441 - select NORTHBRIDGE_INTEL_I945GC + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index ec5c073..8b45e31 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -4,7 +4,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 - select NORTHBRIDGE_INTEL_I945GM + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index d1abcf6..8ed286c 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -4,7 +4,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 - select NORTHBRIDGE_INTEL_I945GM + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 69f83a8..68f19ca 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -4,7 +4,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 - select NORTHBRIDGE_INTEL_I945GM + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_RICOH_RL5C476 select SUPERIO_NSC_PC87382 diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index d5de7dc..7e527ca 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -4,7 +4,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 - select NORTHBRIDGE_INTEL_I945GM + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCI7420 diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index c599dab..6153052 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -8,7 +8,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 42cc7ce..093411f 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -17,15 +17,19 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config NORTHBRIDGE_INTEL_I945GC +config NORTHBRIDGE_INTEL_I945 bool - select HAVE_DEBUG_RAM_SETUP -config NORTHBRIDGE_INTEL_I945GM - bool +if NORTHBRIDGE_INTEL_I945 + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y select HAVE_DEBUG_RAM_SETUP -if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM +config NORTHBRIDGE_INTEL_SUBTYPE_I945GC + def_bool n +config NORTHBRIDGE_INTEL_SUBTYPE_I945GM + def_bool n config VGA_BIOS_ID string diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 14c66c4..f27dca0 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -91,7 +91,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_NORTHBRIDGE_INTEL_I945GC +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } @@ -140,7 +140,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if CONFIG_NORTHBRIDGE_INTEL_I945GM +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index d92c006..f22af21 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -113,7 +113,7 @@ void sdram_dump_mchbar_registers(void) static int memclk(void) { int offset = 0; -#if CONFIG_NORTHBRIDGE_INTEL_I945GM +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM offset++; #endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { @@ -125,7 +125,7 @@ static int memclk(void) return -1; } -#if CONFIG_NORTHBRIDGE_INTEL_I945GM +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -136,7 +136,7 @@ static u16 fsbclk(void) } return 0xffff; } -#elif CONFIG_NORTHBRIDGE_INTEL_I945GC +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -1075,7 +1075,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index) return nc; } -#if CONFIG_NORTHBRIDGE_INTEL_I945GM +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -1130,7 +1130,7 @@ static const u8 single_channel_strength_multiplier[] = { 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif CONFIG_NORTHBRIDGE_INTEL_I945GC +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -2186,7 +2186,7 @@ static void sdram_program_clock_crossing(void) /** * We add the indices according to our clocks from CLKCFG. */ -#if CONFIG_NORTHBRIDGE_INTEL_I945GM +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2231,7 +2231,7 @@ static void sdram_program_clock_crossing(void) 0xffffffff, 0xffffffff, /* nonexistant */ }; -#elif CONFIG_NORTHBRIDGE_INTEL_I945GC +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2822,9 +2822,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) { u8 clocks[2] = { 0, 0 }; -#if CONFIG_NORTHBRIDGE_INTEL_I945GM +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM #define CLOCKS_WIDTH 2 -#elif CONFIG_NORTHBRIDGE_INTEL_I945GC +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) From gerrit at coreboot.org Sun Feb 26 23:18:43 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Sun, 26 Feb 2012 23:18:43 +0100 Subject: [coreboot] New patch to review for coreboot: 03df38b VIA southbridge K8T890: Apply un-written naming rules References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/685 -gerrit commit 03df38b15cd14ba6d08a206918416ca6be01bb06 Author: Ky?sti M?lkki Date: Sat Feb 25 17:14:20 2012 +0200 VIA southbridge K8T890: Apply un-written naming rules Use separate Kconfig option to select a driver directory for build and the specific type of southbridge to support. Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3 Signed-off-by: Ky?sti M?lkki --- src/mainboard/asus/a8v-e_deluxe/Kconfig | 1 + src/mainboard/asus/a8v-e_se/Kconfig | 1 + src/mainboard/asus/k8v-x/Kconfig | 3 +- src/mainboard/asus/m2v-mx_se/Kconfig | 3 +- src/mainboard/asus/m2v/Kconfig | 1 + src/northbridge/amd/amdk8/incoherent_ht.c | 4 +- src/southbridge/via/Makefile.inc | 6 +---- src/southbridge/via/k8t890/Kconfig | 32 +++++++++++++++------------- src/southbridge/via/k8t890/bridge.c | 4 +- src/southbridge/via/k8t890/ctrl.c | 8 +++--- src/southbridge/via/k8t890/early_car.c | 16 +++++++------- src/southbridge/via/k8t890/romstrap.inc | 6 ++-- src/southbridge/via/vt8237r/lpc.c | 2 +- 13 files changed, 45 insertions(+), 42 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 05408ca..96260bc 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 + select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index 4975cfa..80efbf6 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 + select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 114c609..ff11218 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -7,7 +7,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T800_OLD + select SOUTHBRIDGE_VIA_K8T890 + select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 6434306..72fa803 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -26,7 +26,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8M890 + select SOUTHBRIDGE_VIA_K8T890 + select SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 747c273..731e0de 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R select SOUTHBRIDGE_VIA_K8T890 + select SOUTHBRIDGE_VIA_SUBTYPE_K8T890 select SUPERIO_ITE_IT8712F select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index a14adac..f57eb5b 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -149,10 +149,10 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap); - #if CONFIG_SOUTHBRIDGE_VIA_K8M890 == 1 +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 == 1 freq_cap &= 0x3f; printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n"); - #endif +#endif return freq_cap; } diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc index 3c0160a..8bc9296 100644 --- a/src/southbridge/via/Makefile.inc +++ b/src/southbridge/via/Makefile.inc @@ -1,9 +1,5 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD) += k8t890 # lspci lists B188 and 3188 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800) += k8t890 # lspci lists 0282, 1282, 2282, 3282, and 7282 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) += k8t890 # lspci lists 0282, 1282, 2282, 3282, and 7282 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M800) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 -subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8235) += vt8235 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r + diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index b23b84a..f6e51dc 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -1,25 +1,26 @@ -config SOUTHBRIDGE_VIA_K8M800 #K8M800 not tested - bool - -config SOUTHBRIDGE_VIA_K8T800_OLD # not tested - bool - -config SOUTHBRIDGE_VIA_K8T800 - bool - -config SOUTHBRIDGE_VIA_K8T800PRO - bool - -config SOUTHBRIDGE_VIA_K8M890 - bool config SOUTHBRIDGE_VIA_K8T890 bool +if SOUTHBRIDGE_VIA_K8T890 + +config SOUTHBRIDGE_VIA_SUBTYPE_K8M800 # not tested + def_bool n +config SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD # not tested, lspci lists B188 and 3188 + def_bool n +config SOUTHBRIDGE_VIA_SUBTYPE_K8T800 # lspci lists 0282, 1282, 2282, 3282, and 7282 + def_bool n +config SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO # lspci lists 0282, 1282, 2282, 3282, and 7282 + def_bool n +config SOUTHBRIDGE_VIA_SUBTYPE_K8M890 + def_bool n +config SOUTHBRIDGE_VIA_SUBTYPE_K8T890 + def_bool n + config SOUTHBRIDGE_VIA_K8M890_VGA_EN bool "Enable onboard K8M890 graphics" default y - depends on SOUTHBRIDGE_VIA_K8M890 + depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA @@ -50,3 +51,4 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN +endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index ecfdc35..5e5287e 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,7 +33,7 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); -#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD writeback(dev, 0x42, 0x80); writeback(dev, 0x44, 0x35); #else @@ -49,7 +49,7 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ -#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD writeback(dev, 0x3e, 0x0a); #else writeback(dev, 0x3e, 0x16); diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 1ff0b74..fc851f8 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -51,11 +51,11 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ -#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); #endif pci_write_config8(dev, 0x73, 0x01); -#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD pci_write_config8(dev, 0x74, 0x64); pci_write_config8(dev, 0x75, 0x3f); #else @@ -63,7 +63,7 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x75, 0x0f); #endif pci_write_config8(dev, 0x76, 0x50); -#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); #endif pci_write_config8(dev, 0x78, 0x01); @@ -160,7 +160,7 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ -#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); #endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index da7b4db..5d5f184 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,7 +35,7 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; -#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD #define K8X8XX_HT_CFG_BASE 0xc0 #else #define K8X8XX_HT_CFG_BASE 0x60 @@ -53,7 +53,7 @@ u8 k8t890_early_setup_ht(void) u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; -#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if !CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD u8 reg; /* hack, enable NVRAM in chipset */ @@ -79,21 +79,21 @@ u8 k8t890_early_setup_ht(void) ldtnr = 2; } -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 print_debug("K8M800 found at LDT "); -#elif CONFIG_SOUTHBRIDGE_VIA_K8T800 +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 print_debug("K8T800 found at LDT "); -#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD print_debug("K8T800_OLD found at LDT "); pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); -#elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO print_debug("K8T800 Pro found at LDT "); -#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 print_debug("K8M890 found at LDT "); /* K8M890 fix HT delay */ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22); -#elif CONFIG_SOUTHBRIDGE_VIA_K8T890 +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 print_debug("K8T890 found at LDT "); #endif print_debug_hex8(ldtnr); diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index a3814b0..942def5 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 @@ -52,7 +52,7 @@ tblpointer: .long 0x0 .long 0x0 -#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 tblpointer: .long 0x504400FF, 0x61970FC2 //;200M @@ -72,7 +72,7 @@ tblpointer: .long 0x0 -#elif CONFIG_SOUTHBRIDGE_VIA_K8T890 +#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 tblpointer: .long 0x504400AA, 0x61970FC2 //;200M diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d57d471..7fc5b52 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -322,7 +322,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + #if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 || CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ From svn at coreboot.org Mon Feb 27 16:00:02 2012 From: svn at coreboot.org (coreboot tracker) Date: Mon, 27 Feb 2012 16:00:02 +0100 Subject: [coreboot] Trac reminder: list of new ticket(s) Message-ID: An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Mon Feb 27 20:01:09 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Mon, 27 Feb 2012 20:01:09 +0100 Subject: [coreboot] Patch merged into coreboot/master: 6bfce95 asus/m4a785t-m: correct the CPU microcode patch selection References: Message-ID: the following patch was just integrated into master: commit 6bfce95ce462ea42f08b20a846e07b4c37681b2c Author: Denis 'GNUtoo' Carikli Date: Tue Feb 21 22:29:30 2012 +0100 asus/m4a785t-m: correct the CPU microcode patch selection Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 ruik at ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explained(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli Build-Tested: build bot (Jenkins) at Tue Feb 21 23:49:42 2012, giving +1 Reviewed-By: Marc Jones at Tue Feb 21 23:02:04 2012, giving +2 See http://review.coreboot.org/669 for details. -gerrit From wangqingpei at gmail.com Tue Feb 28 08:52:26 2012 From: wangqingpei at gmail.com (QingPei Wang) Date: Tue, 28 Feb 2012 15:52:26 +0800 Subject: [coreboot] Fwd: [Announce] Now Accepting Applications for Mentoring Organizations for GSoC 2012 In-Reply-To: References: Message-ID: kindly reminder that GSOC 2012 is coming~~~ Best wishes QingPei Wang Phone: 86+018930528086 ---------- Forwarded message ---------- From: Carol Smith Date: Tue, Feb 28, 2012 at 3:47 AM Subject: [Announce] Now Accepting Applications for Mentoring Organizations for GSoC 2012 To: Google Summer of Code Mentors List < google-summer-of-code-mentors-list at googlegroups.com> Hi all, We're pleased to announce the applications for mentoring organizations for GoogleSummer of Code 2012 are now being accepted [1]. Please go Melange [2] to apply on behalf of your organization. Please note that the application period [3] closes on 9 March at 23:00 UTC. We will not accept any late applications for any reason. [1] - http://google-opensource.blogspot.com/2012/02/mentoring-organization-applications-now.html [2] - http://www.google-melange.com [3] - http://www.google-melange.com/gsoc/events/google/gsoc2012 Cheers, Carol -- You received this message because you are subscribed to the Google Groups "Google Summer of Code Mentors List" group. To post to this group, send email to google-summer-of-code-mentors-list at googlegroups.com. To unsubscribe from this group, send email to google-summer-of-code-mentors-list+unsubscribe at googlegroups.com. For more options, visit this group at http://groups.google.com/group/google-summer-of-code-mentors-list?hl=en. -------------- next part -------------- An HTML attachment was scrubbed... URL: From gerrit at coreboot.org Tue Feb 28 13:04:35 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:35 +0100 Subject: [coreboot] New patch to review for coreboot: 5fc1b63 Intel cpus: get MAXPHYADDR at runtime for new CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/686 -gerrit commit 5fc1b63e0baa583b2012569ee8574fbf1dc5943b Author: Ky?sti M?lkki Date: Tue Feb 28 02:06:45 2012 +0200 Intel cpus: get MAXPHYADDR at runtime for new CAR Use CPUID to get MAXPHYADDR and set MTRR masks correctly. Also only BSP CPU clears MTRRs and initializes its Local APIC. Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 58 +++++++++++++++++++++++++------- 1 files changed, 45 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 18fb176..2485e20 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -29,9 +29,6 @@ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) - /* Base address to cache all of Flash ROM, just below 4GB. */ #define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) @@ -44,9 +41,14 @@ cache_as_ram: post_code(0x20) + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_init + /* Zero out all fixed range and variable range MTRRs. - * For hyper-threaded CPU MTRRs are shared so we actually - * clear them more than once, but we don't care. */ + * For hyper-threaded CPUs these are shared. + */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -69,15 +71,45 @@ clear_mtrrs: post_code(0x22) - /* Enable local apic. */ + /* Determine CPU_ADDR_BITS and load PHYSMASK high + * word to %edx. + */ + movl $0x80000000, %eax + cpuid + cmpl $0x80000008, %eax + jc addrsize_no_MSR + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + jmp addrsize_set_high +addrsize_no_MSR: + movl $1, %eax + cpuid + andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ + jz addrsize_set_high + movl $0x0f, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1 and enable local apic at default base. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr movl $LAPIC_BASE_MSR, %ecx + not %edx + movl %edx, %ebx rdmsr - andl $(~CPU_PHYSMASK_HI), %edx + andl %ebx, %edx andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax wrmsr - andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax - jz ap_init bsp_init: @@ -188,8 +220,8 @@ sipi_complete: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx + rdmsr movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ @@ -271,7 +303,7 @@ no_msr_11e: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx + rdmsr movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -343,8 +375,8 @@ no_msr_11e: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx + rdmsr movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable caching and Speculative Reads for Flash ROM device. */ @@ -353,8 +385,8 @@ no_msr_11e: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx + rdmsr movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x39) From gerrit at coreboot.org Tue Feb 28 13:04:35 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:35 +0100 Subject: [coreboot] Patch set updated for coreboot: 6b350da Intel cpus: improve CPU compatibility of new CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/644 -gerrit commit 6b350da4fd2a1f504340fdeed75c2b916220fab1 Author: Ky?sti M?lkki Date: Thu Feb 16 23:12:04 2012 +0200 Intel cpus: improve CPU compatibility of new CAR Most or many Xeons have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 31 ++++++++++++++++++++++++++++++- 1 files changed, 30 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index a6cbd6b..641a2f3 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -83,11 +83,40 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr - /* Enable L2 cache. */ + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). + * + * MSR is set when DisplayFamily_DisplayModel is one of: + * 06_0x, 06_17, 06_1C + * + * Description says this bit enables use of WBINVD and FLUSH#. + * Should this be set only after the system bus and/or memory + * controller can successfully handle write cycles? + */ + +#define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ +#define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) + + movl $1, %eax + cpuid + movl %eax, %ebx + andl $EAX_FAMILY(0x0f), %eax + cmpl $EAX_FAMILY(0x06), %eax + jne no_msr_11e + movl %ebx, %eax + andl $EAX_MODEL(0xff), %eax + cmpl $EAX_MODEL(0x17), %eax + je has_msr_11e + cmpl $EAX_MODEL(0x1c), %eax + je has_msr_11e + andl $EAX_MODEL(0xf0), %eax + cmpl $EAX_MODEL(0x00), %eax + jne no_msr_11e +has_msr_11e: movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax From gerrit at coreboot.org Tue Feb 28 13:04:36 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:36 +0100 Subject: [coreboot] Patch set updated for coreboot: ed37431 Add support for RAM-less multi-processor init References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit ed3743123e4f832be6761a9b550cab5cc8a3f934 Author: Ky?sti M?lkki Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Ky?sti M?lkki --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..0bdef34 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -31,6 +31,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help From gerrit at coreboot.org Tue Feb 28 13:04:36 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:36 +0100 Subject: [coreboot] Patch set updated for coreboot: 265da9b Intel cpus: cache actual size of the Flash ROM device References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/641 -gerrit commit 265da9b2659d2e18bb59e6a99792492fac71bdc8 Author: Ky?sti M?lkki Date: Tue Feb 28 00:24:15 2012 +0200 Intel cpus: cache actual size of the Flash ROM device Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 9 ++++++--- src/mainboard/Kconfig | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 08f5b11..ed207db 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -25,6 +25,9 @@ #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -203,13 +206,13 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a34bd85 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -285,6 +285,10 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 +config CACHE_ROM_SIZE + hex + default ROM_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE From gerrit at coreboot.org Tue Feb 28 13:04:37 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:37 +0100 Subject: [coreboot] Patch set updated for coreboot: 217afa9 Intel cpus: add hyper-threading CPU support to new CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit 217afa9f388738bbb43e80cd631115973b438ce1 Author: Ky?sti M?lkki Date: Tue Feb 28 02:02:27 2012 +0200 Intel cpus: add hyper-threading CPU support to new CAR This improvement of CAR code starts the sibling CPU processors and clears their cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 147 ++++++++++++++++++++++++++++++--- 1 files changed, 134 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 641a2f3..18fb176 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Ky?sti M?lkki * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +27,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) @@ -41,12 +44,9 @@ cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself. */ - movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax - movl %eax, (%edi) - - /* Zero out all fixed range and variable range MTRRs. */ + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -59,12 +59,127 @@ clear_mtrrs: dec %edi jnz clear_mtrrs + post_code(0x21) + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr + post_code(0x22) + + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~CPU_PHYSMASK_HI), %edx + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_init + +bsp_init: + + post_code(0x23) + + /* Send INIT IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + post_code(0x24) + + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc sipi_complete + bswapl %ebx + cmpb $01, %bh + jbe sipi_complete + +hyper_threading_cpu: + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x25) + + /* Send Start IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x26) + + /* Wait for sibling CPU to start. */ +1: movl $(MTRRphysBase_MSR(0)), %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + + +ap_init: + post_code(0x27) + + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + post_code(0x28) + + /* MTRR registers are shared between HT siblings. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(1<<12), %eax + xorl %edx, %edx + wrmsr + + post_code(0x29) + +ap_halt: + cli +1: hlt + jnz 1b + + + +sipi_complete: + + post_code(0x2a) + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax @@ -83,6 +198,8 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr + post_code(0x2b) + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). * * MSR is set when DisplayFamily_DisplayModel is one of: @@ -118,6 +235,8 @@ has_msr_11e: wrmsr no_msr_11e: + post_code(0x2c) + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax @@ -136,6 +255,8 @@ no_msr_11e: orl $(1 << 30), %eax movl %eax, %cr0 + post_code(0x2d) + #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx @@ -160,6 +281,8 @@ no_msr_11e: andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 + post_code(0x2e) + /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ @@ -173,14 +296,12 @@ no_msr_11e: movl %esp, %ebp pushl %eax - post_code(0x23) + post_code(0x2f) /* Call romstage.c main function. */ call main addl $4, %esp - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -188,7 +309,7 @@ no_msr_11e: orl $(1 << 30), %eax movl %eax, %cr0 - post_code(0x31) + post_code(0x34) /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx @@ -196,18 +317,18 @@ no_msr_11e: andl $(~MTRRdefTypeEn), %eax wrmsr - post_code(0x31) + post_code(0x35) invd - post_code(0x33) + post_code(0x36) /* Enable cache. */ movl %cr0, %eax andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 - post_code(0x36) + post_code(0x37) /* Disable cache. */ movl %cr0, %eax From gerrit at coreboot.org Tue Feb 28 13:04:37 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:37 +0100 Subject: [coreboot] Patch set updated for coreboot: f6bf251 Apply cache-as-ram conditionally on socket mPGA604 References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607 -gerrit commit f6bf251e4434d69c7efc33a14b449b4972cfa67c Author: Ky?sti M?lkki Date: Tue Feb 28 14:01:34 2012 +0200 Apply cache-as-ram conditionally on socket mPGA604 The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/Makefile.inc | 8 +------- src/cpu/intel/socket_mPGA604/Kconfig | 17 ++++++++++++++++- src/cpu/intel/socket_mPGA604/Makefile.inc | 2 ++ 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 624b510..ce1f50b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..4fa7569 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,5 +1,10 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -13,4 +18,14 @@ config CPU_INTEL_SOCKET_MPGA604 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..fb1cacd 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc + From gerrit at coreboot.org Tue Feb 28 13:04:38 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:38 +0100 Subject: [coreboot] Patch set updated for coreboot: 33fd183 Intel cpus: apply some good programming practices in new CAR References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643 -gerrit commit 33fd183f1da7a734647fc876d607785990fc6d90 Author: Ky?sti M?lkki Date: Tue Feb 28 01:45:44 2012 +0200 Intel cpus: apply some good programming practices in new CAR Delete dead CAR code and whitespace fixes. Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 39 ++++++++++++-------------------- 1 files changed, 15 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ed207db..a6cbd6b 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -21,6 +21,10 @@ #include #include #include +#include + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) @@ -38,9 +42,9 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -86,17 +90,16 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ @@ -131,11 +134,10 @@ clear_mtrrs: /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -146,6 +148,7 @@ clear_mtrrs: /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f) @@ -167,18 +170,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -196,7 +187,7 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx From gerrit at coreboot.org Tue Feb 28 13:04:38 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Tue, 28 Feb 2012 13:04:38 +0100 Subject: [coreboot] Patch set updated for coreboot: 7380dcf Intel cpus: copy model_6ex CAR code References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 7380dcfbd652b16fbeafb484454f3dcbcabf80cc Author: Ky?sti M?lkki Date: Tue Feb 28 00:15:30 2012 +0200 Intel cpus: copy model_6ex CAR code Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Ky?sti M?lkki --- src/cpu/intel/car/cache_as_ram_ht.inc | 268 +++++++++++++++++++++++++++++++++ 1 files changed, 268 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..08f5b11 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +#define CPU_MAXPHYADDR 36 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + // movl $0x23322332, %eax + xorl %eax, %eax + rep stosl + + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif + movl %eax, %esp + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function. */ + call main + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + From marcj303 at gmail.com Tue Feb 28 23:06:30 2012 From: marcj303 at gmail.com (Marc Jones) Date: Tue, 28 Feb 2012 15:06:30 -0700 Subject: [coreboot] libpayload alloc() gcc 4.6.2 bug? Message-ID: I think I found a bug in gcc 4.6.2 building libpayload (current coreboot crosstools). I would like to get confirmation that someone else sees this and that I haven't done something wrong. Please let me know if there is anything else I should try or post. I'm not sure how to address this. Comments welcome. I found this bug building tint with libpayload. libpayload is built with defconfig and using the same coreboot crosstools gcc. The bug happens in the first call to alloc() when the first header of the first region is installed. The header memory location is checked, found to be 0, and then loaded with the header. The bug is that the original value of the location is used after the memory was updated. It should have been reloaded. It is pretty easy to see in the disassembly below. The libpayload alloc function: static void *alloc(int len) { hdrtype_t header; void *ptr = hstart; /* Align the size. */ len = (len + 3) & ~3; if (!len || len > 0xffffff) return (void *)NULL; /* Make sure the region is setup correctly. */ if (!HAS_MAGIC(*((hdrtype_t *) ptr))) setup(); /* Find some free space. */ do { header = *((hdrtype_t *) ptr); int size = SIZE(header); if (!HAS_MAGIC(header) || size == 0) { <---- fails here due to *((hdrtype_t *) ptr) not being refreshed after memory changes printf("memory allocator panic. (%s%s)\n", !HAS_MAGIC(header) ? " no magic " : "", size == 0 ? " size=0 " : ""); The failing asm: 0010b7c0 : 10b7c0: 56 push %esi 10b7c1: 53 push %ebx 10b7c2: 83 ec 14 sub $0x14,%esp 10b7c5: 8d 70 03 lea 0x3(%eax),%esi 10b7c8: 83 e6 fc and $0xfffffffc,%esi 10b7cb: 74 7c je 10b849 10b7cd: 81 fe ff ff ff 00 cmp $0xffffff,%esi 10b7d3: 7f 74 jg 10b849 10b7d5: a1 a0 5f 11 00 mov 0x115fa0,%eax <--- load alloc header into eax 10b7da: 89 c2 mov %eax,%edx <--- moves it to edx 10b7dc: 81 e2 00 00 00 a8 and $0xa8000000,%edx 10b7e2: 81 fa 00 00 00 a8 cmp $0xa8000000,%edx 10b7e8: 74 1d je 10b807 10b7ea: ba 9c 9f 11 00 mov $0x119f9c,%edx <--- setup() 10b7ef: 81 ea a0 5f 11 00 sub $0x115fa0,%edx 10b7f5: 81 e2 ff ff ff 00 and $0xffffff,%edx 10b7fb: 81 ca 00 00 00 aa or $0xaa000000,%edx 10b801: 89 15 a0 5f 11 00 mov %edx,0x115fa0 <--- memory write 10b807: ba a0 5f 11 00 mov $0x115fa0,%edx 10b80c: eb 04 jmp 10b812 10b80e: 66 90 xchg %ax,%ax 10b810: 8b 02 mov (%edx),%eax 10b812: 89 c1 mov %eax,%ecx <---- starts using eax, but the memory was changed and not reloaded 10b814: 81 e1 ff ff ff 00 and $0xffffff,%ecx This is a passing version built with the old toolchain (gcc 4.5.2): 0010b24c : 10b24c: 55 push %ebp 10b24d: 89 e5 mov %esp,%ebp 10b24f: 56 push %esi 10b250: 53 push %ebx 10b251: 83 c0 03 add $0x3,%eax 10b254: 83 e0 fc and $0xfffffffc,%eax 10b257: 75 0b jne 10b264 10b259: 31 c0 xor %eax,%eax 10b25b: 8d 65 f8 lea -0x8(%ebp),%esp 10b25e: 5b pop %ebx 10b25f: 5e pop %esi 10b260: c9 leave 10b261: c3 ret 10b262: 66 90 xchg %ax,%ax 10b264: 3d ff ff ff 00 cmp $0xffffff,%eax 10b269: 7f ee jg 10b259 10b26b: 8b 15 00 14 11 00 mov 0x111400,%edx <--- loads alloc header into edx. 10b271: 89 d1 mov %edx,%ecx 10b273: 81 e1 00 00 00 a8 and $0xa8000000,%ecx 10b279: 81 f9 00 00 00 a8 cmp $0xa8000000,%ecx 10b27f: 74 1f je 10b2a0 10b281: ba 00 14 11 00 mov $0x111400,%edx <--- setup() 10b286: f7 da neg %edx 10b288: 81 c2 fc 53 11 00 add $0x1153fc,%edx 10b28e: 81 e2 ff ff ff 00 and $0xffffff,%edx 10b294: 81 ca 00 00 00 aa or $0xaa000000,%edx 10b29a: 89 15 00 14 11 00 mov %edx,0x111400 <--- memory updated and still in edx 10b2a0: b9 00 14 11 00 mov $0x111400,%ecx 10b2a5: eb 03 jmp 10b2aa 10b2a7: 90 nop 10b2a8: 8b 11 mov (%ecx),%edx 10b2aa: 89 d3 mov %edx,%ebx <--- edx has correct value My failing gcc version: $ /i386-elf-gcc -v Using built-in specs. COLLECT_GCC=/home/marc/git/coreboot2/payloads/tint-0.03b/./../../util/crossgcc/xgcc/bin/i386-elf-gcc COLLECT_LTO_WRAPPER=/home/marc/devel/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/4.6.2/lto-wrapper Target: i386-elf Configured with: ../gcc-4.6.2/configure --enable-multilib=yes --prefix=/home/marc/devel/coreboot/util/crossgcc/xgcc --libexecdir=/home/marc/devel/coreboot/util/crossgcc/xgcc/lib --target=i386-elf --disable-werror --disable-shared --disable-libssp --disable-bootstrap --disable-nls --disable-libquadmath --with-newlib --enable-lto --enable-languages=c --with-gmp=/home/marc/devel/coreboot/util/crossgcc/xgcc --with-mpfr=/home/marc/devel/coreboot/util/crossgcc/xgcc --with-mpc=/home/marc/devel/coreboot/util/crossgcc/xgcc --with-libelf=/home/marc/devel/coreboot/util/crossgcc/xgcc --with-pkgversion='coreboot toolchain v1.07 November 1st, 2011' Thread model: single gcc version 4.6.2 (coreboot toolchain v1.07 November 1st, 2011) tint.elf and objdump -D files attached. My git repo if you would like try this exact code: git://git.se-eng.com/coreboot.git Questions or comments? Marc -- http://se-eng.com -------------- next part -------------- A non-text attachment was scrubbed... Name: tint-gcc462bug.tar.gz Type: application/x-gzip Size: 479907 bytes Desc: not available URL: From gerrit at coreboot.org Wed Feb 29 01:33:51 2012 From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com)) Date: Wed, 29 Feb 2012 01:33:51 +0100 Subject: [coreboot] New patch to review for coreboot: ca83caf tint requires more heap space for PDCurses. References: Message-ID: Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/687 -gerrit commit ca83caf03615a3ea7cbba7a9a19f6c3d63036793 Author: Marc Jones Date: Tue Feb 28 17:18:58 2012 -0700 tint requires more heap space for PDCurses. tint was failing with the message "initscr(): Unable to create curscr." tint uses the initscr() to enable vga windows, which allocates more heap space with PDCurses than with tinycurses. Expanding the heap from 16KB to 64KB resolves the issue. Change-Id: I1d38651e2b77f55613969c29614fb3b2be38a00c Signed-off-by: Marc Jones --- payloads/libpayload/lib/libpayload.ldscript | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/lib/libpayload.ldscript b/payloads/libpayload/lib/libpayload.ldscript index 830a390..4925e86 100644 --- a/payloads/libpayload/lib/libpayload.ldscript +++ b/payloads/libpayload/lib/libpayload.ldscript @@ -34,7 +34,7 @@ OUTPUT_ARCH(i386) ENTRY(_entry) -HEAP_SIZE = 16384; +HEAP_SIZE = 65536; STACK_SIZE = 16384; SECTIONS From gerrit at coreboot.org Wed Feb 29 01:42:57 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 29 Feb 2012 01:42:57 +0100 Subject: [coreboot] Patch merged into coreboot/master: b2b6c53 AMD southbridge: remove sp5100 References: Message-ID: the following patch was just integrated into master: commit b2b6c535a1e8cdd5d39fc1a13267b14ac1fd2edb Author: Ky?sti M?lkki Date: Thu Feb 23 18:42:55 2012 +0200 AMD southbridge: remove sp5100 Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Sat Feb 25 13:47:54 2012, giving +1 Reviewed-By: Marc Jones at Wed Feb 29 01:42:11 2012, giving +2 See http://review.coreboot.org/679 for details. -gerrit From patrick at georgi-clan.de Wed Feb 29 08:39:17 2012 From: patrick at georgi-clan.de (Patrick Georgi) Date: Wed, 29 Feb 2012 08:39:17 +0100 Subject: [coreboot] libpayload alloc() gcc 4.6.2 bug? In-Reply-To: References: Message-ID: <4F4DD625.6070906@georgi-clan.de> Am 28.02.2012 23:06, schrieb Marc Jones: > I found this bug building tint with libpayload. libpayload is built > with defconfig and using the same coreboot crosstools gcc. The bug > happens in the first call to alloc() when the first header of the > first region is installed. The header memory location is checked, > found to be 0, and then loaded with the header. The bug is that the > original value of the location is used after the memory was updated. > It should have been reloaded. It is pretty easy to see in the > disassembly below. workaround: mark setup() __attribute__((noinline)) The proper fix is to clean up the various casts so the aliasing based optimizations in gcc do the right thing. Patrick From marcj303 at gmail.com Wed Feb 29 17:38:09 2012 From: marcj303 at gmail.com (Marc Jones) Date: Wed, 29 Feb 2012 09:38:09 -0700 Subject: [coreboot] libpayload alloc() gcc 4.6.2 bug? In-Reply-To: <4F4DD625.6070906@georgi-clan.de> References: <4F4DD625.6070906@georgi-clan.de> Message-ID: On Wed, Feb 29, 2012 at 12:39 AM, Patrick Georgi wrote: > Am 28.02.2012 23:06, schrieb Marc Jones: >> I found this bug building tint with libpayload. libpayload is built >> with defconfig and using the same coreboot crosstools gcc. The bug >> happens in the first call to alloc() when the first header of the >> first region is installed. The header memory location is checked, >> found to be 0, and then loaded with the header. The bug is that the >> original value of the location is used after the memory was updated. >> It should have been reloaded. It is pretty easy to see in the >> disassembly below. > workaround: mark setup() __attribute__((noinline)) > > The proper fix is to clean up the various casts so the aliasing based > optimizations in gcc do the right thing. Can you expand on this? Do you mean that we should change do something like this? hdrtype_t *ptr = hstart; Marc -- http://se-eng.com From gerrit at coreboot.org Wed Feb 29 20:08:42 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 29 Feb 2012 20:08:42 +0100 Subject: [coreboot] Patch merged into coreboot/master: ca83caf tint requires more heap space for PDCurses. References: Message-ID: the following patch was just integrated into master: commit ca83caf03615a3ea7cbba7a9a19f6c3d63036793 Author: Marc Jones Date: Tue Feb 28 17:18:58 2012 -0700 tint requires more heap space for PDCurses. tint was failing with the message "initscr(): Unable to create curscr." tint uses the initscr() to enable vga windows, which allocates more heap space with PDCurses than with tinycurses. Expanding the heap from 16KB to 64KB resolves the issue. Change-Id: I1d38651e2b77f55613969c29614fb3b2be38a00c Signed-off-by: Marc Jones Build-Tested: build bot (Jenkins) at Wed Feb 29 01:45:48 2012, giving +1 Reviewed-By: Marc Jones at Wed Feb 29 20:08:40 2012, giving +2 See http://review.coreboot.org/687 for details. -gerrit From gerrit at coreboot.org Wed Feb 29 20:22:16 2012 From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com)) Date: Wed, 29 Feb 2012 20:22:16 +0100 Subject: [coreboot] New patch to review for coreboot: dd17846 Fix x86 cpu_phys_address_size References: Message-ID: Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/688 -gerrit commit dd17846e4422969c9915bd0d31ebb3769059f80a Author: Ky?sti M?lkki Date: Wed Feb 29 21:17:18 2012 +0200 Fix x86 cpu_phys_address_size After CPUID, requested feature flag is in edx, not eax. Change-Id: I9ce27c22186f17cc64986be342d7d1ac78a79898 Signed-off-by: Ky?sti M?lkki --- src/arch/x86/lib/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index ada57e2..8aacaac 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -147,7 +147,7 @@ int cpu_phys_address_size(void) if (cpu_cpuid_extended_level() >= 0x80000008) return cpuid_eax(0x80000008) & 0xff; - if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) return 36; return 32; } From gerrit at coreboot.org Wed Feb 29 20:58:16 2012 From: gerrit at coreboot.org (gerrit at coreboot.org) Date: Wed, 29 Feb 2012 20:58:16 +0100 Subject: [coreboot] Patch merged into coreboot/master: dd17846 Fix x86 cpu_phys_address_size References: Message-ID: the following patch was just integrated into master: commit dd17846e4422969c9915bd0d31ebb3769059f80a Author: Ky?sti M?lkki Date: Wed Feb 29 21:17:18 2012 +0200 Fix x86 cpu_phys_address_size After CPUID, requested feature flag is in edx, not eax. Change-Id: I9ce27c22186f17cc64986be342d7d1ac78a79898 Signed-off-by: Ky?sti M?lkki Build-Tested: build bot (Jenkins) at Wed Feb 29 20:37:31 2012, giving +1 Reviewed-By: Sven Schnelle at Wed Feb 29 20:58:14 2012, giving +2 See http://review.coreboot.org/688 for details. -gerrit