[coreboot] New patch to review for coreboot: d26740b Apply cache-as-ram conditionally on socket mPGA604

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607

-gerrit

commit d26740b827bcd4b3621200f8a9c911a107857022
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Feb 1 19:15:13 2012 +0200

    Apply cache-as-ram conditionally on socket mPGA604
    
    The socket mPGA604 is for P4 Xeon which to my knowledge is always
    HT-enabled. I assume the existing usage of car/cache_as_ram.inc
    on socket_mPGA604, namely the Tyan S2735, as broken.
    
    Existing car/cache_as_ram.inc has invalid SIPI vector and it does
    not initialise AP CPU's to activate L2 cache.
    
    Other mPGA604 boards are not affected, as they have not been
    converted to CAR.
    
    Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/Makefile.inc                 |    8 +-------
 src/cpu/intel/socket_mPGA604/Kconfig      |   16 ++++++++++++++++
 src/cpu/intel/socket_mPGA604/Makefile.inc |    2 ++
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 36f9d3a..420378b 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc
 endif
 
 crt0s += $(cpu_incs)
-
-#
-# FIXME move to CPU_INTEL_SOCKET_MPGA604
-#
-ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
-crt0s += $(src)/cpu/intel/car/cache_as_ram.inc
-endif
+crt0s += $(cpu_incs-y)
 
 ifeq ($(CONFIG_LLSHELL),y)
 crt0s += $(src)/arch/x86/llshell/llshell.inc
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 2fc27cf..8f65a98 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -1,5 +1,10 @@
 config CPU_INTEL_SOCKET_MPGA604
 	bool
+
+if CPU_INTEL_SOCKET_MPGA604
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+	def_bool y
 	select CPU_INTEL_MODEL_F2X
 	select CPU_INTEL_MODEL_F3X
 	select CPU_INTEL_MODEL_F4X
@@ -14,3 +19,14 @@ config SSE2
 	bool
 	default n
 	depends on CPU_INTEL_SOCKET_MPGA604
+
+config DCACHE_RAM_BASE
+	hex
+	default 0x0ffafc000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+
+endif # CPU_INTEL_SOCKET_MPGA604
+
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
index 1404e84..fb1cacd 100644
--- a/src/cpu/intel/socket_mPGA604/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
+cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+