[coreboot] How to port core boot
r.marek at assembler.cz
Tue Feb 7 16:36:28 CET 2012
> DRAM range verified.
Well the check is quite simple maybe it works for simple cases and fails for
real usage. I guess you need to port something like
http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again. All
it sounds like raminit problem.
Also I don't like couple of things btw. You never showed any of your code. You
only ask sometimes too simple question without bothering too much with them.
Please try hard before asking and try to learn new stuff. You have chosen quite
difficult area, maybe you should try some simpler stuff first to get in touch
better with C and common toolchains and after that get back here in here.
> Loading image.
> Searching for fallback/coreboot_ram
> Check fallback/romstage
> Check fallback/coreboot_ram
> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000
> Stage: done loading.
> Jumping to image.
> On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek<r.marek at assembler.cz> wrote:
>>> Seems there is a case or two of possible infinite while() loops within
>>> the uart8250 serial console code. This is a wild guess, but the uart
>> Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It is
>> always better to boot than to have perfect serial output ;)
>> But in this case I would think memory is not 100% OK. Worth to check if
>> 1M->3M is OK (this is where coreboot ramstage goes)
>> coreboot mailing list: coreboot at coreboot.org
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