[coreboot] How to port core boot
bari at onelabs.com
Tue Feb 7 17:53:21 CET 2012
Here is what is going on here. Unless I missed a memo, coreboot is not a
no cost course on learning how to program with 24hr free tech support.
Initially I was under the impression that there might be a language
barrier here. But after reading your attack on the developers in order
to gain some negative attention I see that it's a personality issue.
Most of the developers here have families, full time jobs and also work
on several open source projects and might even sleep and eat meals as
required. Several have spent decades working and studying to gain the
experience that they now have but also see the value in sharing some of
this for the common good of mankind.
If somebody is replying to your novice level questions on how coreboot,
C, gcc, memory controllers or x86 architecture works, be happy that
somebody has decided to volunteer a small portion of their lifetime to
Most of the answers to your questions are obvious to the experienced
developers and most of the replies have hinted at *your need to gain
more experience and knowledge* on all the topics I have mentioned
earlier. The devs don't really have the time or desire to write lengthy
tutorials on the subjects.
You might be able to find a mentor though if you ask nicely. It also
helps if you fund their time.
Have you followed their advice? Have you gone back and worked with some
much more simple programming projects to gain the experience necessary?
Have you even shared your source code for review?
On 02/07/2012 09:59 AM, ali hagigat wrote:
> Rudolf, When i started to study Coreboot and BIOS , people always made
> me confused by nonsense words. I asked some useful questions but
> interpreted as simple.(now I have developed a project which can drive
> RAM, serial port and hard disk)
> The managers of this project even do not accept their own mistakes.
> Now FILO can not be compiled and when i report it as the README of the
> filo is saying, the manager emails me and tells me that you are not a
> I thought i would be encouraged for that by a thank you. When i ask a
> question nobody talks about the details of the logic behind that
> except one person, Kyösti Mälkki.
> Hey folks, what is going on here? If you are a master of Coreboot why
> we have unrelated simple answers?
> On 2/7/12, Rudolf Marek<r.marek at assembler.cz> wrote:
>>> DRAM range verified.
>> Well the check is quite simple maybe it works for simple cases and fails for
>> real usage. I guess you need to port something like
>> http://pyropus.ca/software/memtester/ to ROMCC to romstage and try again.
>> it sounds like raminit problem.
>> Also I don't like couple of things btw. You never showed any of your code.
>> only ask sometimes too simple question without bothering too much with them.
>> Please try hard before asking and try to learn new stuff. You have chosen
>> difficult area, maybe you should try some simpler stuff first to get in
>> better with C and common toolchains and after that get back here in here.
>>> Loading image.
>>> Searching for fallback/coreboot_ram
>>> Check fallback/romstage
>>> Check fallback/coreboot_ram
>>> Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @
>>> Stage: done loading.
>>> Jumping to image.
>>> On Tue, Feb 7, 2012 at 3:07 AM, Rudolf Marek<r.marek at assembler.cz> wrote:
>>>>> Seems there is a case or two of possible infinite while() loops within
>>>>> the uart8250 serial console code. This is a wild guess, but the uart
>>>> Yeah I dont like that too. Maybe worth to do a timeout? Or Loop count? It
>>>> always better to boot than to have perfect serial output ;)
>>>> But in this case I would think memory is not 100% OK. Worth to check if
>>>> 1M->3M is OK (this is where coreboot ramstage goes)
>>>> coreboot mailing list: coreboot at coreboot.org
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