[coreboot] New patch to review for coreboot: e5ce5d2 i5000: halt second BSP

[Sven Schnelle (svens@stackframe.org)]

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615

-gerrit

commit e5ce5d2160acc69fae296c1fcf89f2c12dadd1e3
Author: Sven Schnelle <svens at stackframe.org>
Date:   Thu Feb 9 21:05:20 2012 +0100

    i5000: halt second BSP
    
    If both FSBs on i5000 are equipped with CPU packages, one CPU
    from each package is elected as BSP. To prevent races between
    both BSPs, hlt the second BSP.
    
    Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/i5000/Makefile.inc      |    1 +
 src/northbridge/intel/i5000/halt_second_bsp.S |   23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
index a5623c0..0c3ce0d 100644
--- a/src/northbridge/intel/i5000/Makefile.inc
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -19,3 +19,4 @@
 
 driver-y += northbridge.c
 romstage-y += raminit.c udelay.c
+cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S
\ No newline at end of file
diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S
new file mode 100644
index 0000000..da13178
--- /dev/null
+++ b/src/northbridge/intel/i5000/halt_second_bsp.S
@@ -0,0 +1,23 @@
+	/* Save BIST result */
+
+	movl	%eax, %ebp
+
+	/* Read the semaphore register of i5000 (BOFL0).
+	   If it returns zero, it means there was already
+	   another read by another CPU */
+
+	movl	$0x800080c0, %eax
+	movw	$0xcf8, %dx
+	outl	%eax, %dx
+
+	addw	$4, %dx
+	inl	%dx, %eax
+	cmp	$0, %eax
+	jne	1f
+
+	cli
+	hlt
+tloop:	jmp	tloop
+
+1:	/* Restore BIST */
+	mov	%ebp, %eax