[coreboot] New patch to review for coreboot: 0bb3bba Whitespaces changes.

Zheng Bao (zheng.bao@amd.com) gerrit at coreboot.org
Mon Feb 13 11:09:03 CET 2012


Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/625

-gerrit

commit 0bb3bba33f27110e1f6c61bd517822300eca9f3e
Author: zbao <zheng.bao at amd.com>
Date:   Mon Feb 13 17:36:29 2012 +0800

    Whitespaces changes.
    
    Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
---
 src/mainboard/amd/persimmon/BiosCallOuts.c     |   45 +++++++------
 src/mainboard/amd/persimmon/PlatformGnbPcie.c  |    1 -
 src/mainboard/amd/persimmon/get_bus_conf.c     |    3 +-
 src/mainboard/amd/persimmon/mainboard.c        |    1 +
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c |   10 ++--
 src/vendorcode/amd/agesa/f14/gcccar.inc        |   84 ++++++++++++------------
 6 files changed, 74 insertions(+), 70 deletions(-)

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index df00c7c..06426c2 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -155,8 +155,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 			}
 			CurrNodeOffset = CurrNodePtr->NextNodeOffset;
 			/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
-			 to the end of the allocated nodes list.
+			   to the end of the allocated nodes list.
 			*/
+
 		}
 		/* Find the node that best fits the requested buffer size */
 		FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@@ -205,7 +206,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 			}
 
 			/* If BestFitNode is the first buffer in the list, then update
-			 StartOfFreedNodes to reflect the new free node
+			   StartOfFreedNodes to reflect the new free node
 			*/
 			if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
 				BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
@@ -290,10 +291,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 			/* Clear the BufferSize and NextNodeOffset of the previous first node */
 			FreedNodePtr->BufferSize = 0;
 			FreedNodePtr->NextNodeOffset = 0;
+
 		} else {
 			/* Otherwise, add freed node to the start of the list
-			 Update NextNodeOffset and BufferSize to include the
-			 size of BIOS_BUFFER_NODE
+			   Update NextNodeOffset and BufferSize to include the
+			   size of BIOS_BUFFER_NODE
 			*/
 			AllocNodePtr->NextNodeOffset = FreedNodeOffset;
 		}
@@ -301,21 +303,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 		BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
 	} else {
 		/* Traverse list of freed nodes to find where the deallocated node
-			 should be place
+		   should be place
 		*/
 		NextNodeOffset = FreedNodeOffset;
 		NextNodePtr = FreedNodePtr;
 		while (AllocNodeOffset > NextNodeOffset) {
 			PrevNodeOffset = NextNodeOffset;
 			if (NextNodePtr->NextNodeOffset == 0) {
-			break;
+				break;
 			}
 			NextNodeOffset = NextNodePtr->NextNodeOffset;
 			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
 		}
 
 		/* If deallocated node is adjacent to the next node,
-			 concatenate both nodes
+		   concatenate both nodes
 		*/
 		if (NextNodeOffset == EndNodeOffset) {
 			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
@@ -329,13 +331,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 			AllocNodePtr->NextNodeOffset = NextNodeOffset;
 		}
 		/* If deallocated node is adjacent to the previous node,
-			 concatenate both nodes
+		   concatenate both nodes
 		*/
 		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
 		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
 		if (AllocNodeOffset == EndNodeOffset) {
 			PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
 			PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
 			AllocNodePtr->BufferSize = 0;
 			AllocNodePtr->NextNodeOffset = 0;
 		} else {
@@ -405,17 +408,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	// 0xCF9 (Reset Port).
 	//
 	switch (ResetType) {
-		case WARM_RESET_WHENEVER:
-		case COLD_RESET_WHENEVER:
+	case WARM_RESET_WHENEVER:
+	case COLD_RESET_WHENEVER:
 		break;
 
-		case WARM_RESET_IMMEDIATELY:
-		case COLD_RESET_IMMEDIATELY:
-			Value = 0x06;
-			LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+	case WARM_RESET_IMMEDIATELY:
+	case COLD_RESET_IMMEDIATELY:
+		Value = 0x06;
+		LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
 		break;
 
-		default:
+	default:
 		break;
 	}
 
@@ -562,13 +565,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 	{
 	case 4:
 		switch (ResetInfo->ResetControl) {
-			case AssertSlotReset:
+		case AssertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
 			Data8 &= ~(UINT8)BIT6 ;
 			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);	 // MXM_GPIO0. GPIO21
 			Status = AGESA_SUCCESS;
 			break;
-			case DeassertSlotReset:
+		case DeassertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
 			Data8 |= BIT6 ;
 			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);		 // MXM_GPIO0. GPIO21
@@ -578,13 +581,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 		break;
 	case 6:
 		switch (ResetInfo->ResetControl) {
-			case AssertSlotReset:
+		case AssertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
 			Data8 &= ~(UINT8)BIT6 ;
 			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);	 // PCIE_RST#_LAN, GPIO25
 			Status = AGESA_SUCCESS;
 			break;
-			case DeassertSlotReset:
+		case DeassertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
 			Data8 |= BIT6 ;
 			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);		 // PCIE_RST#_LAN, GPIO25
@@ -594,13 +597,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 		break;
 	case 7:
 		switch (ResetInfo->ResetControl) {
-			case AssertSlotReset:
+		case AssertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
 			Data8 &= ~(UINT8)BIT6 ;
 			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);	 // MPCIE_RST0, GPIO02
 			Status = AGESA_SUCCESS;
 			break;
-			case DeassertSlotReset:
+		case DeassertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
 			Data8 |= BIT6 ;
 			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);		 // MPCIE_RST0, GPIO02
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
index 2f69e01..bdfcb66 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
@@ -166,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
 	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
-
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index fef7d60..4c094ae 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -136,7 +136,8 @@ void get_bus_conf(void)
 	for (j = bus_sb800[2]; j < bus_isa; j++)
 		bus_type[j] = 1;
 
-	/* I/O APICs:	 APIC ID Version State	 Address */
+
+	/* I/O APICs:    APIC ID Version State   Address */
 	bus_isa = 10;
 	apicid_base = CONFIG_MAX_CPUS;
 	apicid_sb800 = apicid_base;
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 23eea86..9a8428e 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -121,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 #endif
 	return 0;
 }
+
 struct chip_operations mainboard_ops = {
 	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
 	.enable_dev = persimmon_enable,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
index ac613b1..a48d737 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c
@@ -25,7 +25,7 @@
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -33,10 +33,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -47,7 +47,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 981d976..d81b6af 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -9,10 +9,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -23,9 +23,9 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  */
- 
+
 /******************************************************************************
 * AMD Generic Encapsulated Software Architecture
 *
@@ -158,28 +158,28 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
  *                      CPU MACROS - PUBLIC
  *
  ****************************************************************************/
-.macro   _WRMSR 
-        .byte 0x0f, 0x30        
+.macro   _WRMSR
+        .byte 0x0f, 0x30
 .endm
 
-.macro  _RDMSR  
-        .byte   0x0F, 0x32      
+.macro  _RDMSR
+        .byte   0x0F, 0x32
 .endm
 
 .macro AMD_CPUID arg0
-  .ifb \arg0                                             
-    mov   $0x1, %eax    
+  .ifb \arg0
+    mov   $0x1, %eax
     .byte 0x0F, 0x0A2                     /* Execute instruction */
-    bswap %eax                          
+    bswap %eax
     xchg  %ah, %al                        /* Ext model in al now */
     rol   $0x08, %eax                     /* Ext model in ah, model in al */
     and   $0x0FFCF, ax                    /* Keep 23:16, 7:6, 3:0 */
   .else
-    mov   \arg0, %eax    
-    .byte 0x0F, 0x0A2   
+    mov   \arg0, %eax
+    .byte 0x0F, 0x0A2
   .endif
 .endm
-  
+
 /****************************************************************************
 *
 * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
@@ -194,12 +194,12 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
  ****************************************************************************/
 .macro  AMD_ENABLE_STACK_FAMILY_HOOK
 
-    AMD_ENABLE_STACK_FAMILY_HOOK_F10    
-    AMD_ENABLE_STACK_FAMILY_HOOK_F12    
-    AMD_ENABLE_STACK_FAMILY_HOOK_F14    
-    AMD_ENABLE_STACK_FAMILY_HOOK_F15    
+    AMD_ENABLE_STACK_FAMILY_HOOK_F10
+    AMD_ENABLE_STACK_FAMILY_HOOK_F12
+    AMD_ENABLE_STACK_FAMILY_HOOK_F14
+    AMD_ENABLE_STACK_FAMILY_HOOK_F15
 .endm
-  
+
 /****************************************************************************
 *
 * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
@@ -220,7 +220,7 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
     AMD_DISABLE_STACK_FAMILY_HOOK_F15
 
 .endm
-  
+
 /****************************************************************************
 *
 * GET_NODE_ID_CORE_ID Macro - Stackless
@@ -252,9 +252,9 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
      */
     cmp     $-1, %si                      # Has family (node/core) already been discovered?
     jnz     node_core_exit              # Br if yes
-    
+
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
-	
+
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
@@ -263,7 +263,7 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
 node_core_exit:
 
 .endm
-  
+
 /****************************************************************************
 ##                      Family 10h MACROS
 ##***************************************************************************
@@ -291,7 +291,7 @@ node_core_exit:
 #   * MSRC001_102A[ClLinesToNbDis]=1
 #   * No INVD or WBINVD, no exceptions, page faults or interrupts
 ****************************************************************************/
-.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
     LOCAL   fam10_enable_stack_hook_exit
 
     AMD_CPUID   $CPUID_MODEL
@@ -324,7 +324,7 @@ node_core_exit:
     jc      fam10_skipClearingBit4
     btr     $INVD_WBINVD, %eax             # disable INVD -> WBINVD conversion
     _WRMSR
-    
+
 fam10_skipClearingBit4:
     mov %esi, %eax                         # load core#
     or %al, %al                       # If (BSP)
@@ -347,7 +347,7 @@ fam10_skipClearingBit4:
 
 fam10_enable_stack_hook_exit:
 .endm
-  
+
 /****************************************************************************
 *
 * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
@@ -371,7 +371,7 @@ fam10_enable_stack_hook_exit:
 *   * MSRC001_102A[IcDisSpecTlbWr]=0
 *   * MSRC001_102A[ClLinesToNbDis]=0
 *****************************************************************************/
-     
+
 .macro  AMD_DISABLE_STACK_FAMILY_HOOK_F10
     LOCAL   fam10_disable_stack_hook_exit
 
@@ -427,7 +427,7 @@ fam10_enable_stack_hook_exit:
     _WRMSR                              # Disable the event
 
 fam10_disable_stack_hook_exit:
-.endm   
+.endm
 
 /****************************************************************************
 *
@@ -589,7 +589,7 @@ node_core_f10_exit:
     jc      fam12_skipClearingBit4
     btr     $INVD_WBINVD, %eax            # disable INVD -> WBINVD conversion
     _WRMSR
-    
+
 fam12_skipClearingBit4:
     mov     $DE_CFG, %ecx                 # MSR:C001_1029
     _RDMSR
@@ -893,7 +893,7 @@ node_core_f14_exit:
     _RDMSR
     btr     $INVD_WBINVD, %eax            # disable INVD -> WBINVD conversion
     _WRMSR
-    
+
 fam15_skipClearingBit4:
     mov     $LS_CFG, %ecx                 # MSR:C001_1020
     _RDMSR
@@ -973,7 +973,7 @@ fam15_enable_stack_hook_exit:
     btr     $DIS_HW_PF, %eax              # Turn on hardware prefetches
     #.endif                              # End workaround for erratum 498
     0:
-    _WRMSR	
+    _WRMSR
     #--------------------------------------------------------------------------
     # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------
@@ -1135,7 +1135,7 @@ node_core_f15_shared:
                 #.break .if (ch == bl)   # Does 2nd match MyCore#?
                 cmp     %bl, %ch
                 je      9f
-                jmp     2f   
+                jmp     2f
             #.else                       # No 2nd core
             4:
                 #.break .if (ch == bl)   # Does 1st match MyCore#?
@@ -1240,7 +1240,7 @@ node_core_f15_exit:
 *     | >|MA|IN| B|IO|S |RA|NG|E |  |  |  |  |  |  |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE|  |  |  |  |  |< |
 *     +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
 *****************************************************************************/
-.macro  AMD_ENABLE_STACK 
+.macro  AMD_ENABLE_STACK
 
 # These are local labels. Declared so linker doesn't cause 'redefined label' errors
     LOCAL   SetupStack
@@ -1308,7 +1308,7 @@ SetupStack:
         #.if (carry?)                    #     Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
             #  Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
             # Clear all variable and Fixed MTRRs for non-shared cores
-        jnc 0f    
+        jnc 0f
         mov     $AMD_MTRR_VARIABLE_BASE0, %ecx
         xor     %eax, %eax
         xor     %edx, %edx
@@ -1344,20 +1344,20 @@ SetupStack:
         _WRMSR
         #.endif                          #   End Is_Primary
     #.endif                              # End Stack_ReEntry
-    0:    
+    0:
     # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
     xor     %eax, %eax
     xor     %edx, %edx
     mov     $IORR_BASE, %ecx              # MSR:C001_0016 - 0019
     #.while (cl != 1Ah)
     jmp  1f
-    2:   
+    2:
         _WRMSR
         inc     %cl
     #.endw
-    1:  
+    1:
     cmp $0x1A, %cl
-    jne  2b   
+    jne  2b
     mov     $TOP_MEM2, %ecx               # MSR:C001_001D
     _WRMSR
 
@@ -1428,7 +1428,7 @@ SetupStack:
         mov     %eax, %ebp
     #.endif
     0:
-        
+
     # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
     mov     $WB_DRAM_TYPE, %edi           # Load Cache type in 1st slot
     mov     %bh, %cl                      # ShiftCount =  ((slot#   ...
@@ -1584,7 +1584,7 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 *   Destroyed:
 *       eax, ecx, edx, esp
 *****************************************************************************/
-.macro  AMD_DISABLE_STACK 
+.macro  AMD_DISABLE_STACK
 
     mov     %ebx, %esp                    # Save return address
 




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