[coreboot] New patch to review for coreboot: 2e3c13a Intel cpus: add NetBurst compatibility to model_6ex CAR

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/644

-gerrit

commit 2e3c13a0b9ee6dde5a2db7b25ba3019107790f51
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Feb 16 23:12:04 2012 +0200

    Intel cpus: add NetBurst compatibility to model_6ex CAR
    
    P4 CPUs with NetBurst architecture have no MSR 0x11e.
    
    I have previously tested that a HT-enabled P4 (model f25) can
    execute this but will not have cache-as-ram enabled. Should work
    for non-HT P4.
    
    Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/Kconfig                    |    8 ++++++++
 src/cpu/intel/model_6ex/cache_as_ram.inc |   10 +++++++++-
 2 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 81a834c..4e4e2ee 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -1,3 +1,11 @@
+
+config INTEL_NETBURST
+	bool
+	default n
+	help
+	  Select Y to bypass MSR 0x11e during CAR.
+	  FIXME: Runtime CPUID check instead.
+
 # CPU models
 source src/cpu/intel/model_6xx/Kconfig
 source src/cpu/intel/model_67x/Kconfig
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 5a29744..4505e0e 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -82,11 +82,19 @@ clear_mtrrs:
 	orl	$MTRRdefTypeEn, %eax
 	wrmsr
 
-	/* Enable L2 cache. */
+#if !CONFIG_INTEL_NETBURST
+	/* Enable L2 cache Write-Back (WBINVD and FLUSH#).
+	 * This MSR does not exist on NetBurst architecture.
+	 *
+	 * Description says this bit enables use of WBINVD and FLUSH#.
+	 * Should this be set only after the system bus and/or memory
+	 * controller can successfully handle write cycles?
+	 */
 	movl	$0x11e, %ecx
 	rdmsr
 	orl	$(1 << 8), %eax
 	wrmsr
+#endif
 
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax