[coreboot] HP XW9300 the coreboot.rom failed

[Jürgen Trapp]

Hi,

the HP XW9300 with coreboot failed.
I have before flashing the coreboot.rom, a backup from the bios

OUTPUT:

sudo flashrom -w coreboot.rom
flashrom v0.9.4-r1394 on Linux 3.0.0-12-generic (i686), built with libpci 3.1.7, GCC 4.6.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
Found chipset "NVIDIA CK804". Enabling flash write... OK.
WARNING: unexpected second chipset match: "NVIDIA CK804"
ignoring, please report lspci and board URL to flashrom at flashrom.org
with 'CHIPSET: your board name' in the subject line.
This chipset supports the following protocols: Non-SPI.
Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000.
Note: If the following flash access fails, try -m <vendor>:<mainboard>.
Reading old flash chip contents... done.
Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x48, failed byte count from 0x00000000-0x00000fff: 0x100
ERASE FAILED!
Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x48, failed byte count from 0x00000000-0x0000ffff: 0x100
ERASE FAILED!
FAILED!
Uh oh. Erase/write failed. Checking if anything changed.
Good. It seems nothing was changed.
Writing to the flash chip apparently didn't do anything.
This means we have to add special support for your board, programmer or flash chip.
Please report this on IRC at irc.freenode.net (channel #flashrom) or
mail flashrom at flashrom.org!
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You may now reboot or simply leave the machine running.

sudo flashrom -w hp.rom
flashrom v0.9.4-r1394 on Linux 3.0.0-12-generic (i686), built with libpci 3.1.7, GCC 4.6.1, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
Found chipset "NVIDIA CK804". Enabling flash write... OK.
WARNING: unexpected second chipset match: "NVIDIA CK804"
ignoring, please report lspci and board URL to flashrom at flashrom.org
with 'CHIPSET: your board name' in the subject line.
This chipset supports the following protocols: Non-SPI.
Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000.
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Reading old flash chip contents... done.
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
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