[coreboot] Patch set updated for coreboot: 265da9b Intel cpus: cache actual size of the Flash ROM device
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue Feb 28 13:04:36 CET 2012
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/641
-gerrit
commit 265da9b2659d2e18bb59e6a99792492fac71bdc8
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 28 00:24:15 2012 +0200
Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.
Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.
Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/car/cache_as_ram_ht.inc | 9 ++++++---
src/mainboard/Kconfig | 4 ++++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 08f5b11..ed207db 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -25,6 +25,9 @@
#define CPU_MAXPHYADDR 36
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+/* Base address to cache all of Flash ROM, just below 4GB. */
+#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
+
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -203,13 +206,13 @@ clear_mtrrs:
movl $CPU_PHYSMASK_HI, %edx
wrmsr
- /* Enable caching and Speculative Reads for the last 4MB. */
+ /* Enable caching and Speculative Reads for Flash ROM device. */
movl $MTRRphysBase_MSR(1), %ecx
- movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+ movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
- movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index cc4e14f..a34bd85 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -285,6 +285,10 @@ config ROM_SIZE
default 0x800000 if COREBOOT_ROMSIZE_KB_8192
default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
+config CACHE_ROM_SIZE
+ hex
+ default ROM_SIZE
+
config ENABLE_POWER_BUTTON
bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
default y if POWER_BUTTON_DEFAULT_ENABLE
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